src/cpu/o3/iew.hh

   1 /*
   2  * Copyright (c) 2010-2012, 2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_O3_IEW_HH__
  44 #define __CPU_O3_IEW_HH__
  45
  46 #include <queue>
  47 #include <set>
  48
  49 #include "base/statistics.hh"
  50 #include "cpu/o3/comm.hh"
  51 #include "cpu/o3/lsq.hh"
  52 #include "cpu/o3/scoreboard.hh"
  53 #include "cpu/timebuf.hh"
  54 #include "debug/IEW.hh"
  55 #include "sim/probe/probe.hh"
  56
  57 struct DerivO3CPUParams;
  58 class FUPool;
  59
  60 /**
  61  * DefaultIEW handles both single threaded and SMT IEW
  62  * (issue/execute/writeback).  It handles the dispatching of
  63  * instructions to the LSQ/IQ as part of the issue stage, and has the
  64  * IQ try to issue instructions each cycle. The execute latency is
  65  * actually tied into the issue latency to allow the IQ to be able to
  66  * do back-to-back scheduling without having to speculatively schedule
  67  * instructions. This happens by having the IQ have access to the
  68  * functional units, and the IQ gets the execution latencies from the
  69  * FUs when it issues instructions. Instructions reach the execute
  70  * stage on the last cycle of their execution, which is when the IQ
  71  * knows to wake up any dependent instructions, allowing back to back
  72  * scheduling. The execute portion of IEW separates memory
  73  * instructions from non-memory instructions, either telling the LSQ
  74  * to execute the instruction, or executing the instruction directly.
  75  * The writeback portion of IEW completes the instructions by waking
  76  * up any dependents, and marking the register ready on the
  77  * scoreboard.
  78  */
  79 template<class Impl>
  80 class DefaultIEW
  81 {
  82   private:
  83     //Typedefs from Impl
  84     typedef typename Impl::CPUPol CPUPol;
  85     typedef typename Impl::DynInstPtr DynInstPtr;
  86     typedef typename Impl::O3CPU O3CPU;
  87
  88     typedef typename CPUPol::IQ IQ;
  89     typedef typename CPUPol::RenameMap RenameMap;
  90     typedef typename CPUPol::LSQ LSQ;
  91
  92     typedef typename CPUPol::TimeStruct TimeStruct;
  93     typedef typename CPUPol::IEWStruct IEWStruct;
  94     typedef typename CPUPol::RenameStruct RenameStruct;
  95     typedef typename CPUPol::IssueStruct IssueStruct;
  96
  97   public:
  98     /** Overall IEW stage status. Used to determine if the CPU can
  99      * deschedule itself due to a lack of activity.
 100      */
 101     enum Status {
 102         Active,
 103         Inactive
 104     };
 105
 106     /** Status for Issue, Execute, and Writeback stages. */
 107     enum StageStatus {
 108         Running,
 109         Blocked,
 110         Idle,
 111         StartSquash,
 112         Squashing,
 113         Unblocking
 114     };
 115
 116   private:
 117     /** Overall stage status. */
 118     Status _status;
 119     /** Dispatch status. */
 120     StageStatus dispatchStatus[Impl::MaxThreads];
 121     /** Execute status. */
 122     StageStatus exeStatus;
 123     /** Writeback status. */
 124     StageStatus wbStatus;
 125
 126     /** Probe points. */
 127     ProbePointArg<DynInstPtr> *ppMispredict;
 128     ProbePointArg<DynInstPtr> *ppDispatch;
 129     /** To probe when instruction execution begins. */
 130     ProbePointArg<DynInstPtr> *ppExecute;
 131     /** To probe when instruction execution is complete. */
 132     ProbePointArg<DynInstPtr> *ppToCommit;
 133
 134   public:
 135     /** Constructs a DefaultIEW with the given parameters. */
 136     DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
 137
 138     /** Returns the name of the DefaultIEW stage. */
 139     std::string name() const;
 140
 141     /** Registers statistics. */
 142     void regStats();
 143
 144     /** Registers probes. */
 145     void regProbePoints();
 146
 147     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
 148     void startupStage();
 149
 150     /** Clear all thread-specific states */
 151     void clearStates(ThreadID tid);
 152
 153     /** Sets main time buffer used for backwards communication. */
 154     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 155
 156     /** Sets time buffer for getting instructions coming from rename. */
 157     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 158
 159     /** Sets time buffer to pass on instructions to commit. */
 160     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 161
 162     /** Sets pointer to list of active threads. */
 163     void setActiveThreads(std::list<ThreadID> *at_ptr);
 164
 165     /** Sets pointer to the scoreboard. */
 166     void setScoreboard(Scoreboard *sb_ptr);
 167
 168     /** Perform sanity checks after a drain. */
 169     void drainSanityCheck() const;
 170
 171     /** Has the stage drained? */
 172     bool isDrained() const;
 173
 174     /** Takes over from another CPU's thread. */
 175     void takeOverFrom();
 176
 177     /** Squashes instructions in IEW for a specific thread. */
 178     void squash(ThreadID tid);
 179
 180     /** Wakes all dependents of a completed instruction. */
 181     void wakeDependents(const DynInstPtr &inst);
 182
 183     /** Tells memory dependence unit that a memory instruction needs to be
 184      * rescheduled. It will re-execute once replayMemInst() is called.
 185      */
 186     void rescheduleMemInst(const DynInstPtr &inst);
 187
 188     /** Re-executes all rescheduled memory instructions. */
 189     void replayMemInst(const DynInstPtr &inst);
 190
 191     /** Moves memory instruction onto the list of cache blocked instructions */
 192     void blockMemInst(const DynInstPtr &inst);
 193
 194     /** Notifies that the cache has become unblocked */
 195     void cacheUnblocked();
 196
 197     /** Sends an instruction to commit through the time buffer. */
 198     void instToCommit(const DynInstPtr &inst);
 199
 200     /** Inserts unused instructions of a thread into the skid buffer. */
 201     void skidInsert(ThreadID tid);
 202
 203     /** Returns the max of the number of entries in all of the skid buffers. */
 204     int skidCount();
 205
 206     /** Returns if all of the skid buffers are empty. */
 207     bool skidsEmpty();
 208
 209     /** Updates overall IEW status based on all of the stages' statuses. */
 210     void updateStatus();
 211
 212     /** Resets entries of the IQ and the LSQ. */
 213     void resetEntries();
 214
 215     /** Tells the CPU to wakeup if it has descheduled itself due to no
 216      * activity. Used mainly by the LdWritebackEvent.
 217      */
 218     void wakeCPU();
 219
 220     /** Reports to the CPU that there is activity this cycle. */
 221     void activityThisCycle();
 222
 223     /** Tells CPU that the IEW stage is active and running. */
 224     inline void activateStage();
 225
 226     /** Tells CPU that the IEW stage is inactive and idle. */
 227     inline void deactivateStage();
 228
 229     /** Returns if the LSQ has any stores to writeback. */
 230     bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 231
 232     /** Returns if the LSQ has any stores to writeback. */
 233     bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
 234
 235     /** Check misprediction  */
 236     void checkMisprediction(const DynInstPtr &inst);
 237
 238   private:
 239     /** Sends commit proper information for a squash due to a branch
 240      * mispredict.
 241      */
 242     void squashDueToBranch(const DynInstPtr &inst, ThreadID tid);
 243
 244     /** Sends commit proper information for a squash due to a memory order
 245      * violation.
 246      */
 247     void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid);
 248
 249     /** Sets Dispatch to blocked, and signals back to other stages to block. */
 250     void block(ThreadID tid);
 251
 252     /** Unblocks Dispatch if the skid buffer is empty, and signals back to
 253      * other stages to unblock.
 254      */
 255     void unblock(ThreadID tid);
 256
 257     /** Determines proper actions to take given Dispatch's status. */
 258     void dispatch(ThreadID tid);
 259
 260     /** Dispatches instructions to IQ and LSQ. */
 261     void dispatchInsts(ThreadID tid);
 262
 263     /** Executes instructions. In the case of memory operations, it informs the
 264      * LSQ to execute the instructions. Also handles any redirects that occur
 265      * due to the executed instructions.
 266      */
 267     void executeInsts();
 268
 269     /** Writebacks instructions. In our model, the instruction's execute()
 270      * function atomically reads registers, executes, and writes registers.
 271      * Thus this writeback only wakes up dependent instructions, and informs
 272      * the scoreboard of registers becoming ready.
 273      */
 274     void writebackInsts();
 275
 276     /** Returns the number of valid, non-squashed instructions coming from
 277      * rename to dispatch.
 278      */
 279     unsigned validInstsFromRename();
 280
 281     /** Checks if any of the stall conditions are currently true. */
 282     bool checkStall(ThreadID tid);
 283
 284     /** Processes inputs and changes state accordingly. */
 285     void checkSignalsAndUpdate(ThreadID tid);
 286
 287     /** Removes instructions from rename from a thread's instruction list. */
 288     void emptyRenameInsts(ThreadID tid);
 289
 290     /** Sorts instructions coming from rename into lists separated by thread. */
 291     void sortInsts();
 292
 293   public:
 294     /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
 295      * Writeback to run for one cycle.
 296      */
 297     void tick();
 298
 299   private:
 300     /** Updates execution stats based on the instruction. */
 301     void updateExeInstStats(const DynInstPtr &inst);
 302
 303     /** Pointer to main time buffer used for backwards communication. */
 304     TimeBuffer<TimeStruct> *timeBuffer;
 305
 306     /** Wire to write information heading to previous stages. */
 307     typename TimeBuffer<TimeStruct>::wire toFetch;
 308
 309     /** Wire to get commit's output from backwards time buffer. */
 310     typename TimeBuffer<TimeStruct>::wire fromCommit;
 311
 312     /** Wire to write information heading to previous stages. */
 313     typename TimeBuffer<TimeStruct>::wire toRename;
 314
 315     /** Rename instruction queue interface. */
 316     TimeBuffer<RenameStruct> *renameQueue;
 317
 318     /** Wire to get rename's output from rename queue. */
 319     typename TimeBuffer<RenameStruct>::wire fromRename;
 320
 321     /** Issue stage queue. */
 322     TimeBuffer<IssueStruct> issueToExecQueue;
 323
 324     /** Wire to read information from the issue stage time queue. */
 325     typename TimeBuffer<IssueStruct>::wire fromIssue;
 326
 327     /**
 328      * IEW stage time buffer.  Holds ROB indices of instructions that
 329      * can be marked as completed.
 330      */
 331     TimeBuffer<IEWStruct> *iewQueue;
 332
 333     /** Wire to write infromation heading to commit. */
 334     typename TimeBuffer<IEWStruct>::wire toCommit;
 335
 336     /** Queue of all instructions coming from rename this cycle. */
 337     std::queue<DynInstPtr> insts[Impl::MaxThreads];
 338
 339     /** Skid buffer between rename and IEW. */
 340     std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
 341
 342     /** Scoreboard pointer. */
 343     Scoreboard* scoreboard;
 344
 345   private:
 346     /** CPU pointer. */
 347     O3CPU *cpu;
 348
 349     /** Records if IEW has written to the time buffer this cycle, so that the
 350      * CPU can deschedule itself if there is no activity.
 351      */
 352     bool wroteToTimeBuffer;
 353
 354     /** Debug function to print instructions that are issued this cycle. */
 355     void printAvailableInsts();
 356
 357   public:
 358     /** Instruction queue. */
 359     IQ instQueue;
 360
 361     /** Load / store queue. */
 362     LSQ ldstQueue;
 363
 364     /** Pointer to the functional unit pool. */
 365     FUPool *fuPool;
 366     /** Records if the LSQ needs to be updated on the next cycle, so that
 367      * IEW knows if there will be activity on the next cycle.
 368      */
 369     bool updateLSQNextCycle;
 370
 371   private:
 372     /** Records if there is a fetch redirect on this cycle for each thread. */
 373     bool fetchRedirect[Impl::MaxThreads];
 374
 375     /** Records if the queues have been changed (inserted or issued insts),
 376      * so that IEW knows to broadcast the updated amount of free entries.
 377      */
 378     bool updatedQueues;
 379
 380     /** Commit to IEW delay. */
 381     Cycles commitToIEWDelay;
 382
 383     /** Rename to IEW delay. */
 384     Cycles renameToIEWDelay;
 385
 386     /**
 387      * Issue to execute delay. What this actually represents is
 388      * the amount of time it takes for an instruction to wake up, be
 389      * scheduled, and sent to a FU for execution.
 390      */
 391     Cycles issueToExecuteDelay;
 392
 393     /** Width of dispatch, in instructions. */
 394     unsigned dispatchWidth;
 395
 396     /** Width of issue, in instructions. */
 397     unsigned issueWidth;
 398
 399     /** Index into queue of instructions being written back. */
 400     unsigned wbNumInst;
 401
 402     /** Cycle number within the queue of instructions being written back.
 403      * Used in case there are too many instructions writing back at the current
 404      * cycle and writesbacks need to be scheduled for the future. See comments
 405      * in instToCommit().
 406      */
 407     unsigned wbCycle;
 408
 409     /** Writeback width. */
 410     unsigned wbWidth;
 411
 412     /** Number of active threads. */
 413     ThreadID numThreads;
 414
 415     /** Pointer to list of active threads. */
 416     std::list<ThreadID> *activeThreads;
 417
 418     /** Maximum size of the skid buffer. */
 419     unsigned skidBufferMax;
 420
 421     /** Stat for total number of idle cycles. */
 422     Stats::Scalar iewIdleCycles;
 423     /** Stat for total number of squashing cycles. */
 424     Stats::Scalar iewSquashCycles;
 425     /** Stat for total number of blocking cycles. */
 426     Stats::Scalar iewBlockCycles;
 427     /** Stat for total number of unblocking cycles. */
 428     Stats::Scalar iewUnblockCycles;
 429     /** Stat for total number of instructions dispatched. */
 430     Stats::Scalar iewDispatchedInsts;
 431     /** Stat for total number of squashed instructions dispatch skips. */
 432     Stats::Scalar iewDispSquashedInsts;
 433     /** Stat for total number of dispatched load instructions. */
 434     Stats::Scalar iewDispLoadInsts;
 435     /** Stat for total number of dispatched store instructions. */
 436     Stats::Scalar iewDispStoreInsts;
 437     /** Stat for total number of dispatched non speculative instructions. */
 438     Stats::Scalar iewDispNonSpecInsts;
 439     /** Stat for number of times the IQ becomes full. */
 440     Stats::Scalar iewIQFullEvents;
 441     /** Stat for number of times the LSQ becomes full. */
 442     Stats::Scalar iewLSQFullEvents;
 443     /** Stat for total number of memory ordering violation events. */
 444     Stats::Scalar memOrderViolationEvents;
 445     /** Stat for total number of incorrect predicted taken branches. */
 446     Stats::Scalar predictedTakenIncorrect;
 447     /** Stat for total number of incorrect predicted not taken branches. */
 448     Stats::Scalar predictedNotTakenIncorrect;
 449     /** Stat for total number of mispredicted branches detected at execute. */
 450     Stats::Formula branchMispredicts;
 451
 452     /** Stat for total number of executed instructions. */
 453     Stats::Scalar iewExecutedInsts;
 454     /** Stat for total number of executed load instructions. */
 455     Stats::Vector iewExecLoadInsts;
 456     /** Stat for total number of executed store instructions. */
 457 //    Stats::Scalar iewExecStoreInsts;
 458     /** Stat for total number of squashed instructions skipped at execute. */
 459     Stats::Scalar iewExecSquashedInsts;
 460     /** Number of executed software prefetches. */
 461     Stats::Vector iewExecutedSwp;
 462     /** Number of executed nops. */
 463     Stats::Vector iewExecutedNop;
 464     /** Number of executed meomory references. */
 465     Stats::Vector iewExecutedRefs;
 466     /** Number of executed branches. */
 467     Stats::Vector iewExecutedBranches;
 468     /** Number of executed store instructions. */
 469     Stats::Formula iewExecStoreInsts;
 470     /** Number of instructions executed per cycle. */
 471     Stats::Formula iewExecRate;
 472
 473     /** Number of instructions sent to commit. */
 474     Stats::Vector iewInstsToCommit;
 475     /** Number of instructions that writeback. */
 476     Stats::Vector writebackCount;
 477     /** Number of instructions that wake consumers. */
 478     Stats::Vector producerInst;
 479     /** Number of instructions that wake up from producers. */
 480     Stats::Vector consumerInst;
 481     /** Number of instructions per cycle written back. */
 482     Stats::Formula wbRate;
 483     /** Average number of woken instructions per writeback. */
 484     Stats::Formula wbFanout;
 485 };
 486
 487 #endif // __CPU_O3_IEW_HH__