src/cpu/o3/iew.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_O3_IEW_HH__
  32 #define __CPU_O3_IEW_HH__
  33
  34 #include <queue>
  35
  36 #include "base/statistics.hh"
  37 #include "base/timebuf.hh"
  38 #include "config/full_system.hh"
  39 #include "cpu/o3/comm.hh"
  40 #include "cpu/o3/scoreboard.hh"
  41 #include "cpu/o3/lsq.hh"
  42
  43 class FUPool;
  44
  45 /**
  46  * DefaultIEW handles both single threaded and SMT IEW
  47  * (issue/execute/writeback).  It handles the dispatching of
  48  * instructions to the LSQ/IQ as part of the issue stage, and has the
  49  * IQ try to issue instructions each cycle. The execute latency is
  50  * actually tied into the issue latency to allow the IQ to be able to
  51  * do back-to-back scheduling without having to speculatively schedule
  52  * instructions. This happens by having the IQ have access to the
  53  * functional units, and the IQ gets the execution latencies from the
  54  * FUs when it issues instructions. Instructions reach the execute
  55  * stage on the last cycle of their execution, which is when the IQ
  56  * knows to wake up any dependent instructions, allowing back to back
  57  * scheduling. The execute portion of IEW separates memory
  58  * instructions from non-memory instructions, either telling the LSQ
  59  * to execute the instruction, or executing the instruction directly.
  60  * The writeback portion of IEW completes the instructions by waking
  61  * up any dependents, and marking the register ready on the
  62  * scoreboard.
  63  */
  64 template<class Impl>
  65 class DefaultIEW
  66 {
  67   private:
  68     //Typedefs from Impl
  69     typedef typename Impl::CPUPol CPUPol;
  70     typedef typename Impl::DynInstPtr DynInstPtr;
  71     typedef typename Impl::FullCPU FullCPU;
  72     typedef typename Impl::Params Params;
  73
  74     typedef typename CPUPol::IQ IQ;
  75     typedef typename CPUPol::RenameMap RenameMap;
  76     typedef typename CPUPol::LSQ LSQ;
  77
  78     typedef typename CPUPol::TimeStruct TimeStruct;
  79     typedef typename CPUPol::IEWStruct IEWStruct;
  80     typedef typename CPUPol::RenameStruct RenameStruct;
  81     typedef typename CPUPol::IssueStruct IssueStruct;
  82
  83     friend class Impl::FullCPU;
  84     friend class CPUPol::IQ;
  85
  86   public:
  87     /** Overall IEW stage status. Used to determine if the CPU can
  88      * deschedule itself due to a lack of activity.
  89      */
  90     enum Status {
  91         Active,
  92         Inactive
  93     };
  94
  95     /** Status for Issue, Execute, and Writeback stages. */
  96     enum StageStatus {
  97         Running,
  98         Blocked,
  99         Idle,
 100         StartSquash,
 101         Squashing,
 102         Unblocking
 103     };
 104
 105   private:
 106     /** Overall stage status. */
 107     Status _status;
 108     /** Dispatch status. */
 109     StageStatus dispatchStatus[Impl::MaxThreads];
 110     /** Execute status. */
 111     StageStatus exeStatus;
 112     /** Writeback status. */
 113     StageStatus wbStatus;
 114
 115   public:
 116     /** Constructs a DefaultIEW with the given parameters. */
 117     DefaultIEW(Params *params);
 118
 119     /** Returns the name of the DefaultIEW stage. */
 120     std::string name() const;
 121
 122     /** Registers statistics. */
 123     void regStats();
 124
 125     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
 126     void initStage();
 127
 128     /** Sets CPU pointer for IEW, IQ, and LSQ. */
 129     void setCPU(FullCPU *cpu_ptr);
 130
 131     /** Sets main time buffer used for backwards communication. */
 132     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 133
 134     /** Sets time buffer for getting instructions coming from rename. */
 135     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 136
 137     /** Sets time buffer to pass on instructions to commit. */
 138     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 139
 140     /** Sets pointer to list of active threads. */
 141     void setActiveThreads(std::list<unsigned> *at_ptr);
 142
 143     /** Sets pointer to the scoreboard. */
 144     void setScoreboard(Scoreboard *sb_ptr);
 145
 146     void switchOut();
 147
 148     void doSwitchOut();
 149
 150     void takeOverFrom();
 151
 152     bool isSwitchedOut() { return switchedOut; }
 153
 154     /** Sets page table pointer within LSQ. */
 155 //    void setPageTable(PageTable *pt_ptr);
 156
 157     /** Squashes instructions in IEW for a specific thread. */
 158     void squash(unsigned tid);
 159
 160     /** Wakes all dependents of a completed instruction. */
 161     void wakeDependents(DynInstPtr &inst);
 162
 163     /** Tells memory dependence unit that a memory instruction needs to be
 164      * rescheduled. It will re-execute once replayMemInst() is called.
 165      */
 166     void rescheduleMemInst(DynInstPtr &inst);
 167
 168     /** Re-executes all rescheduled memory instructions. */
 169     void replayMemInst(DynInstPtr &inst);
 170
 171     /** Sends an instruction to commit through the time buffer. */
 172     void instToCommit(DynInstPtr &inst);
 173
 174     /** Inserts unused instructions of a thread into the skid buffer. */
 175     void skidInsert(unsigned tid);
 176
 177     /** Returns the max of the number of entries in all of the skid buffers. */
 178     int skidCount();
 179
 180     /** Returns if all of the skid buffers are empty. */
 181     bool skidsEmpty();
 182
 183     /** Updates overall IEW status based on all of the stages' statuses. */
 184     void updateStatus();
 185
 186     /** Resets entries of the IQ and the LSQ. */
 187     void resetEntries();
 188
 189     /** Tells the CPU to wakeup if it has descheduled itself due to no
 190      * activity. Used mainly by the LdWritebackEvent.
 191      */
 192     void wakeCPU();
 193
 194     /** Reports to the CPU that there is activity this cycle. */
 195     void activityThisCycle();
 196
 197     /** Tells CPU that the IEW stage is active and running. */
 198     inline void activateStage();
 199
 200     /** Tells CPU that the IEW stage is inactive and idle. */
 201     inline void deactivateStage();
 202
 203     /** Returns if the LSQ has any stores to writeback. */
 204     bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 205
 206   private:
 207     /** Sends commit proper information for a squash due to a branch
 208      * mispredict.
 209      */
 210     void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
 211
 212     /** Sends commit proper information for a squash due to a memory order
 213      * violation.
 214      */
 215     void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
 216
 217     /** Sends commit proper information for a squash due to memory becoming
 218      * blocked (younger issued instructions must be retried).
 219      */
 220     void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
 221
 222     /** Sets Dispatch to blocked, and signals back to other stages to block. */
 223     void block(unsigned thread_id);
 224
 225     /** Unblocks Dispatch if the skid buffer is empty, and signals back to
 226      * other stages to unblock.
 227      */
 228     void unblock(unsigned thread_id);
 229
 230     /** Determines proper actions to take given Dispatch's status. */
 231     void dispatch(unsigned tid);
 232
 233     /** Dispatches instructions to IQ and LSQ. */
 234     void dispatchInsts(unsigned tid);
 235
 236     /** Executes instructions. In the case of memory operations, it informs the
 237      * LSQ to execute the instructions. Also handles any redirects that occur
 238      * due to the executed instructions.
 239      */
 240     void executeInsts();
 241
 242     /** Writebacks instructions. In our model, the instruction's execute()
 243      * function atomically reads registers, executes, and writes registers.
 244      * Thus this writeback only wakes up dependent instructions, and informs
 245      * the scoreboard of registers becoming ready.
 246      */
 247     void writebackInsts();
 248
 249     /** Returns the number of valid, non-squashed instructions coming from
 250      * rename to dispatch.
 251      */
 252     unsigned validInstsFromRename();
 253
 254     /** Reads the stall signals. */
 255     void readStallSignals(unsigned tid);
 256
 257     /** Checks if any of the stall conditions are currently true. */
 258     bool checkStall(unsigned tid);
 259
 260     /** Processes inputs and changes state accordingly. */
 261     void checkSignalsAndUpdate(unsigned tid);
 262
 263     /** Sorts instructions coming from rename into lists separated by thread. */
 264     void sortInsts();
 265
 266   public:
 267     /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
 268      * Writeback to run for one cycle.
 269      */
 270     void tick();
 271
 272   private:
 273     void updateExeInstStats(DynInstPtr &inst);
 274
 275     /** Pointer to main time buffer used for backwards communication. */
 276     TimeBuffer<TimeStruct> *timeBuffer;
 277
 278     /** Wire to write information heading to previous stages. */
 279     typename TimeBuffer<TimeStruct>::wire toFetch;
 280
 281     /** Wire to get commit's output from backwards time buffer. */
 282     typename TimeBuffer<TimeStruct>::wire fromCommit;
 283
 284     /** Wire to write information heading to previous stages. */
 285     typename TimeBuffer<TimeStruct>::wire toRename;
 286
 287     /** Rename instruction queue interface. */
 288     TimeBuffer<RenameStruct> *renameQueue;
 289
 290     /** Wire to get rename's output from rename queue. */
 291     typename TimeBuffer<RenameStruct>::wire fromRename;
 292
 293     /** Issue stage queue. */
 294     TimeBuffer<IssueStruct> issueToExecQueue;
 295
 296     /** Wire to read information from the issue stage time queue. */
 297     typename TimeBuffer<IssueStruct>::wire fromIssue;
 298
 299     /**
 300      * IEW stage time buffer.  Holds ROB indices of instructions that
 301      * can be marked as completed.
 302      */
 303     TimeBuffer<IEWStruct> *iewQueue;
 304
 305     /** Wire to write infromation heading to commit. */
 306     typename TimeBuffer<IEWStruct>::wire toCommit;
 307
 308     /** Queue of all instructions coming from rename this cycle. */
 309     std::queue<DynInstPtr> insts[Impl::MaxThreads];
 310
 311     /** Skid buffer between rename and IEW. */
 312     std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
 313
 314     /** Scoreboard pointer. */
 315     Scoreboard* scoreboard;
 316
 317   public:
 318     /** Instruction queue. */
 319     IQ instQueue;
 320
 321     /** Load / store queue. */
 322     LSQ ldstQueue;
 323
 324     /** Pointer to the functional unit pool. */
 325     FUPool *fuPool;
 326
 327   private:
 328     /** CPU pointer. */
 329     FullCPU *cpu;
 330
 331     /** Records if IEW has written to the time buffer this cycle, so that the
 332      * CPU can deschedule itself if there is no activity.
 333      */
 334     bool wroteToTimeBuffer;
 335
 336     /** Source of possible stalls. */
 337     struct Stalls {
 338         bool commit;
 339     };
 340
 341     /** Stages that are telling IEW to stall. */
 342     Stalls stalls[Impl::MaxThreads];
 343
 344     /** Debug function to print instructions that are issued this cycle. */
 345     void printAvailableInsts();
 346
 347   public:
 348     /** Records if the LSQ needs to be updated on the next cycle, so that
 349      * IEW knows if there will be activity on the next cycle.
 350      */
 351     bool updateLSQNextCycle;
 352
 353   private:
 354     /** Records if there is a fetch redirect on this cycle for each thread. */
 355     bool fetchRedirect[Impl::MaxThreads];
 356
 357     /** Used to track if all instructions have been dispatched this cycle.
 358      * If they have not, then blocking must have occurred, and the instructions
 359      * would already be added to the skid buffer.
 360      * @todo: Fix this hack.
 361      */
 362     bool dispatchedAllInsts;
 363
 364     /** Records if the queues have been changed (inserted or issued insts),
 365      * so that IEW knows to broadcast the updated amount of free entries.
 366      */
 367     bool updatedQueues;
 368
 369     /** Commit to IEW delay, in ticks. */
 370     unsigned commitToIEWDelay;
 371
 372     /** Rename to IEW delay, in ticks. */
 373     unsigned renameToIEWDelay;
 374
 375     /**
 376      * Issue to execute delay, in ticks.  What this actually represents is
 377      * the amount of time it takes for an instruction to wake up, be
 378      * scheduled, and sent to a FU for execution.
 379      */
 380     unsigned issueToExecuteDelay;
 381
 382     /** Width of issue's read path, in instructions.  The read path is both
 383      *  the skid buffer and the rename instruction queue.
 384      *  Note to self: is this really different than issueWidth?
 385      */
 386     unsigned issueReadWidth;
 387
 388     /** Width of issue, in instructions. */
 389     unsigned issueWidth;
 390
 391     /** Width of execute, in instructions.  Might make more sense to break
 392      *  down into FP vs int.
 393      */
 394     unsigned executeWidth;
 395
 396     /** Index into queue of instructions being written back. */
 397     unsigned wbNumInst;
 398
 399     /** Cycle number within the queue of instructions being written back.
 400      * Used in case there are too many instructions writing back at the current
 401      * cycle and writesbacks need to be scheduled for the future. See comments
 402      * in instToCommit().
 403      */
 404     unsigned wbCycle;
 405
 406     /** Number of active threads. */
 407     unsigned numThreads;
 408
 409     /** Pointer to list of active threads. */
 410     std::list<unsigned> *activeThreads;
 411
 412     /** Maximum size of the skid buffer. */
 413     unsigned skidBufferMax;
 414
 415     bool switchedOut;
 416
 417     /** Stat for total number of idle cycles. */
 418     Stats::Scalar<> iewIdleCycles;
 419     /** Stat for total number of squashing cycles. */
 420     Stats::Scalar<> iewSquashCycles;
 421     /** Stat for total number of blocking cycles. */
 422     Stats::Scalar<> iewBlockCycles;
 423     /** Stat for total number of unblocking cycles. */
 424     Stats::Scalar<> iewUnblockCycles;
 425     /** Stat for total number of instructions dispatched. */
 426     Stats::Scalar<> iewDispatchedInsts;
 427     /** Stat for total number of squashed instructions dispatch skips. */
 428     Stats::Scalar<> iewDispSquashedInsts;
 429     /** Stat for total number of dispatched load instructions. */
 430     Stats::Scalar<> iewDispLoadInsts;
 431     /** Stat for total number of dispatched store instructions. */
 432     Stats::Scalar<> iewDispStoreInsts;
 433     /** Stat for total number of dispatched non speculative instructions. */
 434     Stats::Scalar<> iewDispNonSpecInsts;
 435     /** Stat for number of times the IQ becomes full. */
 436     Stats::Scalar<> iewIQFullEvents;
 437     /** Stat for number of times the LSQ becomes full. */
 438     Stats::Scalar<> iewLSQFullEvents;
 439     /** Stat for total number of executed instructions. */
 440     Stats::Scalar<> iewExecutedInsts;
 441     /** Stat for total number of executed load instructions. */
 442     Stats::Vector<> iewExecLoadInsts;
 443     /** Stat for total number of executed store instructions. */
 444 //    Stats::Scalar<> iewExecStoreInsts;
 445     /** Stat for total number of squashed instructions skipped at execute. */
 446     Stats::Scalar<> iewExecSquashedInsts;
 447     /** Stat for total number of memory ordering violation events. */
 448     Stats::Scalar<> memOrderViolationEvents;
 449     /** Stat for total number of incorrect predicted taken branches. */
 450     Stats::Scalar<> predictedTakenIncorrect;
 451     /** Stat for total number of incorrect predicted not taken branches. */
 452     Stats::Scalar<> predictedNotTakenIncorrect;
 453     /** Stat for total number of mispredicted branches detected at execute. */
 454     Stats::Formula branchMispredicts;
 455
 456     Stats::Vector<> exeSwp;
 457     Stats::Vector<> exeNop;
 458     Stats::Vector<> exeRefs;
 459     Stats::Vector<> exeBranches;
 460
 461 //    Stats::Vector<> issued_ops;
 462 /*
 463     Stats::Vector<> stat_fu_busy;
 464     Stats::Vector2d<> stat_fuBusy;
 465     Stats::Vector<> dist_unissued;
 466     Stats::Vector2d<> stat_issued_inst_type;
 467 */
 468     Stats::Formula issueRate;
 469     Stats::Formula iewExecStoreInsts;
 470 //    Stats::Formula issue_op_rate;
 471 //    Stats::Formula fu_busy_rate;
 472
 473     Stats::Vector<> iewInstsToCommit;
 474     Stats::Vector<> writebackCount;
 475     Stats::Vector<> producerInst;
 476     Stats::Vector<> consumerInst;
 477     Stats::Vector<> wbPenalized;
 478
 479     Stats::Formula wbRate;
 480     Stats::Formula wbFanout;
 481     Stats::Formula wbPenalizedRate;
 482 };
 483
 484 #endif // __CPU_O3_IEW_HH__