src/cpu/o3/iew.hh

   1 /*
   2  * Copyright (c) 2010-2012, 2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_O3_IEW_HH__
  44 #define __CPU_O3_IEW_HH__
  45
  46 #include <queue>
  47 #include <set>
  48
  49 #include "base/statistics.hh"
  50 #include "cpu/o3/comm.hh"
  51 #include "cpu/o3/lsq.hh"
  52 #include "cpu/o3/scoreboard.hh"
  53 #include "cpu/timebuf.hh"
  54 #include "debug/IEW.hh"
  55 #include "sim/probe/probe.hh"
  56
  57 struct DerivO3CPUParams;
  58 class FUPool;
  59
  60 /**
  61  * DefaultIEW handles both single threaded and SMT IEW
  62  * (issue/execute/writeback).  It handles the dispatching of
  63  * instructions to the LSQ/IQ as part of the issue stage, and has the
  64  * IQ try to issue instructions each cycle. The execute latency is
  65  * actually tied into the issue latency to allow the IQ to be able to
  66  * do back-to-back scheduling without having to speculatively schedule
  67  * instructions. This happens by having the IQ have access to the
  68  * functional units, and the IQ gets the execution latencies from the
  69  * FUs when it issues instructions. Instructions reach the execute
  70  * stage on the last cycle of their execution, which is when the IQ
  71  * knows to wake up any dependent instructions, allowing back to back
  72  * scheduling. The execute portion of IEW separates memory
  73  * instructions from non-memory instructions, either telling the LSQ
  74  * to execute the instruction, or executing the instruction directly.
  75  * The writeback portion of IEW completes the instructions by waking
  76  * up any dependents, and marking the register ready on the
  77  * scoreboard.
  78  */
  79 template<class Impl>
  80 class DefaultIEW
  81 {
  82   private:
  83     //Typedefs from Impl
  84     typedef typename Impl::CPUPol CPUPol;
  85     typedef typename Impl::DynInstPtr DynInstPtr;
  86     typedef typename Impl::O3CPU O3CPU;
  87
  88     typedef typename CPUPol::IQ IQ;
  89     typedef typename CPUPol::RenameMap RenameMap;
  90     typedef typename CPUPol::LSQ LSQ;
  91
  92     typedef typename CPUPol::TimeStruct TimeStruct;
  93     typedef typename CPUPol::IEWStruct IEWStruct;
  94     typedef typename CPUPol::RenameStruct RenameStruct;
  95     typedef typename CPUPol::IssueStruct IssueStruct;
  96
  97   public:
  98     /** Overall IEW stage status. Used to determine if the CPU can
  99      * deschedule itself due to a lack of activity.
 100      */
 101     enum Status {
 102         Active,
 103         Inactive
 104     };
 105
 106     /** Status for Issue, Execute, and Writeback stages. */
 107     enum StageStatus {
 108         Running,
 109         Blocked,
 110         Idle,
 111         StartSquash,
 112         Squashing,
 113         Unblocking
 114     };
 115
 116   private:
 117     /** Overall stage status. */
 118     Status _status;
 119     /** Dispatch status. */
 120     StageStatus dispatchStatus[Impl::MaxThreads];
 121     /** Execute status. */
 122     StageStatus exeStatus;
 123     /** Writeback status. */
 124     StageStatus wbStatus;
 125
 126     /** Probe points. */
 127     ProbePointArg<DynInstPtr> *ppMispredict;
 128     ProbePointArg<DynInstPtr> *ppDispatch;
 129     /** To probe when instruction execution begins. */
 130     ProbePointArg<DynInstPtr> *ppExecute;
 131     /** To probe when instruction execution is complete. */
 132     ProbePointArg<DynInstPtr> *ppToCommit;
 133
 134   public:
 135     /** Constructs a DefaultIEW with the given parameters. */
 136     DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
 137
 138     /** Returns the name of the DefaultIEW stage. */
 139     std::string name() const;
 140
 141     /** Registers statistics. */
 142     void regStats();
 143
 144     /** Registers probes. */
 145     void regProbePoints();
 146
 147     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
 148     void startupStage();
 149
 150     /** Sets main time buffer used for backwards communication. */
 151     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 152
 153     /** Sets time buffer for getting instructions coming from rename. */
 154     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 155
 156     /** Sets time buffer to pass on instructions to commit. */
 157     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 158
 159     /** Sets pointer to list of active threads. */
 160     void setActiveThreads(std::list<ThreadID> *at_ptr);
 161
 162     /** Sets pointer to the scoreboard. */
 163     void setScoreboard(Scoreboard *sb_ptr);
 164
 165     /** Perform sanity checks after a drain. */
 166     void drainSanityCheck() const;
 167
 168     /** Has the stage drained? */
 169     bool isDrained() const;
 170
 171     /** Takes over from another CPU's thread. */
 172     void takeOverFrom();
 173
 174     /** Squashes instructions in IEW for a specific thread. */
 175     void squash(ThreadID tid);
 176
 177     /** Wakes all dependents of a completed instruction. */
 178     void wakeDependents(const DynInstPtr &inst);
 179
 180     /** Tells memory dependence unit that a memory instruction needs to be
 181      * rescheduled. It will re-execute once replayMemInst() is called.
 182      */
 183     void rescheduleMemInst(const DynInstPtr &inst);
 184
 185     /** Re-executes all rescheduled memory instructions. */
 186     void replayMemInst(const DynInstPtr &inst);
 187
 188     /** Moves memory instruction onto the list of cache blocked instructions */
 189     void blockMemInst(const DynInstPtr &inst);
 190
 191     /** Notifies that the cache has become unblocked */
 192     void cacheUnblocked();
 193
 194     /** Sends an instruction to commit through the time buffer. */
 195     void instToCommit(const DynInstPtr &inst);
 196
 197     /** Inserts unused instructions of a thread into the skid buffer. */
 198     void skidInsert(ThreadID tid);
 199
 200     /** Returns the max of the number of entries in all of the skid buffers. */
 201     int skidCount();
 202
 203     /** Returns if all of the skid buffers are empty. */
 204     bool skidsEmpty();
 205
 206     /** Updates overall IEW status based on all of the stages' statuses. */
 207     void updateStatus();
 208
 209     /** Resets entries of the IQ and the LSQ. */
 210     void resetEntries();
 211
 212     /** Tells the CPU to wakeup if it has descheduled itself due to no
 213      * activity. Used mainly by the LdWritebackEvent.
 214      */
 215     void wakeCPU();
 216
 217     /** Reports to the CPU that there is activity this cycle. */
 218     void activityThisCycle();
 219
 220     /** Tells CPU that the IEW stage is active and running. */
 221     inline void activateStage();
 222
 223     /** Tells CPU that the IEW stage is inactive and idle. */
 224     inline void deactivateStage();
 225
 226     /** Returns if the LSQ has any stores to writeback. */
 227     bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 228
 229     /** Returns if the LSQ has any stores to writeback. */
 230     bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
 231
 232     /** Check misprediction  */
 233     void checkMisprediction(const DynInstPtr &inst);
 234
 235   private:
 236     /** Sends commit proper information for a squash due to a branch
 237      * mispredict.
 238      */
 239     void squashDueToBranch(const DynInstPtr &inst, ThreadID tid);
 240
 241     /** Sends commit proper information for a squash due to a memory order
 242      * violation.
 243      */
 244     void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid);
 245
 246     /** Sets Dispatch to blocked, and signals back to other stages to block. */
 247     void block(ThreadID tid);
 248
 249     /** Unblocks Dispatch if the skid buffer is empty, and signals back to
 250      * other stages to unblock.
 251      */
 252     void unblock(ThreadID tid);
 253
 254     /** Determines proper actions to take given Dispatch's status. */
 255     void dispatch(ThreadID tid);
 256
 257     /** Dispatches instructions to IQ and LSQ. */
 258     void dispatchInsts(ThreadID tid);
 259
 260     /** Executes instructions. In the case of memory operations, it informs the
 261      * LSQ to execute the instructions. Also handles any redirects that occur
 262      * due to the executed instructions.
 263      */
 264     void executeInsts();
 265
 266     /** Writebacks instructions. In our model, the instruction's execute()
 267      * function atomically reads registers, executes, and writes registers.
 268      * Thus this writeback only wakes up dependent instructions, and informs
 269      * the scoreboard of registers becoming ready.
 270      */
 271     void writebackInsts();
 272
 273     /** Returns the number of valid, non-squashed instructions coming from
 274      * rename to dispatch.
 275      */
 276     unsigned validInstsFromRename();
 277
 278     /** Checks if any of the stall conditions are currently true. */
 279     bool checkStall(ThreadID tid);
 280
 281     /** Processes inputs and changes state accordingly. */
 282     void checkSignalsAndUpdate(ThreadID tid);
 283
 284     /** Removes instructions from rename from a thread's instruction list. */
 285     void emptyRenameInsts(ThreadID tid);
 286
 287     /** Sorts instructions coming from rename into lists separated by thread. */
 288     void sortInsts();
 289
 290   public:
 291     /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
 292      * Writeback to run for one cycle.
 293      */
 294     void tick();
 295
 296   private:
 297     /** Updates execution stats based on the instruction. */
 298     void updateExeInstStats(const DynInstPtr &inst);
 299
 300     /** Pointer to main time buffer used for backwards communication. */
 301     TimeBuffer<TimeStruct> *timeBuffer;
 302
 303     /** Wire to write information heading to previous stages. */
 304     typename TimeBuffer<TimeStruct>::wire toFetch;
 305
 306     /** Wire to get commit's output from backwards time buffer. */
 307     typename TimeBuffer<TimeStruct>::wire fromCommit;
 308
 309     /** Wire to write information heading to previous stages. */
 310     typename TimeBuffer<TimeStruct>::wire toRename;
 311
 312     /** Rename instruction queue interface. */
 313     TimeBuffer<RenameStruct> *renameQueue;
 314
 315     /** Wire to get rename's output from rename queue. */
 316     typename TimeBuffer<RenameStruct>::wire fromRename;
 317
 318     /** Issue stage queue. */
 319     TimeBuffer<IssueStruct> issueToExecQueue;
 320
 321     /** Wire to read information from the issue stage time queue. */
 322     typename TimeBuffer<IssueStruct>::wire fromIssue;
 323
 324     /**
 325      * IEW stage time buffer.  Holds ROB indices of instructions that
 326      * can be marked as completed.
 327      */
 328     TimeBuffer<IEWStruct> *iewQueue;
 329
 330     /** Wire to write infromation heading to commit. */
 331     typename TimeBuffer<IEWStruct>::wire toCommit;
 332
 333     /** Queue of all instructions coming from rename this cycle. */
 334     std::queue<DynInstPtr> insts[Impl::MaxThreads];
 335
 336     /** Skid buffer between rename and IEW. */
 337     std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
 338
 339     /** Scoreboard pointer. */
 340     Scoreboard* scoreboard;
 341
 342   private:
 343     /** CPU pointer. */
 344     O3CPU *cpu;
 345
 346     /** Records if IEW has written to the time buffer this cycle, so that the
 347      * CPU can deschedule itself if there is no activity.
 348      */
 349     bool wroteToTimeBuffer;
 350
 351     /** Debug function to print instructions that are issued this cycle. */
 352     void printAvailableInsts();
 353
 354   public:
 355     /** Instruction queue. */
 356     IQ instQueue;
 357
 358     /** Load / store queue. */
 359     LSQ ldstQueue;
 360
 361     /** Pointer to the functional unit pool. */
 362     FUPool *fuPool;
 363     /** Records if the LSQ needs to be updated on the next cycle, so that
 364      * IEW knows if there will be activity on the next cycle.
 365      */
 366     bool updateLSQNextCycle;
 367
 368   private:
 369     /** Records if there is a fetch redirect on this cycle for each thread. */
 370     bool fetchRedirect[Impl::MaxThreads];
 371
 372     /** Records if the queues have been changed (inserted or issued insts),
 373      * so that IEW knows to broadcast the updated amount of free entries.
 374      */
 375     bool updatedQueues;
 376
 377     /** Commit to IEW delay. */
 378     Cycles commitToIEWDelay;
 379
 380     /** Rename to IEW delay. */
 381     Cycles renameToIEWDelay;
 382
 383     /**
 384      * Issue to execute delay. What this actually represents is
 385      * the amount of time it takes for an instruction to wake up, be
 386      * scheduled, and sent to a FU for execution.
 387      */
 388     Cycles issueToExecuteDelay;
 389
 390     /** Width of dispatch, in instructions. */
 391     unsigned dispatchWidth;
 392
 393     /** Width of issue, in instructions. */
 394     unsigned issueWidth;
 395
 396     /** Index into queue of instructions being written back. */
 397     unsigned wbNumInst;
 398
 399     /** Cycle number within the queue of instructions being written back.
 400      * Used in case there are too many instructions writing back at the current
 401      * cycle and writesbacks need to be scheduled for the future. See comments
 402      * in instToCommit().
 403      */
 404     unsigned wbCycle;
 405
 406     /** Writeback width. */
 407     unsigned wbWidth;
 408
 409     /** Number of active threads. */
 410     ThreadID numThreads;
 411
 412     /** Pointer to list of active threads. */
 413     std::list<ThreadID> *activeThreads;
 414
 415     /** Maximum size of the skid buffer. */
 416     unsigned skidBufferMax;
 417
 418     /** Stat for total number of idle cycles. */
 419     Stats::Scalar iewIdleCycles;
 420     /** Stat for total number of squashing cycles. */
 421     Stats::Scalar iewSquashCycles;
 422     /** Stat for total number of blocking cycles. */
 423     Stats::Scalar iewBlockCycles;
 424     /** Stat for total number of unblocking cycles. */
 425     Stats::Scalar iewUnblockCycles;
 426     /** Stat for total number of instructions dispatched. */
 427     Stats::Scalar iewDispatchedInsts;
 428     /** Stat for total number of squashed instructions dispatch skips. */
 429     Stats::Scalar iewDispSquashedInsts;
 430     /** Stat for total number of dispatched load instructions. */
 431     Stats::Scalar iewDispLoadInsts;
 432     /** Stat for total number of dispatched store instructions. */
 433     Stats::Scalar iewDispStoreInsts;
 434     /** Stat for total number of dispatched non speculative instructions. */
 435     Stats::Scalar iewDispNonSpecInsts;
 436     /** Stat for number of times the IQ becomes full. */
 437     Stats::Scalar iewIQFullEvents;
 438     /** Stat for number of times the LSQ becomes full. */
 439     Stats::Scalar iewLSQFullEvents;
 440     /** Stat for total number of memory ordering violation events. */
 441     Stats::Scalar memOrderViolationEvents;
 442     /** Stat for total number of incorrect predicted taken branches. */
 443     Stats::Scalar predictedTakenIncorrect;
 444     /** Stat for total number of incorrect predicted not taken branches. */
 445     Stats::Scalar predictedNotTakenIncorrect;
 446     /** Stat for total number of mispredicted branches detected at execute. */
 447     Stats::Formula branchMispredicts;
 448
 449     /** Stat for total number of executed instructions. */
 450     Stats::Scalar iewExecutedInsts;
 451     /** Stat for total number of executed load instructions. */
 452     Stats::Vector iewExecLoadInsts;
 453     /** Stat for total number of executed store instructions. */
 454 //    Stats::Scalar iewExecStoreInsts;
 455     /** Stat for total number of squashed instructions skipped at execute. */
 456     Stats::Scalar iewExecSquashedInsts;
 457     /** Number of executed software prefetches. */
 458     Stats::Vector iewExecutedSwp;
 459     /** Number of executed nops. */
 460     Stats::Vector iewExecutedNop;
 461     /** Number of executed meomory references. */
 462     Stats::Vector iewExecutedRefs;
 463     /** Number of executed branches. */
 464     Stats::Vector iewExecutedBranches;
 465     /** Number of executed store instructions. */
 466     Stats::Formula iewExecStoreInsts;
 467     /** Number of instructions executed per cycle. */
 468     Stats::Formula iewExecRate;
 469
 470     /** Number of instructions sent to commit. */
 471     Stats::Vector iewInstsToCommit;
 472     /** Number of instructions that writeback. */
 473     Stats::Vector writebackCount;
 474     /** Number of instructions that wake consumers. */
 475     Stats::Vector producerInst;
 476     /** Number of instructions that wake up from producers. */
 477     Stats::Vector consumerInst;
 478     /** Number of instructions per cycle written back. */
 479     Stats::Formula wbRate;
 480     /** Average number of woken instructions per writeback. */
 481     Stats::Formula wbFanout;
 482 };
 483
 484 #endif // __CPU_O3_IEW_HH__