src/cpu/o3/iew.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_O3_IEW_HH__
  32 #define __CPU_O3_IEW_HH__
  33
  34 #include "config/full_system.hh"
  35
  36 #include <queue>
  37
  38 #include "base/statistics.hh"
  39 #include "base/timebuf.hh"
  40 #include "cpu/o3/comm.hh"
  41 #include "cpu/o3/scoreboard.hh"
  42 #include "cpu/o3/lsq.hh"
  43
  44 class FUPool;
  45
  46 /**
  47  * DefaultIEW handles both single threaded and SMT IEW
  48  * (issue/execute/writeback).  It handles the dispatching of
  49  * instructions to the LSQ/IQ as part of the issue stage, and has the
  50  * IQ try to issue instructions each cycle. The execute latency is
  51  * actually tied into the issue latency to allow the IQ to be able to
  52  * do back-to-back scheduling without having to speculatively schedule
  53  * instructions. This happens by having the IQ have access to the
  54  * functional units, and the IQ gets the execution latencies from the
  55  * FUs when it issues instructions. Instructions reach the execute
  56  * stage on the last cycle of their execution, which is when the IQ
  57  * knows to wake up any dependent instructions, allowing back to back
  58  * scheduling. The execute portion of IEW separates memory
  59  * instructions from non-memory instructions, either telling the LSQ
  60  * to execute the instruction, or executing the instruction directly.
  61  * The writeback portion of IEW completes the instructions by waking
  62  * up any dependents, and marking the register ready on the
  63  * scoreboard.
  64  */
  65 template<class Impl>
  66 class DefaultIEW
  67 {
  68   private:
  69     //Typedefs from Impl
  70     typedef typename Impl::CPUPol CPUPol;
  71     typedef typename Impl::DynInstPtr DynInstPtr;
  72     typedef typename Impl::O3CPU O3CPU;
  73     typedef typename Impl::Params Params;
  74
  75     typedef typename CPUPol::IQ IQ;
  76     typedef typename CPUPol::RenameMap RenameMap;
  77     typedef typename CPUPol::LSQ LSQ;
  78
  79     typedef typename CPUPol::TimeStruct TimeStruct;
  80     typedef typename CPUPol::IEWStruct IEWStruct;
  81     typedef typename CPUPol::RenameStruct RenameStruct;
  82     typedef typename CPUPol::IssueStruct IssueStruct;
  83
  84     friend class Impl::O3CPU;
  85     friend class CPUPol::IQ;
  86
  87   public:
  88     /** Overall IEW stage status. Used to determine if the CPU can
  89      * deschedule itself due to a lack of activity.
  90      */
  91     enum Status {
  92         Active,
  93         Inactive
  94     };
  95
  96     /** Status for Issue, Execute, and Writeback stages. */
  97     enum StageStatus {
  98         Running,
  99         Blocked,
 100         Idle,
 101         StartSquash,
 102         Squashing,
 103         Unblocking
 104     };
 105
 106   private:
 107     /** Overall stage status. */
 108     Status _status;
 109     /** Dispatch status. */
 110     StageStatus dispatchStatus[Impl::MaxThreads];
 111     /** Execute status. */
 112     StageStatus exeStatus;
 113     /** Writeback status. */
 114     StageStatus wbStatus;
 115
 116   public:
 117     /** Constructs a DefaultIEW with the given parameters. */
 118     DefaultIEW(O3CPU *_cpu, Params *params);
 119
 120     /** Returns the name of the DefaultIEW stage. */
 121     std::string name() const;
 122
 123     /** Registers statistics. */
 124     void regStats();
 125
 126     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
 127     void initStage();
 128
 129     /** Returns the dcache port. */
 130     Port *getDcachePort() { return ldstQueue.getDcachePort(); }
 131
 132     /** Sets main time buffer used for backwards communication. */
 133     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 134
 135     /** Sets time buffer for getting instructions coming from rename. */
 136     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 137
 138     /** Sets time buffer to pass on instructions to commit. */
 139     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 140
 141     /** Sets pointer to list of active threads. */
 142     void setActiveThreads(std::list<unsigned> *at_ptr);
 143
 144     /** Sets pointer to the scoreboard. */
 145     void setScoreboard(Scoreboard *sb_ptr);
 146
 147     /** Drains IEW stage. */
 148     bool drain();
 149
 150     /** Resumes execution after a drain. */
 151     void resume();
 152
 153     /** Completes switch out of IEW stage. */
 154     void switchOut();
 155
 156     /** Takes over from another CPU's thread. */
 157     void takeOverFrom();
 158
 159     /** Returns if IEW is switched out. */
 160     bool isSwitchedOut() { return switchedOut; }
 161
 162     /** Squashes instructions in IEW for a specific thread. */
 163     void squash(unsigned tid);
 164
 165     /** Wakes all dependents of a completed instruction. */
 166     void wakeDependents(DynInstPtr &inst);
 167
 168     /** Tells memory dependence unit that a memory instruction needs to be
 169      * rescheduled. It will re-execute once replayMemInst() is called.
 170      */
 171     void rescheduleMemInst(DynInstPtr &inst);
 172
 173     /** Re-executes all rescheduled memory instructions. */
 174     void replayMemInst(DynInstPtr &inst);
 175
 176     /** Sends an instruction to commit through the time buffer. */
 177     void instToCommit(DynInstPtr &inst);
 178
 179     /** Inserts unused instructions of a thread into the skid buffer. */
 180     void skidInsert(unsigned tid);
 181
 182     /** Returns the max of the number of entries in all of the skid buffers. */
 183     int skidCount();
 184
 185     /** Returns if all of the skid buffers are empty. */
 186     bool skidsEmpty();
 187
 188     /** Updates overall IEW status based on all of the stages' statuses. */
 189     void updateStatus();
 190
 191     /** Resets entries of the IQ and the LSQ. */
 192     void resetEntries();
 193
 194     /** Tells the CPU to wakeup if it has descheduled itself due to no
 195      * activity. Used mainly by the LdWritebackEvent.
 196      */
 197     void wakeCPU();
 198
 199     /** Reports to the CPU that there is activity this cycle. */
 200     void activityThisCycle();
 201
 202     /** Tells CPU that the IEW stage is active and running. */
 203     inline void activateStage();
 204
 205     /** Tells CPU that the IEW stage is inactive and idle. */
 206     inline void deactivateStage();
 207
 208     /** Returns if the LSQ has any stores to writeback. */
 209     bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 210
 211     void incrWb(InstSeqNum &sn)
 212     {
 213         if (++wbOutstanding == wbMax)
 214             ableToIssue = false;
 215         DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
 216         assert(wbOutstanding <= wbMax);
 217 #ifdef DEBUG
 218         wbList.insert(sn);
 219 #endif
 220     }
 221
 222     void decrWb(InstSeqNum &sn)
 223     {
 224         if (wbOutstanding-- == wbMax)
 225             ableToIssue = true;
 226         DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
 227         assert(wbOutstanding >= 0);
 228 #ifdef DEBUG
 229         assert(wbList.find(sn) != wbList.end());
 230         wbList.erase(sn);
 231 #endif
 232     }
 233
 234 #ifdef DEBUG
 235     std::set<InstSeqNum> wbList;
 236
 237     void dumpWb()
 238     {
 239         std::set<InstSeqNum>::iterator wb_it = wbList.begin();
 240         while (wb_it != wbList.end()) {
 241             cprintf("[sn:%lli]\n",
 242                     (*wb_it));
 243             wb_it++;
 244         }
 245     }
 246 #endif
 247
 248     bool canIssue() { return ableToIssue; }
 249
 250     bool ableToIssue;
 251
 252   private:
 253     /** Sends commit proper information for a squash due to a branch
 254      * mispredict.
 255      */
 256     void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
 257
 258     /** Sends commit proper information for a squash due to a memory order
 259      * violation.
 260      */
 261     void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
 262
 263     /** Sends commit proper information for a squash due to memory becoming
 264      * blocked (younger issued instructions must be retried).
 265      */
 266     void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
 267
 268     /** Sets Dispatch to blocked, and signals back to other stages to block. */
 269     void block(unsigned thread_id);
 270
 271     /** Unblocks Dispatch if the skid buffer is empty, and signals back to
 272      * other stages to unblock.
 273      */
 274     void unblock(unsigned thread_id);
 275
 276     /** Determines proper actions to take given Dispatch's status. */
 277     void dispatch(unsigned tid);
 278
 279     /** Dispatches instructions to IQ and LSQ. */
 280     void dispatchInsts(unsigned tid);
 281
 282     /** Executes instructions. In the case of memory operations, it informs the
 283      * LSQ to execute the instructions. Also handles any redirects that occur
 284      * due to the executed instructions.
 285      */
 286     void executeInsts();
 287
 288     /** Writebacks instructions. In our model, the instruction's execute()
 289      * function atomically reads registers, executes, and writes registers.
 290      * Thus this writeback only wakes up dependent instructions, and informs
 291      * the scoreboard of registers becoming ready.
 292      */
 293     void writebackInsts();
 294
 295     /** Returns the number of valid, non-squashed instructions coming from
 296      * rename to dispatch.
 297      */
 298     unsigned validInstsFromRename();
 299
 300     /** Reads the stall signals. */
 301     void readStallSignals(unsigned tid);
 302
 303     /** Checks if any of the stall conditions are currently true. */
 304     bool checkStall(unsigned tid);
 305
 306     /** Processes inputs and changes state accordingly. */
 307     void checkSignalsAndUpdate(unsigned tid);
 308
 309     /** Removes instructions from rename from a thread's instruction list. */
 310     void emptyRenameInsts(unsigned tid);
 311
 312     /** Sorts instructions coming from rename into lists separated by thread. */
 313     void sortInsts();
 314
 315   public:
 316     /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
 317      * Writeback to run for one cycle.
 318      */
 319     void tick();
 320
 321   private:
 322     /** Updates execution stats based on the instruction. */
 323     void updateExeInstStats(DynInstPtr &inst);
 324
 325     /** Pointer to main time buffer used for backwards communication. */
 326     TimeBuffer<TimeStruct> *timeBuffer;
 327
 328     /** Wire to write information heading to previous stages. */
 329     typename TimeBuffer<TimeStruct>::wire toFetch;
 330
 331     /** Wire to get commit's output from backwards time buffer. */
 332     typename TimeBuffer<TimeStruct>::wire fromCommit;
 333
 334     /** Wire to write information heading to previous stages. */
 335     typename TimeBuffer<TimeStruct>::wire toRename;
 336
 337     /** Rename instruction queue interface. */
 338     TimeBuffer<RenameStruct> *renameQueue;
 339
 340     /** Wire to get rename's output from rename queue. */
 341     typename TimeBuffer<RenameStruct>::wire fromRename;
 342
 343     /** Issue stage queue. */
 344     TimeBuffer<IssueStruct> issueToExecQueue;
 345
 346     /** Wire to read information from the issue stage time queue. */
 347     typename TimeBuffer<IssueStruct>::wire fromIssue;
 348
 349     /**
 350      * IEW stage time buffer.  Holds ROB indices of instructions that
 351      * can be marked as completed.
 352      */
 353     TimeBuffer<IEWStruct> *iewQueue;
 354
 355     /** Wire to write infromation heading to commit. */
 356     typename TimeBuffer<IEWStruct>::wire toCommit;
 357
 358     /** Queue of all instructions coming from rename this cycle. */
 359     std::queue<DynInstPtr> insts[Impl::MaxThreads];
 360
 361     /** Skid buffer between rename and IEW. */
 362     std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
 363
 364     /** Scoreboard pointer. */
 365     Scoreboard* scoreboard;
 366
 367   private:
 368     /** CPU pointer. */
 369     O3CPU *cpu;
 370
 371     /** Records if IEW has written to the time buffer this cycle, so that the
 372      * CPU can deschedule itself if there is no activity.
 373      */
 374     bool wroteToTimeBuffer;
 375
 376     /** Source of possible stalls. */
 377     struct Stalls {
 378         bool commit;
 379     };
 380
 381     /** Stages that are telling IEW to stall. */
 382     Stalls stalls[Impl::MaxThreads];
 383
 384     /** Debug function to print instructions that are issued this cycle. */
 385     void printAvailableInsts();
 386
 387   public:
 388     /** Instruction queue. */
 389     IQ instQueue;
 390
 391     /** Load / store queue. */
 392     LSQ ldstQueue;
 393
 394     /** Pointer to the functional unit pool. */
 395     FUPool *fuPool;
 396     /** Records if the LSQ needs to be updated on the next cycle, so that
 397      * IEW knows if there will be activity on the next cycle.
 398      */
 399     bool updateLSQNextCycle;
 400
 401   private:
 402     /** Records if there is a fetch redirect on this cycle for each thread. */
 403     bool fetchRedirect[Impl::MaxThreads];
 404
 405     /** Keeps track of the last valid branch delay slot instss for threads */
 406     InstSeqNum bdelayDoneSeqNum[Impl::MaxThreads];
 407
 408     /** Used to track if all instructions have been dispatched this cycle.
 409      * If they have not, then blocking must have occurred, and the instructions
 410      * would already be added to the skid buffer.
 411      * @todo: Fix this hack.
 412      */
 413     bool dispatchedAllInsts;
 414
 415     /** Records if the queues have been changed (inserted or issued insts),
 416      * so that IEW knows to broadcast the updated amount of free entries.
 417      */
 418     bool updatedQueues;
 419
 420     /** Commit to IEW delay, in ticks. */
 421     unsigned commitToIEWDelay;
 422
 423     /** Rename to IEW delay, in ticks. */
 424     unsigned renameToIEWDelay;
 425
 426     /**
 427      * Issue to execute delay, in ticks.  What this actually represents is
 428      * the amount of time it takes for an instruction to wake up, be
 429      * scheduled, and sent to a FU for execution.
 430      */
 431     unsigned issueToExecuteDelay;
 432
 433     /** Width of dispatch, in instructions. */
 434     unsigned dispatchWidth;
 435
 436     /** Width of issue, in instructions. */
 437     unsigned issueWidth;
 438
 439     /** Index into queue of instructions being written back. */
 440     unsigned wbNumInst;
 441
 442     /** Cycle number within the queue of instructions being written back.
 443      * Used in case there are too many instructions writing back at the current
 444      * cycle and writesbacks need to be scheduled for the future. See comments
 445      * in instToCommit().
 446      */
 447     unsigned wbCycle;
 448
 449     /** Number of instructions in flight that will writeback. */
 450
 451     /** Number of instructions in flight that will writeback. */
 452     int wbOutstanding;
 453
 454     /** Writeback width. */
 455     unsigned wbWidth;
 456
 457     /** Writeback width * writeback depth, where writeback depth is
 458      * the number of cycles of writing back instructions that can be
 459      * buffered. */
 460     unsigned wbMax;
 461
 462     /** Number of active threads. */
 463     unsigned numThreads;
 464
 465     /** Pointer to list of active threads. */
 466     std::list<unsigned> *activeThreads;
 467
 468     /** Maximum size of the skid buffer. */
 469     unsigned skidBufferMax;
 470
 471     /** Is this stage switched out. */
 472     bool switchedOut;
 473
 474     /** Stat for total number of idle cycles. */
 475     Stats::Scalar<> iewIdleCycles;
 476     /** Stat for total number of squashing cycles. */
 477     Stats::Scalar<> iewSquashCycles;
 478     /** Stat for total number of blocking cycles. */
 479     Stats::Scalar<> iewBlockCycles;
 480     /** Stat for total number of unblocking cycles. */
 481     Stats::Scalar<> iewUnblockCycles;
 482     /** Stat for total number of instructions dispatched. */
 483     Stats::Scalar<> iewDispatchedInsts;
 484     /** Stat for total number of squashed instructions dispatch skips. */
 485     Stats::Scalar<> iewDispSquashedInsts;
 486     /** Stat for total number of dispatched load instructions. */
 487     Stats::Scalar<> iewDispLoadInsts;
 488     /** Stat for total number of dispatched store instructions. */
 489     Stats::Scalar<> iewDispStoreInsts;
 490     /** Stat for total number of dispatched non speculative instructions. */
 491     Stats::Scalar<> iewDispNonSpecInsts;
 492     /** Stat for number of times the IQ becomes full. */
 493     Stats::Scalar<> iewIQFullEvents;
 494     /** Stat for number of times the LSQ becomes full. */
 495     Stats::Scalar<> iewLSQFullEvents;
 496     /** Stat for total number of memory ordering violation events. */
 497     Stats::Scalar<> memOrderViolationEvents;
 498     /** Stat for total number of incorrect predicted taken branches. */
 499     Stats::Scalar<> predictedTakenIncorrect;
 500     /** Stat for total number of incorrect predicted not taken branches. */
 501     Stats::Scalar<> predictedNotTakenIncorrect;
 502     /** Stat for total number of mispredicted branches detected at execute. */
 503     Stats::Formula branchMispredicts;
 504
 505     /** Stat for total number of executed instructions. */
 506     Stats::Scalar<> iewExecutedInsts;
 507     /** Stat for total number of executed load instructions. */
 508     Stats::Vector<> iewExecLoadInsts;
 509     /** Stat for total number of executed store instructions. */
 510 //    Stats::Scalar<> iewExecStoreInsts;
 511     /** Stat for total number of squashed instructions skipped at execute. */
 512     Stats::Scalar<> iewExecSquashedInsts;
 513     /** Number of executed software prefetches. */
 514     Stats::Vector<> iewExecutedSwp;
 515     /** Number of executed nops. */
 516     Stats::Vector<> iewExecutedNop;
 517     /** Number of executed meomory references. */
 518     Stats::Vector<> iewExecutedRefs;
 519     /** Number of executed branches. */
 520     Stats::Vector<> iewExecutedBranches;
 521     /** Number of executed store instructions. */
 522     Stats::Formula iewExecStoreInsts;
 523     /** Number of instructions executed per cycle. */
 524     Stats::Formula iewExecRate;
 525
 526     /** Number of instructions sent to commit. */
 527     Stats::Vector<> iewInstsToCommit;
 528     /** Number of instructions that writeback. */
 529     Stats::Vector<> writebackCount;
 530     /** Number of instructions that wake consumers. */
 531     Stats::Vector<> producerInst;
 532     /** Number of instructions that wake up from producers. */
 533     Stats::Vector<> consumerInst;
 534     /** Number of instructions that were delayed in writing back due
 535      * to resource contention.
 536      */
 537     Stats::Vector<> wbPenalized;
 538     /** Number of instructions per cycle written back. */
 539     Stats::Formula wbRate;
 540     /** Average number of woken instructions per writeback. */
 541     Stats::Formula wbFanout;
 542     /** Number of instructions per cycle delayed in writing back . */
 543     Stats::Formula wbPenalizedRate;
 544 };
 545
 546 #endif // __CPU_O3_IEW_HH__