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31 #ifndef __CPU_O3_IEW_HH__
32 #define __CPU_O3_IEW_HH__
36 #include "base/statistics.hh"
37 #include "base/timebuf.hh"
38 #include "config/full_system.hh"
39 #include "cpu/o3/comm.hh"
40 #include "cpu/o3/scoreboard.hh"
41 #include "cpu/o3/lsq.hh"
46 * DefaultIEW handles both single threaded and SMT IEW
47 * (issue/execute/writeback). It handles the dispatching of
48 * instructions to the LSQ/IQ as part of the issue stage, and has the
49 * IQ try to issue instructions each cycle. The execute latency is
50 * actually tied into the issue latency to allow the IQ to be able to
51 * do back-to-back scheduling without having to speculatively schedule
52 * instructions. This happens by having the IQ have access to the
53 * functional units, and the IQ gets the execution latencies from the
54 * FUs when it issues instructions. Instructions reach the execute
55 * stage on the last cycle of their execution, which is when the IQ
56 * knows to wake up any dependent instructions, allowing back to back
57 * scheduling. The execute portion of IEW separates memory
58 * instructions from non-memory instructions, either telling the LSQ
59 * to execute the instruction, or executing the instruction directly.
60 * The writeback portion of IEW completes the instructions by waking
61 * up any dependents, and marking the register ready on the
69 typedef typename Impl::CPUPol CPUPol;
70 typedef typename Impl::DynInstPtr DynInstPtr;
71 typedef typename Impl::O3CPU O3CPU;
72 typedef typename Impl::Params Params;
74 typedef typename CPUPol::IQ IQ;
75 typedef typename CPUPol::RenameMap RenameMap;
76 typedef typename CPUPol::LSQ LSQ;
78 typedef typename CPUPol::TimeStruct TimeStruct;
79 typedef typename CPUPol::IEWStruct IEWStruct;
80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::IssueStruct IssueStruct;
83 friend class Impl::O3CPU;
84 friend class CPUPol::IQ;
87 /** Overall IEW stage status. Used to determine if the CPU can
88 * deschedule itself due to a lack of activity.
95 /** Status for Issue, Execute, and Writeback stages. */
106 /** Overall stage status. */
108 /** Dispatch status. */
109 StageStatus dispatchStatus[Impl::MaxThreads];
110 /** Execute status. */
111 StageStatus exeStatus;
112 /** Writeback status. */
113 StageStatus wbStatus;
116 /** Constructs a DefaultIEW with the given parameters. */
117 DefaultIEW(Params *params);
119 /** Returns the name of the DefaultIEW stage. */
120 std::string name() const;
122 /** Registers statistics. */
125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
128 /** Sets CPU pointer for IEW, IQ, and LSQ. */
129 void setCPU(O3CPU *cpu_ptr);
131 /** Sets main time buffer used for backwards communication. */
132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
134 /** Sets time buffer for getting instructions coming from rename. */
135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
137 /** Sets time buffer to pass on instructions to commit. */
138 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
140 /** Sets pointer to list of active threads. */
141 void setActiveThreads(std::list<unsigned> *at_ptr);
143 /** Sets pointer to the scoreboard. */
144 void setScoreboard(Scoreboard *sb_ptr);
146 /** Starts switch out of IEW stage. */
149 /** Completes switch out of IEW stage. */
152 /** Takes over from another CPU's thread. */
155 /** Returns if IEW is switched out. */
156 bool isSwitchedOut() { return switchedOut; }
158 /** Squashes instructions in IEW for a specific thread. */
159 void squash(unsigned tid);
161 /** Wakes all dependents of a completed instruction. */
162 void wakeDependents(DynInstPtr &inst);
164 /** Tells memory dependence unit that a memory instruction needs to be
165 * rescheduled. It will re-execute once replayMemInst() is called.
167 void rescheduleMemInst(DynInstPtr &inst);
169 /** Re-executes all rescheduled memory instructions. */
170 void replayMemInst(DynInstPtr &inst);
172 /** Sends an instruction to commit through the time buffer. */
173 void instToCommit(DynInstPtr &inst);
175 /** Inserts unused instructions of a thread into the skid buffer. */
176 void skidInsert(unsigned tid);
178 /** Returns the max of the number of entries in all of the skid buffers. */
181 /** Returns if all of the skid buffers are empty. */
184 /** Updates overall IEW status based on all of the stages' statuses. */
187 /** Resets entries of the IQ and the LSQ. */
190 /** Tells the CPU to wakeup if it has descheduled itself due to no
191 * activity. Used mainly by the LdWritebackEvent.
195 /** Reports to the CPU that there is activity this cycle. */
196 void activityThisCycle();
198 /** Tells CPU that the IEW stage is active and running. */
199 inline void activateStage();
201 /** Tells CPU that the IEW stage is inactive and idle. */
202 inline void deactivateStage();
204 /** Returns if the LSQ has any stores to writeback. */
205 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
207 void incrWb(InstSeqNum &sn)
209 if (++wbOutstanding == wbMax)
211 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
217 void decrWb(InstSeqNum &sn)
219 if (wbOutstanding-- == wbMax)
221 DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
223 assert(wbList.find(sn) != wbList.end());
229 std::set<InstSeqNum> wbList;
233 std::set<InstSeqNum>::iterator wb_it = wbList.begin();
234 while (wb_it != wbList.end()) {
235 cprintf("[sn:%lli]\n",
242 bool canIssue() { return ableToIssue; }
247 /** Sends commit proper information for a squash due to a branch
250 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
252 /** Sends commit proper information for a squash due to a memory order
255 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
257 /** Sends commit proper information for a squash due to memory becoming
258 * blocked (younger issued instructions must be retried).
260 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
262 /** Sets Dispatch to blocked, and signals back to other stages to block. */
263 void block(unsigned thread_id);
265 /** Unblocks Dispatch if the skid buffer is empty, and signals back to
266 * other stages to unblock.
268 void unblock(unsigned thread_id);
270 /** Determines proper actions to take given Dispatch's status. */
271 void dispatch(unsigned tid);
273 /** Dispatches instructions to IQ and LSQ. */
274 void dispatchInsts(unsigned tid);
276 /** Executes instructions. In the case of memory operations, it informs the
277 * LSQ to execute the instructions. Also handles any redirects that occur
278 * due to the executed instructions.
282 /** Writebacks instructions. In our model, the instruction's execute()
283 * function atomically reads registers, executes, and writes registers.
284 * Thus this writeback only wakes up dependent instructions, and informs
285 * the scoreboard of registers becoming ready.
287 void writebackInsts();
289 /** Returns the number of valid, non-squashed instructions coming from
290 * rename to dispatch.
292 unsigned validInstsFromRename();
294 /** Reads the stall signals. */
295 void readStallSignals(unsigned tid);
297 /** Checks if any of the stall conditions are currently true. */
298 bool checkStall(unsigned tid);
300 /** Processes inputs and changes state accordingly. */
301 void checkSignalsAndUpdate(unsigned tid);
303 /** Removes instructions from rename from a thread's instruction list. */
304 void emptyRenameInsts(unsigned tid);
306 /** Sorts instructions coming from rename into lists separated by thread. */
310 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
311 * Writeback to run for one cycle.
316 /** Updates execution stats based on the instruction. */
317 void updateExeInstStats(DynInstPtr &inst);
319 /** Pointer to main time buffer used for backwards communication. */
320 TimeBuffer<TimeStruct> *timeBuffer;
322 /** Wire to write information heading to previous stages. */
323 typename TimeBuffer<TimeStruct>::wire toFetch;
325 /** Wire to get commit's output from backwards time buffer. */
326 typename TimeBuffer<TimeStruct>::wire fromCommit;
328 /** Wire to write information heading to previous stages. */
329 typename TimeBuffer<TimeStruct>::wire toRename;
331 /** Rename instruction queue interface. */
332 TimeBuffer<RenameStruct> *renameQueue;
334 /** Wire to get rename's output from rename queue. */
335 typename TimeBuffer<RenameStruct>::wire fromRename;
337 /** Issue stage queue. */
338 TimeBuffer<IssueStruct> issueToExecQueue;
340 /** Wire to read information from the issue stage time queue. */
341 typename TimeBuffer<IssueStruct>::wire fromIssue;
344 * IEW stage time buffer. Holds ROB indices of instructions that
345 * can be marked as completed.
347 TimeBuffer<IEWStruct> *iewQueue;
349 /** Wire to write infromation heading to commit. */
350 typename TimeBuffer<IEWStruct>::wire toCommit;
352 /** Queue of all instructions coming from rename this cycle. */
353 std::queue<DynInstPtr> insts[Impl::MaxThreads];
355 /** Skid buffer between rename and IEW. */
356 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
358 /** Scoreboard pointer. */
359 Scoreboard* scoreboard;
362 /** Instruction queue. */
365 /** Load / store queue. */
368 /** Pointer to the functional unit pool. */
375 /** Records if IEW has written to the time buffer this cycle, so that the
376 * CPU can deschedule itself if there is no activity.
378 bool wroteToTimeBuffer;
380 /** Source of possible stalls. */
385 /** Stages that are telling IEW to stall. */
386 Stalls stalls[Impl::MaxThreads];
388 /** Debug function to print instructions that are issued this cycle. */
389 void printAvailableInsts();
392 /** Records if the LSQ needs to be updated on the next cycle, so that
393 * IEW knows if there will be activity on the next cycle.
395 bool updateLSQNextCycle;
398 /** Records if there is a fetch redirect on this cycle for each thread. */
399 bool fetchRedirect[Impl::MaxThreads];
401 /** Used to track if all instructions have been dispatched this cycle.
402 * If they have not, then blocking must have occurred, and the instructions
403 * would already be added to the skid buffer.
404 * @todo: Fix this hack.
406 bool dispatchedAllInsts;
408 /** Records if the queues have been changed (inserted or issued insts),
409 * so that IEW knows to broadcast the updated amount of free entries.
413 /** Commit to IEW delay, in ticks. */
414 unsigned commitToIEWDelay;
416 /** Rename to IEW delay, in ticks. */
417 unsigned renameToIEWDelay;
420 * Issue to execute delay, in ticks. What this actually represents is
421 * the amount of time it takes for an instruction to wake up, be
422 * scheduled, and sent to a FU for execution.
424 unsigned issueToExecuteDelay;
426 /** Width of dispatch, in instructions. */
427 unsigned dispatchWidth;
429 /** Width of issue, in instructions. */
432 /** Index into queue of instructions being written back. */
435 /** Cycle number within the queue of instructions being written back.
436 * Used in case there are too many instructions writing back at the current
437 * cycle and writesbacks need to be scheduled for the future. See comments
442 /** Number of instructions in flight that will writeback. */
443 unsigned wbOutstanding;
445 /** Writeback width. */
448 /** Writeback width * writeback depth, where writeback depth is
449 * the number of cycles of writing back instructions that can be
453 /** Number of active threads. */
456 /** Pointer to list of active threads. */
457 std::list<unsigned> *activeThreads;
459 /** Maximum size of the skid buffer. */
460 unsigned skidBufferMax;
462 /** Is this stage switched out. */
465 /** Stat for total number of idle cycles. */
466 Stats::Scalar<> iewIdleCycles;
467 /** Stat for total number of squashing cycles. */
468 Stats::Scalar<> iewSquashCycles;
469 /** Stat for total number of blocking cycles. */
470 Stats::Scalar<> iewBlockCycles;
471 /** Stat for total number of unblocking cycles. */
472 Stats::Scalar<> iewUnblockCycles;
473 /** Stat for total number of instructions dispatched. */
474 Stats::Scalar<> iewDispatchedInsts;
475 /** Stat for total number of squashed instructions dispatch skips. */
476 Stats::Scalar<> iewDispSquashedInsts;
477 /** Stat for total number of dispatched load instructions. */
478 Stats::Scalar<> iewDispLoadInsts;
479 /** Stat for total number of dispatched store instructions. */
480 Stats::Scalar<> iewDispStoreInsts;
481 /** Stat for total number of dispatched non speculative instructions. */
482 Stats::Scalar<> iewDispNonSpecInsts;
483 /** Stat for number of times the IQ becomes full. */
484 Stats::Scalar<> iewIQFullEvents;
485 /** Stat for number of times the LSQ becomes full. */
486 Stats::Scalar<> iewLSQFullEvents;
487 /** Stat for total number of memory ordering violation events. */
488 Stats::Scalar<> memOrderViolationEvents;
489 /** Stat for total number of incorrect predicted taken branches. */
490 Stats::Scalar<> predictedTakenIncorrect;
491 /** Stat for total number of incorrect predicted not taken branches. */
492 Stats::Scalar<> predictedNotTakenIncorrect;
493 /** Stat for total number of mispredicted branches detected at execute. */
494 Stats::Formula branchMispredicts;
496 /** Stat for total number of executed instructions. */
497 Stats::Scalar<> iewExecutedInsts;
498 /** Stat for total number of executed load instructions. */
499 Stats::Vector<> iewExecLoadInsts;
500 /** Stat for total number of squashed instructions skipped at execute. */
501 Stats::Scalar<> iewExecSquashedInsts;
502 /** Number of executed software prefetches. */
503 Stats::Vector<> iewExecutedSwp;
504 /** Number of executed nops. */
505 Stats::Vector<> iewExecutedNop;
506 /** Number of executed meomory references. */
507 Stats::Vector<> iewExecutedRefs;
508 /** Number of executed branches. */
509 Stats::Vector<> iewExecutedBranches;
510 /** Number of executed store instructions. */
511 Stats::Formula iewExecStoreInsts;
512 /** Number of instructions executed per cycle. */
513 Stats::Formula iewExecRate;
515 /** Number of instructions sent to commit. */
516 Stats::Vector<> iewInstsToCommit;
517 /** Number of instructions that writeback. */
518 Stats::Vector<> writebackCount;
519 /** Number of instructions that wake consumers. */
520 Stats::Vector<> producerInst;
521 /** Number of instructions that wake up from producers. */
522 Stats::Vector<> consumerInst;
523 /** Number of instructions that were delayed in writing back due
524 * to resource contention.
526 Stats::Vector<> wbPenalized;
527 /** Number of instructions per cycle written back. */
528 Stats::Formula wbRate;
529 /** Average number of woken instructions per writeback. */
530 Stats::Formula wbFanout;
531 /** Number of instructions per cycle delayed in writing back . */
532 Stats::Formula wbPenalizedRate;
535 #endif // __CPU_O3_IEW_HH__