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43 // @todo: Fix the instantaneous communication among all the stages within
44 // iew. There's a clear delay between issue and execute, yet backwards
45 // communication happens simultaneously.
49 #include "arch/utility.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/checker/cpu.hh"
52 #include "cpu/o3/fu_pool.hh"
53 #include "cpu/o3/iew.hh"
54 #include "cpu/timebuf.hh"
55 #include "debug/Activity.hh"
56 #include "debug/Decode.hh"
57 #include "debug/IEW.hh"
58 #include "params/DerivO3CPU.hh"
63 DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
64 : issueToExecQueue(params->backComSize, params->forwardComSize),
66 instQueue(_cpu, this, params),
67 ldstQueue(_cpu, this, params),
68 fuPool(params->fuPool),
69 commitToIEWDelay(params->commitToIEWDelay),
70 renameToIEWDelay(params->renameToIEWDelay),
71 issueToExecuteDelay(params->issueToExecuteDelay),
72 dispatchWidth(params->dispatchWidth),
73 issueWidth(params->issueWidth),
75 wbWidth(params->wbWidth),
76 numThreads(params->numThreads),
83 // Setup wire to read instructions coming from issue.
84 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
86 // Instruction queue needs the queue between issue and execute.
87 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
89 for (ThreadID tid = 0; tid < numThreads; tid++) {
90 dispatchStatus[tid] = Running;
91 stalls[tid].commit = false;
92 fetchRedirect[tid] = false;
95 wbMax = wbWidth * params->wbDepth;
97 updateLSQNextCycle = false;
101 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
104 template <class Impl>
106 DefaultIEW<Impl>::name() const
108 return cpu->name() + ".iew";
111 template <class Impl>
113 DefaultIEW<Impl>::regStats()
115 using namespace Stats;
117 instQueue.regStats();
118 ldstQueue.regStats();
121 .name(name() + ".iewIdleCycles")
122 .desc("Number of cycles IEW is idle");
125 .name(name() + ".iewSquashCycles")
126 .desc("Number of cycles IEW is squashing");
129 .name(name() + ".iewBlockCycles")
130 .desc("Number of cycles IEW is blocking");
133 .name(name() + ".iewUnblockCycles")
134 .desc("Number of cycles IEW is unblocking");
137 .name(name() + ".iewDispatchedInsts")
138 .desc("Number of instructions dispatched to IQ");
141 .name(name() + ".iewDispSquashedInsts")
142 .desc("Number of squashed instructions skipped by dispatch");
145 .name(name() + ".iewDispLoadInsts")
146 .desc("Number of dispatched load instructions");
149 .name(name() + ".iewDispStoreInsts")
150 .desc("Number of dispatched store instructions");
153 .name(name() + ".iewDispNonSpecInsts")
154 .desc("Number of dispatched non-speculative instructions");
157 .name(name() + ".iewIQFullEvents")
158 .desc("Number of times the IQ has become full, causing a stall");
161 .name(name() + ".iewLSQFullEvents")
162 .desc("Number of times the LSQ has become full, causing a stall");
164 memOrderViolationEvents
165 .name(name() + ".memOrderViolationEvents")
166 .desc("Number of memory order violations");
168 predictedTakenIncorrect
169 .name(name() + ".predictedTakenIncorrect")
170 .desc("Number of branches that were predicted taken incorrectly");
172 predictedNotTakenIncorrect
173 .name(name() + ".predictedNotTakenIncorrect")
174 .desc("Number of branches that were predicted not taken incorrectly");
177 .name(name() + ".branchMispredicts")
178 .desc("Number of branch mispredicts detected at execute");
180 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
183 .name(name() + ".iewExecutedInsts")
184 .desc("Number of executed instructions");
187 .init(cpu->numThreads)
188 .name(name() + ".iewExecLoadInsts")
189 .desc("Number of load instructions executed")
193 .name(name() + ".iewExecSquashedInsts")
194 .desc("Number of squashed instructions skipped in execute");
197 .init(cpu->numThreads)
198 .name(name() + ".exec_swp")
199 .desc("number of swp insts executed")
203 .init(cpu->numThreads)
204 .name(name() + ".exec_nop")
205 .desc("number of nop insts executed")
209 .init(cpu->numThreads)
210 .name(name() + ".exec_refs")
211 .desc("number of memory reference insts executed")
215 .init(cpu->numThreads)
216 .name(name() + ".exec_branches")
217 .desc("Number of branches executed")
221 .name(name() + ".exec_stores")
222 .desc("Number of stores executed")
224 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
227 .name(name() + ".exec_rate")
228 .desc("Inst execution rate")
231 iewExecRate = iewExecutedInsts / cpu->numCycles;
234 .init(cpu->numThreads)
235 .name(name() + ".wb_sent")
236 .desc("cumulative count of insts sent to commit")
240 .init(cpu->numThreads)
241 .name(name() + ".wb_count")
242 .desc("cumulative count of insts written-back")
246 .init(cpu->numThreads)
247 .name(name() + ".wb_producers")
248 .desc("num instructions producing a value")
252 .init(cpu->numThreads)
253 .name(name() + ".wb_consumers")
254 .desc("num instructions consuming a value")
258 .init(cpu->numThreads)
259 .name(name() + ".wb_penalized")
260 .desc("number of instrctions required to write to 'other' IQ")
264 .name(name() + ".wb_penalized_rate")
265 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
268 wbPenalizedRate = wbPenalized / writebackCount;
271 .name(name() + ".wb_fanout")
272 .desc("average fanout of values written-back")
275 wbFanout = producerInst / consumerInst;
278 .name(name() + ".wb_rate")
279 .desc("insts written-back per cycle")
281 wbRate = writebackCount / cpu->numCycles;
286 DefaultIEW<Impl>::initStage()
288 for (ThreadID tid = 0; tid < numThreads; tid++) {
289 toRename->iewInfo[tid].usedIQ = true;
290 toRename->iewInfo[tid].freeIQEntries =
291 instQueue.numFreeEntries(tid);
293 toRename->iewInfo[tid].usedLSQ = true;
294 toRename->iewInfo[tid].freeLSQEntries =
295 ldstQueue.numFreeEntries(tid);
298 // Initialize the checker's dcache port here
300 cpu->checker->setDcachePort(&cpu->getDataPort());
303 cpu->activateStage(O3CPU::IEWIdx);
308 DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
312 // Setup wire to read information from time buffer, from commit.
313 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
315 // Setup wire to write information back to previous stages.
316 toRename = timeBuffer->getWire(0);
318 toFetch = timeBuffer->getWire(0);
320 // Instruction queue also needs main time buffer.
321 instQueue.setTimeBuffer(tb_ptr);
326 DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
328 renameQueue = rq_ptr;
330 // Setup wire to read information from rename queue.
331 fromRename = renameQueue->getWire(-renameToIEWDelay);
336 DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
340 // Setup wire to write instructions to commit.
341 toCommit = iewQueue->getWire(0);
346 DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
348 activeThreads = at_ptr;
350 ldstQueue.setActiveThreads(at_ptr);
351 instQueue.setActiveThreads(at_ptr);
356 DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
361 template <class Impl>
363 DefaultIEW<Impl>::drain()
365 // IEW is ready to drain at any time.
366 cpu->signalDrained();
370 template <class Impl>
372 DefaultIEW<Impl>::resume()
376 template <class Impl>
378 DefaultIEW<Impl>::switchOut()
382 assert(insts[0].empty());
383 assert(skidBuffer[0].empty());
385 instQueue.switchOut();
386 ldstQueue.switchOut();
389 for (ThreadID tid = 0; tid < numThreads; tid++) {
390 while (!insts[tid].empty())
392 while (!skidBuffer[tid].empty())
393 skidBuffer[tid].pop();
397 template <class Impl>
399 DefaultIEW<Impl>::takeOverFrom()
407 instQueue.takeOverFrom();
408 ldstQueue.takeOverFrom();
412 cpu->activityThisCycle();
414 for (ThreadID tid = 0; tid < numThreads; tid++) {
415 dispatchStatus[tid] = Running;
416 stalls[tid].commit = false;
417 fetchRedirect[tid] = false;
420 updateLSQNextCycle = false;
422 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
423 issueToExecQueue.advance();
429 DefaultIEW<Impl>::squash(ThreadID tid)
431 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
433 // Tell the IQ to start squashing.
434 instQueue.squash(tid);
436 // Tell the LDSTQ to start squashing.
437 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
438 updatedQueues = true;
440 // Clear the skid buffer in case it has any data in it.
441 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
442 tid, fromCommit->commitInfo[tid].doneSeqNum);
444 while (!skidBuffer[tid].empty()) {
445 if (skidBuffer[tid].front()->isLoad() ||
446 skidBuffer[tid].front()->isStore() ) {
447 toRename->iewInfo[tid].dispatchedToLSQ++;
450 toRename->iewInfo[tid].dispatched++;
452 skidBuffer[tid].pop();
455 emptyRenameInsts(tid);
460 DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
462 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
463 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
465 if (toCommit->squash[tid] == false ||
466 inst->seqNum < toCommit->squashedSeqNum[tid]) {
467 toCommit->squash[tid] = true;
468 toCommit->squashedSeqNum[tid] = inst->seqNum;
469 toCommit->branchTaken[tid] = inst->pcState().branching();
471 TheISA::PCState pc = inst->pcState();
472 TheISA::advancePC(pc, inst->staticInst);
474 toCommit->pc[tid] = pc;
475 toCommit->mispredictInst[tid] = inst;
476 toCommit->includeSquashInst[tid] = false;
478 wroteToTimeBuffer = true;
485 DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
487 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
488 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
489 // Need to include inst->seqNum in the following comparison to cover the
490 // corner case when a branch misprediction and a memory violation for the
491 // same instruction (e.g. load PC) are detected in the same cycle. In this
492 // case the memory violator should take precedence over the branch
493 // misprediction because it requires the violator itself to be included in
495 if (toCommit->squash[tid] == false ||
496 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
497 toCommit->squash[tid] = true;
499 toCommit->squashedSeqNum[tid] = inst->seqNum;
500 toCommit->pc[tid] = inst->pcState();
501 toCommit->mispredictInst[tid] = NULL;
503 // Must include the memory violator in the squash.
504 toCommit->includeSquashInst[tid] = true;
506 wroteToTimeBuffer = true;
512 DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
514 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
515 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
516 if (toCommit->squash[tid] == false ||
517 inst->seqNum < toCommit->squashedSeqNum[tid]) {
518 toCommit->squash[tid] = true;
520 toCommit->squashedSeqNum[tid] = inst->seqNum;
521 toCommit->pc[tid] = inst->pcState();
522 toCommit->mispredictInst[tid] = NULL;
524 // Must include the broadcasted SN in the squash.
525 toCommit->includeSquashInst[tid] = true;
527 ldstQueue.setLoadBlockedHandled(tid);
529 wroteToTimeBuffer = true;
535 DefaultIEW<Impl>::block(ThreadID tid)
537 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
539 if (dispatchStatus[tid] != Blocked &&
540 dispatchStatus[tid] != Unblocking) {
541 toRename->iewBlock[tid] = true;
542 wroteToTimeBuffer = true;
545 // Add the current inputs to the skid buffer so they can be
546 // reprocessed when this stage unblocks.
549 dispatchStatus[tid] = Blocked;
554 DefaultIEW<Impl>::unblock(ThreadID tid)
556 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
557 "buffer %u.\n",tid, tid);
559 // If the skid bufffer is empty, signal back to previous stages to unblock.
560 // Also switch status to running.
561 if (skidBuffer[tid].empty()) {
562 toRename->iewUnblock[tid] = true;
563 wroteToTimeBuffer = true;
564 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
565 dispatchStatus[tid] = Running;
571 DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
573 instQueue.wakeDependents(inst);
578 DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
580 instQueue.rescheduleMemInst(inst);
585 DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
587 instQueue.replayMemInst(inst);
592 DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
594 // This function should not be called after writebackInsts in a
595 // single cycle. That will cause problems with an instruction
596 // being added to the queue to commit without being processed by
597 // writebackInsts prior to being sent to commit.
599 // First check the time slot that this instruction will write
600 // to. If there are free write ports at the time, then go ahead
601 // and write the instruction to that time. If there are not,
602 // keep looking back to see where's the first time there's a
604 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
606 if (wbNumInst == wbWidth) {
611 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
614 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
615 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
616 // Add finished instruction to queue to commit.
617 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
618 (*iewQueue)[wbCycle].size++;
621 template <class Impl>
623 DefaultIEW<Impl>::validInstsFromRename()
625 unsigned inst_count = 0;
627 for (int i=0; i<fromRename->size; i++) {
628 if (!fromRename->insts[i]->isSquashed())
637 DefaultIEW<Impl>::skidInsert(ThreadID tid)
639 DynInstPtr inst = NULL;
641 while (!insts[tid].empty()) {
642 inst = insts[tid].front();
646 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
647 "dispatch skidBuffer %i\n",tid, inst->seqNum,
648 inst->pcState(),tid);
650 skidBuffer[tid].push(inst);
653 assert(skidBuffer[tid].size() <= skidBufferMax &&
654 "Skidbuffer Exceeded Max Size");
659 DefaultIEW<Impl>::skidCount()
663 list<ThreadID>::iterator threads = activeThreads->begin();
664 list<ThreadID>::iterator end = activeThreads->end();
666 while (threads != end) {
667 ThreadID tid = *threads++;
668 unsigned thread_count = skidBuffer[tid].size();
669 if (max < thread_count)
678 DefaultIEW<Impl>::skidsEmpty()
680 list<ThreadID>::iterator threads = activeThreads->begin();
681 list<ThreadID>::iterator end = activeThreads->end();
683 while (threads != end) {
684 ThreadID tid = *threads++;
686 if (!skidBuffer[tid].empty())
693 template <class Impl>
695 DefaultIEW<Impl>::updateStatus()
697 bool any_unblocking = false;
699 list<ThreadID>::iterator threads = activeThreads->begin();
700 list<ThreadID>::iterator end = activeThreads->end();
702 while (threads != end) {
703 ThreadID tid = *threads++;
705 if (dispatchStatus[tid] == Unblocking) {
706 any_unblocking = true;
711 // If there are no ready instructions waiting to be scheduled by the IQ,
712 // and there's no stores waiting to write back, and dispatch is not
713 // unblocking, then there is no internal activity for the IEW stage.
714 instQueue.intInstQueueReads++;
715 if (_status == Active && !instQueue.hasReadyInsts() &&
716 !ldstQueue.willWB() && !any_unblocking) {
717 DPRINTF(IEW, "IEW switching to idle\n");
722 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
723 ldstQueue.willWB() ||
725 // Otherwise there is internal activity. Set to active.
726 DPRINTF(IEW, "IEW switching to active\n");
734 template <class Impl>
736 DefaultIEW<Impl>::resetEntries()
738 instQueue.resetEntries();
739 ldstQueue.resetEntries();
742 template <class Impl>
744 DefaultIEW<Impl>::readStallSignals(ThreadID tid)
746 if (fromCommit->commitBlock[tid]) {
747 stalls[tid].commit = true;
750 if (fromCommit->commitUnblock[tid]) {
751 assert(stalls[tid].commit);
752 stalls[tid].commit = false;
756 template <class Impl>
758 DefaultIEW<Impl>::checkStall(ThreadID tid)
762 if (stalls[tid].commit) {
763 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
765 } else if (instQueue.isFull(tid)) {
766 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
768 } else if (ldstQueue.isFull(tid)) {
769 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
771 if (ldstQueue.numLoads(tid) > 0 ) {
773 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
774 tid,ldstQueue.getLoadHeadSeqNum(tid));
777 if (ldstQueue.numStores(tid) > 0) {
779 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
780 tid,ldstQueue.getStoreHeadSeqNum(tid));
784 } else if (ldstQueue.isStalled(tid)) {
785 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
792 template <class Impl>
794 DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
796 // Check if there's a squash signal, squash if there is
797 // Check stall signals, block if there is.
798 // If status was Blocked
799 // if so then go to unblocking
800 // If status was Squashing
801 // check if squashing is not high. Switch to running this cycle.
803 readStallSignals(tid);
805 if (fromCommit->commitInfo[tid].squash) {
808 if (dispatchStatus[tid] == Blocked ||
809 dispatchStatus[tid] == Unblocking) {
810 toRename->iewUnblock[tid] = true;
811 wroteToTimeBuffer = true;
814 dispatchStatus[tid] = Squashing;
815 fetchRedirect[tid] = false;
819 if (fromCommit->commitInfo[tid].robSquashing) {
820 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
822 dispatchStatus[tid] = Squashing;
823 emptyRenameInsts(tid);
824 wroteToTimeBuffer = true;
828 if (checkStall(tid)) {
830 dispatchStatus[tid] = Blocked;
834 if (dispatchStatus[tid] == Blocked) {
835 // Status from previous cycle was blocked, but there are no more stall
836 // conditions. Switch over to unblocking.
837 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
840 dispatchStatus[tid] = Unblocking;
847 if (dispatchStatus[tid] == Squashing) {
848 // Switch status to running if rename isn't being told to block or
849 // squash this cycle.
850 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
853 dispatchStatus[tid] = Running;
859 template <class Impl>
861 DefaultIEW<Impl>::sortInsts()
863 int insts_from_rename = fromRename->size;
865 for (ThreadID tid = 0; tid < numThreads; tid++)
866 assert(insts[tid].empty());
868 for (int i = 0; i < insts_from_rename; ++i) {
869 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
873 template <class Impl>
875 DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
877 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
879 while (!insts[tid].empty()) {
881 if (insts[tid].front()->isLoad() ||
882 insts[tid].front()->isStore() ) {
883 toRename->iewInfo[tid].dispatchedToLSQ++;
886 toRename->iewInfo[tid].dispatched++;
892 template <class Impl>
894 DefaultIEW<Impl>::wakeCPU()
899 template <class Impl>
901 DefaultIEW<Impl>::activityThisCycle()
903 DPRINTF(Activity, "Activity this cycle.\n");
904 cpu->activityThisCycle();
907 template <class Impl>
909 DefaultIEW<Impl>::activateStage()
911 DPRINTF(Activity, "Activating stage.\n");
912 cpu->activateStage(O3CPU::IEWIdx);
915 template <class Impl>
917 DefaultIEW<Impl>::deactivateStage()
919 DPRINTF(Activity, "Deactivating stage.\n");
920 cpu->deactivateStage(O3CPU::IEWIdx);
925 DefaultIEW<Impl>::dispatch(ThreadID tid)
927 // If status is Running or idle,
928 // call dispatchInsts()
929 // If status is Unblocking,
930 // buffer any instructions coming from rename
931 // continue trying to empty skid buffer
932 // check if stall conditions have passed
934 if (dispatchStatus[tid] == Blocked) {
937 } else if (dispatchStatus[tid] == Squashing) {
941 // Dispatch should try to dispatch as many instructions as its bandwidth
942 // will allow, as long as it is not currently blocked.
943 if (dispatchStatus[tid] == Running ||
944 dispatchStatus[tid] == Idle) {
945 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
949 } else if (dispatchStatus[tid] == Unblocking) {
950 // Make sure that the skid buffer has something in it if the
951 // status is unblocking.
952 assert(!skidsEmpty());
954 // If the status was unblocking, then instructions from the skid
955 // buffer were used. Remove those instructions and handle
956 // the rest of unblocking.
961 if (validInstsFromRename()) {
962 // Add the current inputs to the skid buffer so they can be
963 // reprocessed when this stage unblocks.
971 template <class Impl>
973 DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
975 // Obtain instructions from skid buffer if unblocking, or queue from rename
977 std::queue<DynInstPtr> &insts_to_dispatch =
978 dispatchStatus[tid] == Unblocking ?
979 skidBuffer[tid] : insts[tid];
981 int insts_to_add = insts_to_dispatch.size();
984 bool add_to_iq = false;
985 int dis_num_inst = 0;
987 // Loop through the instructions, putting them in the instruction
989 for ( ; dis_num_inst < insts_to_add &&
990 dis_num_inst < dispatchWidth;
993 inst = insts_to_dispatch.front();
995 if (dispatchStatus[tid] == Unblocking) {
996 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1000 // Make sure there's a valid instruction there.
1003 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
1005 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1007 // Be sure to mark these instructions as ready so that the
1008 // commit stage can go ahead and execute them, and mark
1009 // them as issued so the IQ doesn't reprocess them.
1011 // Check for squashed instructions.
1012 if (inst->isSquashed()) {
1013 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1014 "not adding to IQ.\n", tid);
1016 ++iewDispSquashedInsts;
1018 insts_to_dispatch.pop();
1020 //Tell Rename That An Instruction has been processed
1021 if (inst->isLoad() || inst->isStore()) {
1022 toRename->iewInfo[tid].dispatchedToLSQ++;
1024 toRename->iewInfo[tid].dispatched++;
1029 // Check for full conditions.
1030 if (instQueue.isFull(tid)) {
1031 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1033 // Call function to start blocking.
1036 // Set unblock to false. Special case where we are using
1037 // skidbuffer (unblocking) instructions but then we still
1038 // get full in the IQ.
1039 toRename->iewUnblock[tid] = false;
1043 } else if (ldstQueue.isFull(tid)) {
1044 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1046 // Call function to start blocking.
1049 // Set unblock to false. Special case where we are using
1050 // skidbuffer (unblocking) instructions but then we still
1051 // get full in the IQ.
1052 toRename->iewUnblock[tid] = false;
1058 // Otherwise issue the instruction just fine.
1059 if (inst->isLoad()) {
1060 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1061 "encountered, adding to LSQ.\n", tid);
1063 // Reserve a spot in the load store queue for this
1065 ldstQueue.insertLoad(inst);
1071 toRename->iewInfo[tid].dispatchedToLSQ++;
1072 } else if (inst->isStore()) {
1073 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1074 "encountered, adding to LSQ.\n", tid);
1076 ldstQueue.insertStore(inst);
1078 ++iewDispStoreInsts;
1080 if (inst->isStoreConditional()) {
1081 // Store conditionals need to be set as "canCommit()"
1082 // so that commit can process them when they reach the
1084 // @todo: This is somewhat specific to Alpha.
1085 inst->setCanCommit();
1086 instQueue.insertNonSpec(inst);
1089 ++iewDispNonSpecInsts;
1094 toRename->iewInfo[tid].dispatchedToLSQ++;
1095 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1096 // Same as non-speculative stores.
1097 inst->setCanCommit();
1098 instQueue.insertBarrier(inst);
1100 } else if (inst->isNop()) {
1101 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1102 "skipping.\n", tid);
1105 inst->setExecuted();
1106 inst->setCanCommit();
1108 instQueue.recordProducer(inst);
1110 iewExecutedNop[tid]++;
1113 } else if (inst->isExecuted()) {
1114 assert(0 && "Instruction shouldn't be executed.\n");
1115 DPRINTF(IEW, "Issue: Executed branch encountered, "
1119 inst->setCanCommit();
1121 instQueue.recordProducer(inst);
1127 if (inst->isNonSpeculative()) {
1128 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1129 "encountered, skipping.\n", tid);
1131 // Same as non-speculative stores.
1132 inst->setCanCommit();
1134 // Specifically insert it as nonspeculative.
1135 instQueue.insertNonSpec(inst);
1137 ++iewDispNonSpecInsts;
1142 // If the instruction queue is not full, then add the
1145 instQueue.insert(inst);
1148 insts_to_dispatch.pop();
1150 toRename->iewInfo[tid].dispatched++;
1152 ++iewDispatchedInsts;
1155 inst->dispatchTick = curTick() - inst->fetchTick;
1159 if (!insts_to_dispatch.empty()) {
1160 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1162 toRename->iewUnblock[tid] = false;
1165 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1166 dispatchStatus[tid] = Running;
1168 updatedQueues = true;
1174 template <class Impl>
1176 DefaultIEW<Impl>::printAvailableInsts()
1180 std::cout << "Available Instructions: ";
1182 while (fromIssue->insts[inst]) {
1184 if (inst%3==0) std::cout << "\n\t";
1186 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1187 << " TN: " << fromIssue->insts[inst]->threadNumber
1188 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1197 template <class Impl>
1199 DefaultIEW<Impl>::executeInsts()
1204 list<ThreadID>::iterator threads = activeThreads->begin();
1205 list<ThreadID>::iterator end = activeThreads->end();
1207 while (threads != end) {
1208 ThreadID tid = *threads++;
1209 fetchRedirect[tid] = false;
1212 // Uncomment this if you want to see all available instructions.
1213 // @todo This doesn't actually work anymore, we should fix it.
1214 // printAvailableInsts();
1216 // Execute/writeback any instructions that are available.
1217 int insts_to_execute = fromIssue->size;
1219 for (; inst_num < insts_to_execute;
1222 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1224 DynInstPtr inst = instQueue.getInstToExecute();
1226 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1227 inst->pcState(), inst->threadNumber,inst->seqNum);
1229 // Check if the instruction is squashed; if so then skip it
1230 if (inst->isSquashed()) {
1231 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1232 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1235 // Consider this instruction executed so that commit can go
1236 // ahead and retire the instruction.
1237 inst->setExecuted();
1239 // Not sure if I should set this here or just let commit try to
1240 // commit any squashed instructions. I like the latter a bit more.
1241 inst->setCanCommit();
1243 ++iewExecSquashedInsts;
1245 decrWb(inst->seqNum);
1249 Fault fault = NoFault;
1251 // Execute instruction.
1252 // Note that if the instruction faults, it will be handled
1253 // at the commit stage.
1254 if (inst->isMemRef()) {
1255 DPRINTF(IEW, "Execute: Calculating address for memory "
1258 // Tell the LDSTQ to execute this instruction (if it is a load).
1259 if (inst->isLoad()) {
1260 // Loads will mark themselves as executed, and their writeback
1261 // event adds the instruction to the queue to commit
1262 fault = ldstQueue.executeLoad(inst);
1264 if (inst->isTranslationDelayed() &&
1266 // A hw page table walk is currently going on; the
1267 // instruction must be deferred.
1268 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1270 instQueue.deferMemInst(inst);
1274 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1275 inst->fault = NoFault;
1277 } else if (inst->isStore()) {
1278 fault = ldstQueue.executeStore(inst);
1280 if (inst->isTranslationDelayed() &&
1282 // A hw page table walk is currently going on; the
1283 // instruction must be deferred.
1284 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1286 instQueue.deferMemInst(inst);
1290 // If the store had a fault then it may not have a mem req
1291 if (fault != NoFault || inst->readPredicate() == false ||
1292 !inst->isStoreConditional()) {
1293 // If the instruction faulted, then we need to send it along
1294 // to commit without the instruction completing.
1295 // Send this instruction to commit, also make sure iew stage
1296 // realizes there is activity.
1297 inst->setExecuted();
1299 activityThisCycle();
1302 // Store conditionals will mark themselves as
1303 // executed, and their writeback event will add the
1304 // instruction to the queue to commit.
1306 panic("Unexpected memory type!\n");
1310 // If the instruction has already faulted, then skip executing it.
1311 // Such case can happen when it faulted during ITLB translation.
1312 // If we execute the instruction (even if it's a nop) the fault
1313 // will be replaced and we will lose it.
1314 if (inst->getFault() == NoFault) {
1316 if (inst->readPredicate() == false)
1317 inst->forwardOldRegs();
1320 inst->setExecuted();
1325 updateExeInstStats(inst);
1327 // Check if branch prediction was correct, if not then we need
1328 // to tell commit to squash in flight instructions. Only
1329 // handle this if there hasn't already been something that
1330 // redirects fetch in this group of instructions.
1332 // This probably needs to prioritize the redirects if a different
1333 // scheduler is used. Currently the scheduler schedules the oldest
1334 // instruction first, so the branch resolution order will be correct.
1335 ThreadID tid = inst->threadNumber;
1337 if (!fetchRedirect[tid] ||
1338 !toCommit->squash[tid] ||
1339 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1341 // Prevent testing for misprediction on load instructions,
1342 // that have not been executed.
1343 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1345 if (inst->mispredicted() && !loadNotExecuted) {
1346 fetchRedirect[tid] = true;
1348 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1349 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1350 inst->readPredTarg());
1351 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1353 // If incorrect, then signal the ROB that it must be squashed.
1354 squashDueToBranch(inst, tid);
1356 if (inst->readPredTaken()) {
1357 predictedTakenIncorrect++;
1359 predictedNotTakenIncorrect++;
1361 } else if (ldstQueue.violation(tid)) {
1362 assert(inst->isMemRef());
1363 // If there was an ordering violation, then get the
1364 // DynInst that caused the violation. Note that this
1365 // clears the violation signal.
1366 DynInstPtr violator;
1367 violator = ldstQueue.getMemDepViolator(tid);
1369 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1370 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1371 violator->pcState(), violator->seqNum,
1372 inst->pcState(), inst->seqNum, inst->physEffAddr);
1374 fetchRedirect[tid] = true;
1376 // Tell the instruction queue that a violation has occured.
1377 instQueue.violation(inst, violator);
1380 squashDueToMemOrder(violator, tid);
1382 ++memOrderViolationEvents;
1383 } else if (ldstQueue.loadBlocked(tid) &&
1384 !ldstQueue.isLoadBlockedHandled(tid)) {
1385 fetchRedirect[tid] = true;
1387 DPRINTF(IEW, "Load operation couldn't execute because the "
1388 "memory system is blocked. PC: %s [sn:%lli]\n",
1389 inst->pcState(), inst->seqNum);
1391 squashDueToMemBlocked(inst, tid);
1394 // Reset any state associated with redirects that will not
1396 if (ldstQueue.violation(tid)) {
1397 assert(inst->isMemRef());
1399 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1401 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1402 "%s, inst PC: %s. Addr is: %#x.\n",
1403 violator->pcState(), inst->pcState(),
1405 DPRINTF(IEW, "Violation will not be handled because "
1406 "already squashing\n");
1408 ++memOrderViolationEvents;
1410 if (ldstQueue.loadBlocked(tid) &&
1411 !ldstQueue.isLoadBlockedHandled(tid)) {
1412 DPRINTF(IEW, "Load operation couldn't execute because the "
1413 "memory system is blocked. PC: %s [sn:%lli]\n",
1414 inst->pcState(), inst->seqNum);
1415 DPRINTF(IEW, "Blocked load will not be handled because "
1416 "already squashing\n");
1418 ldstQueue.setLoadBlockedHandled(tid);
1424 // Update and record activity if we processed any instructions.
1426 if (exeStatus == Idle) {
1427 exeStatus = Running;
1430 updatedQueues = true;
1432 cpu->activityThisCycle();
1435 // Need to reset this in case a writeback event needs to write into the
1436 // iew queue. That way the writeback event will write into the correct
1437 // spot in the queue.
1442 template <class Impl>
1444 DefaultIEW<Impl>::writebackInsts()
1446 // Loop through the head of the time buffer and wake any
1447 // dependents. These instructions are about to write back. Also
1448 // mark scoreboard that this instruction is finally complete.
1449 // Either have IEW have direct access to scoreboard, or have this
1450 // as part of backwards communication.
1451 for (int inst_num = 0; inst_num < wbWidth &&
1452 toCommit->insts[inst_num]; inst_num++) {
1453 DynInstPtr inst = toCommit->insts[inst_num];
1454 ThreadID tid = inst->threadNumber;
1456 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1457 inst->seqNum, inst->pcState());
1459 iewInstsToCommit[tid]++;
1461 // Some instructions will be sent to commit without having
1462 // executed because they need commit to handle them.
1463 // E.g. Uncached loads have not actually executed when they
1464 // are first sent to commit. Instead commit must tell the LSQ
1465 // when it's ready to execute the uncached load.
1466 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1467 int dependents = instQueue.wakeDependents(inst);
1469 for (int i = 0; i < inst->numDestRegs(); i++) {
1471 DPRINTF(IEW,"Setting Destination Register %i\n",
1472 inst->renamedDestRegIdx(i));
1473 scoreboard->setReg(inst->renamedDestRegIdx(i));
1477 producerInst[tid]++;
1478 consumerInst[tid]+= dependents;
1480 writebackCount[tid]++;
1483 decrWb(inst->seqNum);
1487 template<class Impl>
1489 DefaultIEW<Impl>::tick()
1494 wroteToTimeBuffer = false;
1495 updatedQueues = false;
1499 // Free function units marked as being freed this cycle.
1500 fuPool->processFreeUnits();
1502 list<ThreadID>::iterator threads = activeThreads->begin();
1503 list<ThreadID>::iterator end = activeThreads->end();
1505 // Check stall and squash signals, dispatch any instructions.
1506 while (threads != end) {
1507 ThreadID tid = *threads++;
1509 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1511 checkSignalsAndUpdate(tid);
1515 if (exeStatus != Squashing) {
1520 // Have the instruction queue try to schedule any ready instructions.
1521 // (In actuality, this scheduling is for instructions that will
1522 // be executed next cycle.)
1523 instQueue.scheduleReadyInsts();
1525 // Also should advance its own time buffers if the stage ran.
1526 // Not the best place for it, but this works (hopefully).
1527 issueToExecQueue.advance();
1530 bool broadcast_free_entries = false;
1532 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1534 updateLSQNextCycle = false;
1536 broadcast_free_entries = true;
1539 // Writeback any stores using any leftover bandwidth.
1540 ldstQueue.writebackStores();
1542 // Check the committed load/store signals to see if there's a load
1543 // or store to commit. Also check if it's being told to execute a
1544 // nonspeculative instruction.
1545 // This is pretty inefficient...
1547 threads = activeThreads->begin();
1548 while (threads != end) {
1549 ThreadID tid = (*threads++);
1551 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1553 // Update structures based on instructions committed.
1554 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1555 !fromCommit->commitInfo[tid].squash &&
1556 !fromCommit->commitInfo[tid].robSquashing) {
1558 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1560 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1562 updateLSQNextCycle = true;
1563 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1566 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1568 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1569 if (fromCommit->commitInfo[tid].uncached) {
1570 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1571 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1573 instQueue.scheduleNonSpec(
1574 fromCommit->commitInfo[tid].nonSpecSeqNum);
1578 if (broadcast_free_entries) {
1579 toFetch->iewInfo[tid].iqCount =
1580 instQueue.getCount(tid);
1581 toFetch->iewInfo[tid].ldstqCount =
1582 ldstQueue.getCount(tid);
1584 toRename->iewInfo[tid].usedIQ = true;
1585 toRename->iewInfo[tid].freeIQEntries =
1586 instQueue.numFreeEntries();
1587 toRename->iewInfo[tid].usedLSQ = true;
1588 toRename->iewInfo[tid].freeLSQEntries =
1589 ldstQueue.numFreeEntries(tid);
1591 wroteToTimeBuffer = true;
1594 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1595 tid, toRename->iewInfo[tid].dispatched);
1598 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1599 "LSQ has %i free entries.\n",
1600 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1601 ldstQueue.numFreeEntries());
1605 if (wroteToTimeBuffer) {
1606 DPRINTF(Activity, "Activity this cycle.\n");
1607 cpu->activityThisCycle();
1611 template <class Impl>
1613 DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1615 ThreadID tid = inst->threadNumber;
1620 inst->completeTick = curTick() - inst->fetchTick;
1624 // Control operations
1626 if (inst->isControl())
1627 iewExecutedBranches[tid]++;
1630 // Memory operations
1632 if (inst->isMemRef()) {
1633 iewExecutedRefs[tid]++;
1635 if (inst->isLoad()) {
1636 iewExecLoadInsts[tid]++;
1641 template <class Impl>
1643 DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1645 ThreadID tid = inst->threadNumber;
1647 if (!fetchRedirect[tid] ||
1648 !toCommit->squash[tid] ||
1649 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1651 if (inst->mispredicted()) {
1652 fetchRedirect[tid] = true;
1654 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1655 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1656 inst->predInstAddr(), inst->predNextInstAddr());
1657 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1658 " NPC: %#x.\n", inst->nextInstAddr(),
1659 inst->nextInstAddr());
1660 // If incorrect, then signal the ROB that it must be squashed.
1661 squashDueToBranch(inst, tid);
1663 if (inst->readPredTaken()) {
1664 predictedTakenIncorrect++;
1666 predictedNotTakenIncorrect++;