2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
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43 // @todo: Fix the instantaneous communication among all the stages within
44 // iew. There's a clear delay between issue and execute, yet backwards
45 // communication happens simultaneously.
49 #include "config/the_isa.hh"
50 #include "cpu/o3/fu_pool.hh"
51 #include "cpu/o3/iew.hh"
52 #include "cpu/timebuf.hh"
53 #include "params/DerivO3CPU.hh"
58 DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
59 : issueToExecQueue(params->backComSize, params->forwardComSize),
61 instQueue(_cpu, this, params),
62 ldstQueue(_cpu, this, params),
63 fuPool(params->fuPool),
64 commitToIEWDelay(params->commitToIEWDelay),
65 renameToIEWDelay(params->renameToIEWDelay),
66 issueToExecuteDelay(params->issueToExecuteDelay),
67 dispatchWidth(params->dispatchWidth),
68 issueWidth(params->issueWidth),
70 wbWidth(params->wbWidth),
71 numThreads(params->numThreads),
78 // Setup wire to read instructions coming from issue.
79 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
81 // Instruction queue needs the queue between issue and execute.
82 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
84 for (ThreadID tid = 0; tid < numThreads; tid++) {
85 dispatchStatus[tid] = Running;
86 stalls[tid].commit = false;
87 fetchRedirect[tid] = false;
90 wbMax = wbWidth * params->wbDepth;
92 updateLSQNextCycle = false;
96 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
101 DefaultIEW<Impl>::name() const
103 return cpu->name() + ".iew";
106 template <class Impl>
108 DefaultIEW<Impl>::regStats()
110 using namespace Stats;
112 instQueue.regStats();
113 ldstQueue.regStats();
116 .name(name() + ".iewIdleCycles")
117 .desc("Number of cycles IEW is idle");
120 .name(name() + ".iewSquashCycles")
121 .desc("Number of cycles IEW is squashing");
124 .name(name() + ".iewBlockCycles")
125 .desc("Number of cycles IEW is blocking");
128 .name(name() + ".iewUnblockCycles")
129 .desc("Number of cycles IEW is unblocking");
132 .name(name() + ".iewDispatchedInsts")
133 .desc("Number of instructions dispatched to IQ");
136 .name(name() + ".iewDispSquashedInsts")
137 .desc("Number of squashed instructions skipped by dispatch");
140 .name(name() + ".iewDispLoadInsts")
141 .desc("Number of dispatched load instructions");
144 .name(name() + ".iewDispStoreInsts")
145 .desc("Number of dispatched store instructions");
148 .name(name() + ".iewDispNonSpecInsts")
149 .desc("Number of dispatched non-speculative instructions");
152 .name(name() + ".iewIQFullEvents")
153 .desc("Number of times the IQ has become full, causing a stall");
156 .name(name() + ".iewLSQFullEvents")
157 .desc("Number of times the LSQ has become full, causing a stall");
159 memOrderViolationEvents
160 .name(name() + ".memOrderViolationEvents")
161 .desc("Number of memory order violations");
163 predictedTakenIncorrect
164 .name(name() + ".predictedTakenIncorrect")
165 .desc("Number of branches that were predicted taken incorrectly");
167 predictedNotTakenIncorrect
168 .name(name() + ".predictedNotTakenIncorrect")
169 .desc("Number of branches that were predicted not taken incorrectly");
172 .name(name() + ".branchMispredicts")
173 .desc("Number of branch mispredicts detected at execute");
175 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
178 .name(name() + ".iewExecutedInsts")
179 .desc("Number of executed instructions");
182 .init(cpu->numThreads)
183 .name(name() + ".iewExecLoadInsts")
184 .desc("Number of load instructions executed")
188 .name(name() + ".iewExecSquashedInsts")
189 .desc("Number of squashed instructions skipped in execute");
192 .init(cpu->numThreads)
193 .name(name() + ".EXEC:swp")
194 .desc("number of swp insts executed")
198 .init(cpu->numThreads)
199 .name(name() + ".EXEC:nop")
200 .desc("number of nop insts executed")
204 .init(cpu->numThreads)
205 .name(name() + ".EXEC:refs")
206 .desc("number of memory reference insts executed")
210 .init(cpu->numThreads)
211 .name(name() + ".EXEC:branches")
212 .desc("Number of branches executed")
216 .name(name() + ".EXEC:stores")
217 .desc("Number of stores executed")
219 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
222 .name(name() + ".EXEC:rate")
223 .desc("Inst execution rate")
226 iewExecRate = iewExecutedInsts / cpu->numCycles;
229 .init(cpu->numThreads)
230 .name(name() + ".WB:sent")
231 .desc("cumulative count of insts sent to commit")
235 .init(cpu->numThreads)
236 .name(name() + ".WB:count")
237 .desc("cumulative count of insts written-back")
241 .init(cpu->numThreads)
242 .name(name() + ".WB:producers")
243 .desc("num instructions producing a value")
247 .init(cpu->numThreads)
248 .name(name() + ".WB:consumers")
249 .desc("num instructions consuming a value")
253 .init(cpu->numThreads)
254 .name(name() + ".WB:penalized")
255 .desc("number of instrctions required to write to 'other' IQ")
259 .name(name() + ".WB:penalized_rate")
260 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
263 wbPenalizedRate = wbPenalized / writebackCount;
266 .name(name() + ".WB:fanout")
267 .desc("average fanout of values written-back")
270 wbFanout = producerInst / consumerInst;
273 .name(name() + ".WB:rate")
274 .desc("insts written-back per cycle")
276 wbRate = writebackCount / cpu->numCycles;
281 DefaultIEW<Impl>::initStage()
283 for (ThreadID tid = 0; tid < numThreads; tid++) {
284 toRename->iewInfo[tid].usedIQ = true;
285 toRename->iewInfo[tid].freeIQEntries =
286 instQueue.numFreeEntries(tid);
288 toRename->iewInfo[tid].usedLSQ = true;
289 toRename->iewInfo[tid].freeLSQEntries =
290 ldstQueue.numFreeEntries(tid);
293 cpu->activateStage(O3CPU::IEWIdx);
298 DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
302 // Setup wire to read information from time buffer, from commit.
303 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
305 // Setup wire to write information back to previous stages.
306 toRename = timeBuffer->getWire(0);
308 toFetch = timeBuffer->getWire(0);
310 // Instruction queue also needs main time buffer.
311 instQueue.setTimeBuffer(tb_ptr);
316 DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
318 renameQueue = rq_ptr;
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
326 DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
330 // Setup wire to write instructions to commit.
331 toCommit = iewQueue->getWire(0);
336 DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
338 activeThreads = at_ptr;
340 ldstQueue.setActiveThreads(at_ptr);
341 instQueue.setActiveThreads(at_ptr);
346 DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
351 template <class Impl>
353 DefaultIEW<Impl>::drain()
355 // IEW is ready to drain at any time.
356 cpu->signalDrained();
360 template <class Impl>
362 DefaultIEW<Impl>::resume()
366 template <class Impl>
368 DefaultIEW<Impl>::switchOut()
372 assert(insts[0].empty());
373 assert(skidBuffer[0].empty());
375 instQueue.switchOut();
376 ldstQueue.switchOut();
379 for (ThreadID tid = 0; tid < numThreads; tid++) {
380 while (!insts[tid].empty())
382 while (!skidBuffer[tid].empty())
383 skidBuffer[tid].pop();
387 template <class Impl>
389 DefaultIEW<Impl>::takeOverFrom()
397 instQueue.takeOverFrom();
398 ldstQueue.takeOverFrom();
399 fuPool->takeOverFrom();
402 cpu->activityThisCycle();
404 for (ThreadID tid = 0; tid < numThreads; tid++) {
405 dispatchStatus[tid] = Running;
406 stalls[tid].commit = false;
407 fetchRedirect[tid] = false;
410 updateLSQNextCycle = false;
412 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
413 issueToExecQueue.advance();
419 DefaultIEW<Impl>::squash(ThreadID tid)
421 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
423 // Tell the IQ to start squashing.
424 instQueue.squash(tid);
426 // Tell the LDSTQ to start squashing.
427 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428 updatedQueues = true;
430 // Clear the skid buffer in case it has any data in it.
431 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
432 tid, fromCommit->commitInfo[tid].doneSeqNum);
434 while (!skidBuffer[tid].empty()) {
435 if (skidBuffer[tid].front()->isLoad() ||
436 skidBuffer[tid].front()->isStore() ) {
437 toRename->iewInfo[tid].dispatchedToLSQ++;
440 toRename->iewInfo[tid].dispatched++;
442 skidBuffer[tid].pop();
445 emptyRenameInsts(tid);
450 DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
452 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
455 if (toCommit->squash[tid] == false ||
456 inst->seqNum < toCommit->squashedSeqNum[tid]) {
457 toCommit->squash[tid] = true;
458 toCommit->squashedSeqNum[tid] = inst->seqNum;
459 toCommit->branchTaken[tid] = inst->pcState().branching();
461 TheISA::PCState pc = inst->pcState();
462 TheISA::advancePC(pc, inst->staticInst);
464 toCommit->pc[tid] = pc;
465 toCommit->mispredictInst[tid] = inst;
466 toCommit->includeSquashInst[tid] = false;
468 wroteToTimeBuffer = true;
475 DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
477 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
478 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
480 if (toCommit->squash[tid] == false ||
481 inst->seqNum < toCommit->squashedSeqNum[tid]) {
482 toCommit->squash[tid] = true;
483 toCommit->squashedSeqNum[tid] = inst->seqNum;
484 TheISA::PCState pc = inst->pcState();
485 TheISA::advancePC(pc, inst->staticInst);
486 toCommit->pc[tid] = pc;
487 toCommit->mispredictInst[tid] = NULL;
489 toCommit->includeSquashInst[tid] = false;
491 wroteToTimeBuffer = true;
497 DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
499 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
500 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
501 if (toCommit->squash[tid] == false ||
502 inst->seqNum < toCommit->squashedSeqNum[tid]) {
503 toCommit->squash[tid] = true;
505 toCommit->squashedSeqNum[tid] = inst->seqNum;
506 toCommit->pc[tid] = inst->pcState();
507 toCommit->mispredictInst[tid] = NULL;
509 // Must include the broadcasted SN in the squash.
510 toCommit->includeSquashInst[tid] = true;
512 ldstQueue.setLoadBlockedHandled(tid);
514 wroteToTimeBuffer = true;
520 DefaultIEW<Impl>::block(ThreadID tid)
522 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
524 if (dispatchStatus[tid] != Blocked &&
525 dispatchStatus[tid] != Unblocking) {
526 toRename->iewBlock[tid] = true;
527 wroteToTimeBuffer = true;
530 // Add the current inputs to the skid buffer so they can be
531 // reprocessed when this stage unblocks.
534 dispatchStatus[tid] = Blocked;
539 DefaultIEW<Impl>::unblock(ThreadID tid)
541 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
542 "buffer %u.\n",tid, tid);
544 // If the skid bufffer is empty, signal back to previous stages to unblock.
545 // Also switch status to running.
546 if (skidBuffer[tid].empty()) {
547 toRename->iewUnblock[tid] = true;
548 wroteToTimeBuffer = true;
549 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
550 dispatchStatus[tid] = Running;
556 DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
558 instQueue.wakeDependents(inst);
563 DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
565 instQueue.rescheduleMemInst(inst);
570 DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
572 instQueue.replayMemInst(inst);
577 DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
579 // This function should not be called after writebackInsts in a
580 // single cycle. That will cause problems with an instruction
581 // being added to the queue to commit without being processed by
582 // writebackInsts prior to being sent to commit.
584 // First check the time slot that this instruction will write
585 // to. If there are free write ports at the time, then go ahead
586 // and write the instruction to that time. If there are not,
587 // keep looking back to see where's the first time there's a
589 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
591 if (wbNumInst == wbWidth) {
596 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
599 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
600 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
601 // Add finished instruction to queue to commit.
602 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
603 (*iewQueue)[wbCycle].size++;
606 template <class Impl>
608 DefaultIEW<Impl>::validInstsFromRename()
610 unsigned inst_count = 0;
612 for (int i=0; i<fromRename->size; i++) {
613 if (!fromRename->insts[i]->isSquashed())
622 DefaultIEW<Impl>::skidInsert(ThreadID tid)
624 DynInstPtr inst = NULL;
626 while (!insts[tid].empty()) {
627 inst = insts[tid].front();
631 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
632 "dispatch skidBuffer %i\n",tid, inst->seqNum,
633 inst->pcState(),tid);
635 skidBuffer[tid].push(inst);
638 assert(skidBuffer[tid].size() <= skidBufferMax &&
639 "Skidbuffer Exceeded Max Size");
644 DefaultIEW<Impl>::skidCount()
648 list<ThreadID>::iterator threads = activeThreads->begin();
649 list<ThreadID>::iterator end = activeThreads->end();
651 while (threads != end) {
652 ThreadID tid = *threads++;
653 unsigned thread_count = skidBuffer[tid].size();
654 if (max < thread_count)
663 DefaultIEW<Impl>::skidsEmpty()
665 list<ThreadID>::iterator threads = activeThreads->begin();
666 list<ThreadID>::iterator end = activeThreads->end();
668 while (threads != end) {
669 ThreadID tid = *threads++;
671 if (!skidBuffer[tid].empty())
678 template <class Impl>
680 DefaultIEW<Impl>::updateStatus()
682 bool any_unblocking = false;
684 list<ThreadID>::iterator threads = activeThreads->begin();
685 list<ThreadID>::iterator end = activeThreads->end();
687 while (threads != end) {
688 ThreadID tid = *threads++;
690 if (dispatchStatus[tid] == Unblocking) {
691 any_unblocking = true;
696 // If there are no ready instructions waiting to be scheduled by the IQ,
697 // and there's no stores waiting to write back, and dispatch is not
698 // unblocking, then there is no internal activity for the IEW stage.
699 instQueue.intInstQueueReads++;
700 if (_status == Active && !instQueue.hasReadyInsts() &&
701 !ldstQueue.willWB() && !any_unblocking) {
702 DPRINTF(IEW, "IEW switching to idle\n");
707 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
708 ldstQueue.willWB() ||
710 // Otherwise there is internal activity. Set to active.
711 DPRINTF(IEW, "IEW switching to active\n");
719 template <class Impl>
721 DefaultIEW<Impl>::resetEntries()
723 instQueue.resetEntries();
724 ldstQueue.resetEntries();
727 template <class Impl>
729 DefaultIEW<Impl>::readStallSignals(ThreadID tid)
731 if (fromCommit->commitBlock[tid]) {
732 stalls[tid].commit = true;
735 if (fromCommit->commitUnblock[tid]) {
736 assert(stalls[tid].commit);
737 stalls[tid].commit = false;
741 template <class Impl>
743 DefaultIEW<Impl>::checkStall(ThreadID tid)
747 if (stalls[tid].commit) {
748 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
750 } else if (instQueue.isFull(tid)) {
751 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
753 } else if (ldstQueue.isFull(tid)) {
754 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
756 if (ldstQueue.numLoads(tid) > 0 ) {
758 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
759 tid,ldstQueue.getLoadHeadSeqNum(tid));
762 if (ldstQueue.numStores(tid) > 0) {
764 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
765 tid,ldstQueue.getStoreHeadSeqNum(tid));
769 } else if (ldstQueue.isStalled(tid)) {
770 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
777 template <class Impl>
779 DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
781 // Check if there's a squash signal, squash if there is
782 // Check stall signals, block if there is.
783 // If status was Blocked
784 // if so then go to unblocking
785 // If status was Squashing
786 // check if squashing is not high. Switch to running this cycle.
788 readStallSignals(tid);
790 if (fromCommit->commitInfo[tid].squash) {
793 if (dispatchStatus[tid] == Blocked ||
794 dispatchStatus[tid] == Unblocking) {
795 toRename->iewUnblock[tid] = true;
796 wroteToTimeBuffer = true;
799 dispatchStatus[tid] = Squashing;
800 fetchRedirect[tid] = false;
804 if (fromCommit->commitInfo[tid].robSquashing) {
805 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
807 dispatchStatus[tid] = Squashing;
808 emptyRenameInsts(tid);
809 wroteToTimeBuffer = true;
813 if (checkStall(tid)) {
815 dispatchStatus[tid] = Blocked;
819 if (dispatchStatus[tid] == Blocked) {
820 // Status from previous cycle was blocked, but there are no more stall
821 // conditions. Switch over to unblocking.
822 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
825 dispatchStatus[tid] = Unblocking;
832 if (dispatchStatus[tid] == Squashing) {
833 // Switch status to running if rename isn't being told to block or
834 // squash this cycle.
835 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
838 dispatchStatus[tid] = Running;
844 template <class Impl>
846 DefaultIEW<Impl>::sortInsts()
848 int insts_from_rename = fromRename->size;
850 for (ThreadID tid = 0; tid < numThreads; tid++)
851 assert(insts[tid].empty());
853 for (int i = 0; i < insts_from_rename; ++i) {
854 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
858 template <class Impl>
860 DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
862 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
864 while (!insts[tid].empty()) {
866 if (insts[tid].front()->isLoad() ||
867 insts[tid].front()->isStore() ) {
868 toRename->iewInfo[tid].dispatchedToLSQ++;
871 toRename->iewInfo[tid].dispatched++;
877 template <class Impl>
879 DefaultIEW<Impl>::wakeCPU()
884 template <class Impl>
886 DefaultIEW<Impl>::activityThisCycle()
888 DPRINTF(Activity, "Activity this cycle.\n");
889 cpu->activityThisCycle();
892 template <class Impl>
894 DefaultIEW<Impl>::activateStage()
896 DPRINTF(Activity, "Activating stage.\n");
897 cpu->activateStage(O3CPU::IEWIdx);
900 template <class Impl>
902 DefaultIEW<Impl>::deactivateStage()
904 DPRINTF(Activity, "Deactivating stage.\n");
905 cpu->deactivateStage(O3CPU::IEWIdx);
910 DefaultIEW<Impl>::dispatch(ThreadID tid)
912 // If status is Running or idle,
913 // call dispatchInsts()
914 // If status is Unblocking,
915 // buffer any instructions coming from rename
916 // continue trying to empty skid buffer
917 // check if stall conditions have passed
919 if (dispatchStatus[tid] == Blocked) {
922 } else if (dispatchStatus[tid] == Squashing) {
926 // Dispatch should try to dispatch as many instructions as its bandwidth
927 // will allow, as long as it is not currently blocked.
928 if (dispatchStatus[tid] == Running ||
929 dispatchStatus[tid] == Idle) {
930 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
934 } else if (dispatchStatus[tid] == Unblocking) {
935 // Make sure that the skid buffer has something in it if the
936 // status is unblocking.
937 assert(!skidsEmpty());
939 // If the status was unblocking, then instructions from the skid
940 // buffer were used. Remove those instructions and handle
941 // the rest of unblocking.
946 if (validInstsFromRename()) {
947 // Add the current inputs to the skid buffer so they can be
948 // reprocessed when this stage unblocks.
956 template <class Impl>
958 DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
960 // Obtain instructions from skid buffer if unblocking, or queue from rename
962 std::queue<DynInstPtr> &insts_to_dispatch =
963 dispatchStatus[tid] == Unblocking ?
964 skidBuffer[tid] : insts[tid];
966 int insts_to_add = insts_to_dispatch.size();
969 bool add_to_iq = false;
970 int dis_num_inst = 0;
972 // Loop through the instructions, putting them in the instruction
974 for ( ; dis_num_inst < insts_to_add &&
975 dis_num_inst < dispatchWidth;
978 inst = insts_to_dispatch.front();
980 if (dispatchStatus[tid] == Unblocking) {
981 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
985 // Make sure there's a valid instruction there.
988 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
990 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
992 // Be sure to mark these instructions as ready so that the
993 // commit stage can go ahead and execute them, and mark
994 // them as issued so the IQ doesn't reprocess them.
996 // Check for squashed instructions.
997 if (inst->isSquashed()) {
998 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
999 "not adding to IQ.\n", tid);
1001 ++iewDispSquashedInsts;
1003 insts_to_dispatch.pop();
1005 //Tell Rename That An Instruction has been processed
1006 if (inst->isLoad() || inst->isStore()) {
1007 toRename->iewInfo[tid].dispatchedToLSQ++;
1009 toRename->iewInfo[tid].dispatched++;
1014 // Check for full conditions.
1015 if (instQueue.isFull(tid)) {
1016 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1018 // Call function to start blocking.
1021 // Set unblock to false. Special case where we are using
1022 // skidbuffer (unblocking) instructions but then we still
1023 // get full in the IQ.
1024 toRename->iewUnblock[tid] = false;
1028 } else if (ldstQueue.isFull(tid)) {
1029 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1031 // Call function to start blocking.
1034 // Set unblock to false. Special case where we are using
1035 // skidbuffer (unblocking) instructions but then we still
1036 // get full in the IQ.
1037 toRename->iewUnblock[tid] = false;
1043 // Otherwise issue the instruction just fine.
1044 if (inst->isLoad()) {
1045 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1046 "encountered, adding to LSQ.\n", tid);
1048 // Reserve a spot in the load store queue for this
1050 ldstQueue.insertLoad(inst);
1056 toRename->iewInfo[tid].dispatchedToLSQ++;
1057 } else if (inst->isStore()) {
1058 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1059 "encountered, adding to LSQ.\n", tid);
1061 ldstQueue.insertStore(inst);
1063 ++iewDispStoreInsts;
1065 if (inst->isStoreConditional()) {
1066 // Store conditionals need to be set as "canCommit()"
1067 // so that commit can process them when they reach the
1069 // @todo: This is somewhat specific to Alpha.
1070 inst->setCanCommit();
1071 instQueue.insertNonSpec(inst);
1074 ++iewDispNonSpecInsts;
1079 toRename->iewInfo[tid].dispatchedToLSQ++;
1080 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1081 // Same as non-speculative stores.
1082 inst->setCanCommit();
1083 instQueue.insertBarrier(inst);
1085 } else if (inst->isNop()) {
1086 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1087 "skipping.\n", tid);
1090 inst->setExecuted();
1091 inst->setCanCommit();
1093 instQueue.recordProducer(inst);
1095 iewExecutedNop[tid]++;
1098 } else if (inst->isExecuted()) {
1099 assert(0 && "Instruction shouldn't be executed.\n");
1100 DPRINTF(IEW, "Issue: Executed branch encountered, "
1104 inst->setCanCommit();
1106 instQueue.recordProducer(inst);
1112 if (inst->isNonSpeculative()) {
1113 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1114 "encountered, skipping.\n", tid);
1116 // Same as non-speculative stores.
1117 inst->setCanCommit();
1119 // Specifically insert it as nonspeculative.
1120 instQueue.insertNonSpec(inst);
1122 ++iewDispNonSpecInsts;
1127 // If the instruction queue is not full, then add the
1130 instQueue.insert(inst);
1133 insts_to_dispatch.pop();
1135 toRename->iewInfo[tid].dispatched++;
1137 ++iewDispatchedInsts;
1140 if (!insts_to_dispatch.empty()) {
1141 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1143 toRename->iewUnblock[tid] = false;
1146 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1147 dispatchStatus[tid] = Running;
1149 updatedQueues = true;
1155 template <class Impl>
1157 DefaultIEW<Impl>::printAvailableInsts()
1161 std::cout << "Available Instructions: ";
1163 while (fromIssue->insts[inst]) {
1165 if (inst%3==0) std::cout << "\n\t";
1167 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1168 << " TN: " << fromIssue->insts[inst]->threadNumber
1169 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1178 template <class Impl>
1180 DefaultIEW<Impl>::executeInsts()
1185 list<ThreadID>::iterator threads = activeThreads->begin();
1186 list<ThreadID>::iterator end = activeThreads->end();
1188 while (threads != end) {
1189 ThreadID tid = *threads++;
1190 fetchRedirect[tid] = false;
1193 // Uncomment this if you want to see all available instructions.
1194 // @todo This doesn't actually work anymore, we should fix it.
1195 // printAvailableInsts();
1197 // Execute/writeback any instructions that are available.
1198 int insts_to_execute = fromIssue->size;
1200 for (; inst_num < insts_to_execute;
1203 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1205 DynInstPtr inst = instQueue.getInstToExecute();
1207 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1208 inst->pcState(), inst->threadNumber,inst->seqNum);
1210 // Check if the instruction is squashed; if so then skip it
1211 if (inst->isSquashed()) {
1212 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1214 // Consider this instruction executed so that commit can go
1215 // ahead and retire the instruction.
1216 inst->setExecuted();
1218 // Not sure if I should set this here or just let commit try to
1219 // commit any squashed instructions. I like the latter a bit more.
1220 inst->setCanCommit();
1222 ++iewExecSquashedInsts;
1224 decrWb(inst->seqNum);
1228 Fault fault = NoFault;
1230 // Execute instruction.
1231 // Note that if the instruction faults, it will be handled
1232 // at the commit stage.
1233 if (inst->isMemRef()) {
1234 DPRINTF(IEW, "Execute: Calculating address for memory "
1237 // Tell the LDSTQ to execute this instruction (if it is a load).
1238 if (inst->isLoad()) {
1239 // Loads will mark themselves as executed, and their writeback
1240 // event adds the instruction to the queue to commit
1241 fault = ldstQueue.executeLoad(inst);
1243 if (inst->isTranslationDelayed() &&
1245 // A hw page table walk is currently going on; the
1246 // instruction must be deferred.
1247 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1249 instQueue.deferMemInst(inst);
1253 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1254 inst->fault = NoFault;
1256 } else if (inst->isStore()) {
1257 fault = ldstQueue.executeStore(inst);
1259 if (inst->isTranslationDelayed() &&
1261 // A hw page table walk is currently going on; the
1262 // instruction must be deferred.
1263 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1265 instQueue.deferMemInst(inst);
1269 // If the store had a fault then it may not have a mem req
1270 if (fault != NoFault || inst->readPredicate() == false ||
1271 !inst->isStoreConditional()) {
1272 // If the instruction faulted, then we need to send it along
1273 // to commit without the instruction completing.
1274 // Send this instruction to commit, also make sure iew stage
1275 // realizes there is activity.
1276 inst->setExecuted();
1278 activityThisCycle();
1281 // Store conditionals will mark themselves as
1282 // executed, and their writeback event will add the
1283 // instruction to the queue to commit.
1285 panic("Unexpected memory type!\n");
1289 // If the instruction has already faulted, then skip executing it.
1290 // Such case can happen when it faulted during ITLB translation.
1291 // If we execute the instruction (even if it's a nop) the fault
1292 // will be replaced and we will lose it.
1293 if (inst->getFault() == NoFault) {
1295 if (inst->readPredicate() == false)
1296 inst->forwardOldRegs();
1299 inst->setExecuted();
1304 updateExeInstStats(inst);
1306 // Check if branch prediction was correct, if not then we need
1307 // to tell commit to squash in flight instructions. Only
1308 // handle this if there hasn't already been something that
1309 // redirects fetch in this group of instructions.
1311 // This probably needs to prioritize the redirects if a different
1312 // scheduler is used. Currently the scheduler schedules the oldest
1313 // instruction first, so the branch resolution order will be correct.
1314 ThreadID tid = inst->threadNumber;
1316 if (!fetchRedirect[tid] ||
1317 !toCommit->squash[tid] ||
1318 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1320 // Prevent testing for misprediction on load instructions,
1321 // that have not been executed.
1322 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1324 if (inst->mispredicted() && !loadNotExecuted) {
1325 fetchRedirect[tid] = true;
1327 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1328 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1329 inst->predInstAddr(), inst->predNextInstAddr());
1330 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1331 inst->pcState(), inst->nextInstAddr());
1332 // If incorrect, then signal the ROB that it must be squashed.
1333 squashDueToBranch(inst, tid);
1335 if (inst->readPredTaken()) {
1336 predictedTakenIncorrect++;
1338 predictedNotTakenIncorrect++;
1340 } else if (ldstQueue.violation(tid)) {
1341 assert(inst->isMemRef());
1342 // If there was an ordering violation, then get the
1343 // DynInst that caused the violation. Note that this
1344 // clears the violation signal.
1345 DynInstPtr violator;
1346 violator = ldstQueue.getMemDepViolator(tid);
1348 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1349 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1350 violator->pcState(), violator->seqNum,
1351 inst->pcState(), inst->seqNum, inst->physEffAddr);
1353 fetchRedirect[tid] = true;
1355 // Tell the instruction queue that a violation has occured.
1356 instQueue.violation(inst, violator);
1359 squashDueToMemOrder(inst,tid);
1361 ++memOrderViolationEvents;
1362 } else if (ldstQueue.loadBlocked(tid) &&
1363 !ldstQueue.isLoadBlockedHandled(tid)) {
1364 fetchRedirect[tid] = true;
1366 DPRINTF(IEW, "Load operation couldn't execute because the "
1367 "memory system is blocked. PC: %s [sn:%lli]\n",
1368 inst->pcState(), inst->seqNum);
1370 squashDueToMemBlocked(inst, tid);
1373 // Reset any state associated with redirects that will not
1375 if (ldstQueue.violation(tid)) {
1376 assert(inst->isMemRef());
1378 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1380 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1381 "%s, inst PC: %s. Addr is: %#x.\n",
1382 violator->pcState(), inst->pcState(),
1384 DPRINTF(IEW, "Violation will not be handled because "
1385 "already squashing\n");
1387 ++memOrderViolationEvents;
1389 if (ldstQueue.loadBlocked(tid) &&
1390 !ldstQueue.isLoadBlockedHandled(tid)) {
1391 DPRINTF(IEW, "Load operation couldn't execute because the "
1392 "memory system is blocked. PC: %s [sn:%lli]\n",
1393 inst->pcState(), inst->seqNum);
1394 DPRINTF(IEW, "Blocked load will not be handled because "
1395 "already squashing\n");
1397 ldstQueue.setLoadBlockedHandled(tid);
1403 // Update and record activity if we processed any instructions.
1405 if (exeStatus == Idle) {
1406 exeStatus = Running;
1409 updatedQueues = true;
1411 cpu->activityThisCycle();
1414 // Need to reset this in case a writeback event needs to write into the
1415 // iew queue. That way the writeback event will write into the correct
1416 // spot in the queue.
1421 template <class Impl>
1423 DefaultIEW<Impl>::writebackInsts()
1425 // Loop through the head of the time buffer and wake any
1426 // dependents. These instructions are about to write back. Also
1427 // mark scoreboard that this instruction is finally complete.
1428 // Either have IEW have direct access to scoreboard, or have this
1429 // as part of backwards communication.
1430 for (int inst_num = 0; inst_num < wbWidth &&
1431 toCommit->insts[inst_num]; inst_num++) {
1432 DynInstPtr inst = toCommit->insts[inst_num];
1433 ThreadID tid = inst->threadNumber;
1435 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1436 inst->seqNum, inst->pcState());
1438 iewInstsToCommit[tid]++;
1440 // Some instructions will be sent to commit without having
1441 // executed because they need commit to handle them.
1442 // E.g. Uncached loads have not actually executed when they
1443 // are first sent to commit. Instead commit must tell the LSQ
1444 // when it's ready to execute the uncached load.
1445 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1446 int dependents = instQueue.wakeDependents(inst);
1448 for (int i = 0; i < inst->numDestRegs(); i++) {
1450 DPRINTF(IEW,"Setting Destination Register %i\n",
1451 inst->renamedDestRegIdx(i));
1452 scoreboard->setReg(inst->renamedDestRegIdx(i));
1456 producerInst[tid]++;
1457 consumerInst[tid]+= dependents;
1459 writebackCount[tid]++;
1462 decrWb(inst->seqNum);
1466 template<class Impl>
1468 DefaultIEW<Impl>::tick()
1473 wroteToTimeBuffer = false;
1474 updatedQueues = false;
1478 // Free function units marked as being freed this cycle.
1479 fuPool->processFreeUnits();
1481 list<ThreadID>::iterator threads = activeThreads->begin();
1482 list<ThreadID>::iterator end = activeThreads->end();
1484 // Check stall and squash signals, dispatch any instructions.
1485 while (threads != end) {
1486 ThreadID tid = *threads++;
1488 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1490 checkSignalsAndUpdate(tid);
1494 if (exeStatus != Squashing) {
1499 // Have the instruction queue try to schedule any ready instructions.
1500 // (In actuality, this scheduling is for instructions that will
1501 // be executed next cycle.)
1502 instQueue.scheduleReadyInsts();
1504 // Also should advance its own time buffers if the stage ran.
1505 // Not the best place for it, but this works (hopefully).
1506 issueToExecQueue.advance();
1509 bool broadcast_free_entries = false;
1511 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1513 updateLSQNextCycle = false;
1515 broadcast_free_entries = true;
1518 // Writeback any stores using any leftover bandwidth.
1519 ldstQueue.writebackStores();
1521 // Check the committed load/store signals to see if there's a load
1522 // or store to commit. Also check if it's being told to execute a
1523 // nonspeculative instruction.
1524 // This is pretty inefficient...
1526 threads = activeThreads->begin();
1527 while (threads != end) {
1528 ThreadID tid = (*threads++);
1530 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1532 // Update structures based on instructions committed.
1533 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1534 !fromCommit->commitInfo[tid].squash &&
1535 !fromCommit->commitInfo[tid].robSquashing) {
1537 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1539 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1541 updateLSQNextCycle = true;
1542 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1545 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1547 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1548 if (fromCommit->commitInfo[tid].uncached) {
1549 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1550 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1552 instQueue.scheduleNonSpec(
1553 fromCommit->commitInfo[tid].nonSpecSeqNum);
1557 if (broadcast_free_entries) {
1558 toFetch->iewInfo[tid].iqCount =
1559 instQueue.getCount(tid);
1560 toFetch->iewInfo[tid].ldstqCount =
1561 ldstQueue.getCount(tid);
1563 toRename->iewInfo[tid].usedIQ = true;
1564 toRename->iewInfo[tid].freeIQEntries =
1565 instQueue.numFreeEntries();
1566 toRename->iewInfo[tid].usedLSQ = true;
1567 toRename->iewInfo[tid].freeLSQEntries =
1568 ldstQueue.numFreeEntries(tid);
1570 wroteToTimeBuffer = true;
1573 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1574 tid, toRename->iewInfo[tid].dispatched);
1577 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1578 "LSQ has %i free entries.\n",
1579 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1580 ldstQueue.numFreeEntries());
1584 if (wroteToTimeBuffer) {
1585 DPRINTF(Activity, "Activity this cycle.\n");
1586 cpu->activityThisCycle();
1590 template <class Impl>
1592 DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1594 ThreadID tid = inst->threadNumber;
1597 // Pick off the software prefetches
1600 if (inst->isDataPrefetch())
1601 iewExecutedSwp[tid]++;
1603 iewIewExecutedcutedInsts++;
1609 // Control operations
1611 if (inst->isControl())
1612 iewExecutedBranches[tid]++;
1615 // Memory operations
1617 if (inst->isMemRef()) {
1618 iewExecutedRefs[tid]++;
1620 if (inst->isLoad()) {
1621 iewExecLoadInsts[tid]++;
1626 template <class Impl>
1628 DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1630 ThreadID tid = inst->threadNumber;
1632 if (!fetchRedirect[tid] ||
1633 !toCommit->squash[tid] ||
1634 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1636 if (inst->mispredicted()) {
1637 fetchRedirect[tid] = true;
1639 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1640 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1641 inst->predInstAddr(), inst->predNextInstAddr());
1642 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1643 " NPC: %#x.\n", inst->nextInstAddr(),
1644 inst->nextInstAddr());
1645 // If incorrect, then signal the ROB that it must be squashed.
1646 squashDueToBranch(inst, tid);
1648 if (inst->readPredTaken()) {
1649 predictedTakenIncorrect++;
1651 predictedNotTakenIncorrect++;