src/cpu/o3/iew_impl.hh

   1 /*
   2  * Copyright (c) 2010-2013, 2018 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
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  15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
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  41
  42 #ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
  43 #define __CPU_O3_IEW_IMPL_IMPL_HH__
  44
  45 // @todo: Fix the instantaneous communication among all the stages within
  46 // iew.  There's a clear delay between issue and execute, yet backwards
  47 // communication happens simultaneously.
  48
  49 #include <queue>
  50
  51 #include "arch/utility.hh"
  52 #include "config/the_isa.hh"
  53 #include "cpu/checker/cpu.hh"
  54 #include "cpu/o3/fu_pool.hh"
  55 #include "cpu/o3/iew.hh"
  56 #include "cpu/timebuf.hh"
  57 #include "debug/Activity.hh"
  58 #include "debug/Drain.hh"
  59 #include "debug/IEW.hh"
  60 #include "debug/O3PipeView.hh"
  61 #include "params/DerivO3CPU.hh"
  62
  63 using namespace std;
  64
  65 template<class Impl>
  66 DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
  67     : issueToExecQueue(params->backComSize, params->forwardComSize),
  68       cpu(_cpu),
  69       instQueue(_cpu, this, params),
  70       ldstQueue(_cpu, this, params),
  71       fuPool(params->fuPool),
  72       commitToIEWDelay(params->commitToIEWDelay),
  73       renameToIEWDelay(params->renameToIEWDelay),
  74       issueToExecuteDelay(params->issueToExecuteDelay),
  75       dispatchWidth(params->dispatchWidth),
  76       issueWidth(params->issueWidth),
  77       wbNumInst(0),
  78       wbCycle(0),
  79       wbWidth(params->wbWidth),
  80       numThreads(params->numThreads)
  81 {
  82     if (dispatchWidth > Impl::MaxWidth)
  83         fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
  84              "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
  85              dispatchWidth, static_cast<int>(Impl::MaxWidth));
  86     if (issueWidth > Impl::MaxWidth)
  87         fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
  88              "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
  89              issueWidth, static_cast<int>(Impl::MaxWidth));
  90     if (wbWidth > Impl::MaxWidth)
  91         fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
  92              "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
  93              wbWidth, static_cast<int>(Impl::MaxWidth));
  94
  95     _status = Active;
  96     exeStatus = Running;
  97     wbStatus = Idle;
  98
  99     // Setup wire to read instructions coming from issue.
 100     fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
 101
 102     // Instruction queue needs the queue between issue and execute.
 103     instQueue.setIssueToExecuteQueue(&issueToExecQueue);
 104
 105     for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
 106         dispatchStatus[tid] = Running;
 107         fetchRedirect[tid] = false;
 108     }
 109
 110     updateLSQNextCycle = false;
 111
 112     skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
 113 }
 114
 115 template <class Impl>
 116 std::string
 117 DefaultIEW<Impl>::name() const
 118 {
 119     return cpu->name() + ".iew";
 120 }
 121
 122 template <class Impl>
 123 void
 124 DefaultIEW<Impl>::regProbePoints()
 125 {
 126     ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
 127     ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
 128     /**
 129      * Probe point with dynamic instruction as the argument used to probe when
 130      * an instruction starts to execute.
 131      */
 132     ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
 133                                               "Execute");
 134     /**
 135      * Probe point with dynamic instruction as the argument used to probe when
 136      * an instruction execution completes and it is marked ready to commit.
 137      */
 138     ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
 139                                                "ToCommit");
 140 }
 141
 142 template <class Impl>
 143 void
 144 DefaultIEW<Impl>::regStats()
 145 {
 146     using namespace Stats;
 147
 148     instQueue.regStats();
 149     ldstQueue.regStats();
 150
 151     iewIdleCycles
 152         .name(name() + ".iewIdleCycles")
 153         .desc("Number of cycles IEW is idle");
 154
 155     iewSquashCycles
 156         .name(name() + ".iewSquashCycles")
 157         .desc("Number of cycles IEW is squashing");
 158
 159     iewBlockCycles
 160         .name(name() + ".iewBlockCycles")
 161         .desc("Number of cycles IEW is blocking");
 162
 163     iewUnblockCycles
 164         .name(name() + ".iewUnblockCycles")
 165         .desc("Number of cycles IEW is unblocking");
 166
 167     iewDispatchedInsts
 168         .name(name() + ".iewDispatchedInsts")
 169         .desc("Number of instructions dispatched to IQ");
 170
 171     iewDispSquashedInsts
 172         .name(name() + ".iewDispSquashedInsts")
 173         .desc("Number of squashed instructions skipped by dispatch");
 174
 175     iewDispLoadInsts
 176         .name(name() + ".iewDispLoadInsts")
 177         .desc("Number of dispatched load instructions");
 178
 179     iewDispStoreInsts
 180         .name(name() + ".iewDispStoreInsts")
 181         .desc("Number of dispatched store instructions");
 182
 183     iewDispNonSpecInsts
 184         .name(name() + ".iewDispNonSpecInsts")
 185         .desc("Number of dispatched non-speculative instructions");
 186
 187     iewIQFullEvents
 188         .name(name() + ".iewIQFullEvents")
 189         .desc("Number of times the IQ has become full, causing a stall");
 190
 191     iewLSQFullEvents
 192         .name(name() + ".iewLSQFullEvents")
 193         .desc("Number of times the LSQ has become full, causing a stall");
 194
 195     memOrderViolationEvents
 196         .name(name() + ".memOrderViolationEvents")
 197         .desc("Number of memory order violations");
 198
 199     predictedTakenIncorrect
 200         .name(name() + ".predictedTakenIncorrect")
 201         .desc("Number of branches that were predicted taken incorrectly");
 202
 203     predictedNotTakenIncorrect
 204         .name(name() + ".predictedNotTakenIncorrect")
 205         .desc("Number of branches that were predicted not taken incorrectly");
 206
 207     branchMispredicts
 208         .name(name() + ".branchMispredicts")
 209         .desc("Number of branch mispredicts detected at execute");
 210
 211     branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
 212
 213     iewExecutedInsts
 214         .name(name() + ".iewExecutedInsts")
 215         .desc("Number of executed instructions");
 216
 217     iewExecLoadInsts
 218         .init(cpu->numThreads)
 219         .name(name() + ".iewExecLoadInsts")
 220         .desc("Number of load instructions executed")
 221         .flags(total);
 222
 223     iewExecSquashedInsts
 224         .name(name() + ".iewExecSquashedInsts")
 225         .desc("Number of squashed instructions skipped in execute");
 226
 227     iewExecutedSwp
 228         .init(cpu->numThreads)
 229         .name(name() + ".exec_swp")
 230         .desc("number of swp insts executed")
 231         .flags(total);
 232
 233     iewExecutedNop
 234         .init(cpu->numThreads)
 235         .name(name() + ".exec_nop")
 236         .desc("number of nop insts executed")
 237         .flags(total);
 238
 239     iewExecutedRefs
 240         .init(cpu->numThreads)
 241         .name(name() + ".exec_refs")
 242         .desc("number of memory reference insts executed")
 243         .flags(total);
 244
 245     iewExecutedBranches
 246         .init(cpu->numThreads)
 247         .name(name() + ".exec_branches")
 248         .desc("Number of branches executed")
 249         .flags(total);
 250
 251     iewExecStoreInsts
 252         .name(name() + ".exec_stores")
 253         .desc("Number of stores executed")
 254         .flags(total);
 255     iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
 256
 257     iewExecRate
 258         .name(name() + ".exec_rate")
 259         .desc("Inst execution rate")
 260         .flags(total);
 261
 262     iewExecRate = iewExecutedInsts / cpu->numCycles;
 263
 264     iewInstsToCommit
 265         .init(cpu->numThreads)
 266         .name(name() + ".wb_sent")
 267         .desc("cumulative count of insts sent to commit")
 268         .flags(total);
 269
 270     writebackCount
 271         .init(cpu->numThreads)
 272         .name(name() + ".wb_count")
 273         .desc("cumulative count of insts written-back")
 274         .flags(total);
 275
 276     producerInst
 277         .init(cpu->numThreads)
 278         .name(name() + ".wb_producers")
 279         .desc("num instructions producing a value")
 280         .flags(total);
 281
 282     consumerInst
 283         .init(cpu->numThreads)
 284         .name(name() + ".wb_consumers")
 285         .desc("num instructions consuming a value")
 286         .flags(total);
 287
 288     wbFanout
 289         .name(name() + ".wb_fanout")
 290         .desc("average fanout of values written-back")
 291         .flags(total);
 292
 293     wbFanout = producerInst / consumerInst;
 294
 295     wbRate
 296         .name(name() + ".wb_rate")
 297         .desc("insts written-back per cycle")
 298         .flags(total);
 299     wbRate = writebackCount / cpu->numCycles;
 300 }
 301
 302 template<class Impl>
 303 void
 304 DefaultIEW<Impl>::startupStage()
 305 {
 306     for (ThreadID tid = 0; tid < numThreads; tid++) {
 307         toRename->iewInfo[tid].usedIQ = true;
 308         toRename->iewInfo[tid].freeIQEntries =
 309             instQueue.numFreeEntries(tid);
 310
 311         toRename->iewInfo[tid].usedLSQ = true;
 312         toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
 313         toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
 314     }
 315
 316     // Initialize the checker's dcache port here
 317     if (cpu->checker) {
 318         cpu->checker->setDcachePort(&ldstQueue.getDataPort());
 319     }
 320
 321     cpu->activateStage(O3CPU::IEWIdx);
 322 }
 323
 324 template<class Impl>
 325 void
 326 DefaultIEW<Impl>::clearStates(ThreadID tid)
 327 {
 328     toRename->iewInfo[tid].usedIQ = true;
 329     toRename->iewInfo[tid].freeIQEntries =
 330         instQueue.numFreeEntries(tid);
 331
 332     toRename->iewInfo[tid].usedLSQ = true;
 333     toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
 334     toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
 335 }
 336
 337 template<class Impl>
 338 void
 339 DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 340 {
 341     timeBuffer = tb_ptr;
 342
 343     // Setup wire to read information from time buffer, from commit.
 344     fromCommit = timeBuffer->getWire(-commitToIEWDelay);
 345
 346     // Setup wire to write information back to previous stages.
 347     toRename = timeBuffer->getWire(0);
 348
 349     toFetch = timeBuffer->getWire(0);
 350
 351     // Instruction queue also needs main time buffer.
 352     instQueue.setTimeBuffer(tb_ptr);
 353 }
 354
 355 template<class Impl>
 356 void
 357 DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 358 {
 359     renameQueue = rq_ptr;
 360
 361     // Setup wire to read information from rename queue.
 362     fromRename = renameQueue->getWire(-renameToIEWDelay);
 363 }
 364
 365 template<class Impl>
 366 void
 367 DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 368 {
 369     iewQueue = iq_ptr;
 370
 371     // Setup wire to write instructions to commit.
 372     toCommit = iewQueue->getWire(0);
 373 }
 374
 375 template<class Impl>
 376 void
 377 DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 378 {
 379     activeThreads = at_ptr;
 380
 381     ldstQueue.setActiveThreads(at_ptr);
 382     instQueue.setActiveThreads(at_ptr);
 383 }
 384
 385 template<class Impl>
 386 void
 387 DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
 388 {
 389     scoreboard = sb_ptr;
 390 }
 391
 392 template <class Impl>
 393 bool
 394 DefaultIEW<Impl>::isDrained() const
 395 {
 396     bool drained = ldstQueue.isDrained() && instQueue.isDrained();
 397
 398     for (ThreadID tid = 0; tid < numThreads; tid++) {
 399         if (!insts[tid].empty()) {
 400             DPRINTF(Drain, "%i: Insts not empty.\n", tid);
 401             drained = false;
 402         }
 403         if (!skidBuffer[tid].empty()) {
 404             DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
 405             drained = false;
 406         }
 407         drained = drained && dispatchStatus[tid] == Running;
 408     }
 409
 410     // Also check the FU pool as instructions are "stored" in FU
 411     // completion events until they are done and not accounted for
 412     // above
 413     if (drained && !fuPool->isDrained()) {
 414         DPRINTF(Drain, "FU pool still busy.\n");
 415         drained = false;
 416     }
 417
 418     return drained;
 419 }
 420
 421 template <class Impl>
 422 void
 423 DefaultIEW<Impl>::drainSanityCheck() const
 424 {
 425     assert(isDrained());
 426
 427     instQueue.drainSanityCheck();
 428     ldstQueue.drainSanityCheck();
 429 }
 430
 431 template <class Impl>
 432 void
 433 DefaultIEW<Impl>::takeOverFrom()
 434 {
 435     // Reset all state.
 436     _status = Active;
 437     exeStatus = Running;
 438     wbStatus = Idle;
 439
 440     instQueue.takeOverFrom();
 441     ldstQueue.takeOverFrom();
 442     fuPool->takeOverFrom();
 443
 444     startupStage();
 445     cpu->activityThisCycle();
 446
 447     for (ThreadID tid = 0; tid < numThreads; tid++) {
 448         dispatchStatus[tid] = Running;
 449         fetchRedirect[tid] = false;
 450     }
 451
 452     updateLSQNextCycle = false;
 453
 454     for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
 455         issueToExecQueue.advance();
 456     }
 457 }
 458
 459 template<class Impl>
 460 void
 461 DefaultIEW<Impl>::squash(ThreadID tid)
 462 {
 463     DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid);
 464
 465     // Tell the IQ to start squashing.
 466     instQueue.squash(tid);
 467
 468     // Tell the LDSTQ to start squashing.
 469     ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
 470     updatedQueues = true;
 471
 472     // Clear the skid buffer in case it has any data in it.
 473     DPRINTF(IEW,
 474             "Removing skidbuffer instructions until "
 475             "[sn:%llu] [tid:%i]\n",
 476             fromCommit->commitInfo[tid].doneSeqNum, tid);
 477
 478     while (!skidBuffer[tid].empty()) {
 479         if (skidBuffer[tid].front()->isLoad()) {
 480             toRename->iewInfo[tid].dispatchedToLQ++;
 481         }
 482         if (skidBuffer[tid].front()->isStore() ||
 483             skidBuffer[tid].front()->isAtomic()) {
 484             toRename->iewInfo[tid].dispatchedToSQ++;
 485         }
 486
 487         toRename->iewInfo[tid].dispatched++;
 488
 489         skidBuffer[tid].pop();
 490     }
 491
 492     emptyRenameInsts(tid);
 493 }
 494
 495 template<class Impl>
 496 void
 497 DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
 498 {
 499     DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction,"
 500             " PC: %s "
 501             "\n", tid, inst->seqNum, inst->pcState() );
 502
 503     if (!toCommit->squash[tid] ||
 504             inst->seqNum < toCommit->squashedSeqNum[tid]) {
 505         toCommit->squash[tid] = true;
 506         toCommit->squashedSeqNum[tid] = inst->seqNum;
 507         toCommit->branchTaken[tid] = inst->pcState().branching();
 508
 509         TheISA::PCState pc = inst->pcState();
 510         TheISA::advancePC(pc, inst->staticInst);
 511
 512         toCommit->pc[tid] = pc;
 513         toCommit->mispredictInst[tid] = inst;
 514         toCommit->includeSquashInst[tid] = false;
 515
 516         wroteToTimeBuffer = true;
 517     }
 518
 519 }
 520
 521 template<class Impl>
 522 void
 523 DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
 524 {
 525     DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger "
 526             "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
 527     // Need to include inst->seqNum in the following comparison to cover the
 528     // corner case when a branch misprediction and a memory violation for the
 529     // same instruction (e.g. load PC) are detected in the same cycle.  In this
 530     // case the memory violator should take precedence over the branch
 531     // misprediction because it requires the violator itself to be included in
 532     // the squash.
 533     if (!toCommit->squash[tid] ||
 534             inst->seqNum <= toCommit->squashedSeqNum[tid]) {
 535         toCommit->squash[tid] = true;
 536
 537         toCommit->squashedSeqNum[tid] = inst->seqNum;
 538         toCommit->pc[tid] = inst->pcState();
 539         toCommit->mispredictInst[tid] = NULL;
 540
 541         // Must include the memory violator in the squash.
 542         toCommit->includeSquashInst[tid] = true;
 543
 544         wroteToTimeBuffer = true;
 545     }
 546 }
 547
 548 template<class Impl>
 549 void
 550 DefaultIEW<Impl>::block(ThreadID tid)
 551 {
 552     DPRINTF(IEW, "[tid:%i] Blocking.\n", tid);
 553
 554     if (dispatchStatus[tid] != Blocked &&
 555         dispatchStatus[tid] != Unblocking) {
 556         toRename->iewBlock[tid] = true;
 557         wroteToTimeBuffer = true;
 558     }
 559
 560     // Add the current inputs to the skid buffer so they can be
 561     // reprocessed when this stage unblocks.
 562     skidInsert(tid);
 563
 564     dispatchStatus[tid] = Blocked;
 565 }
 566
 567 template<class Impl>
 568 void
 569 DefaultIEW<Impl>::unblock(ThreadID tid)
 570 {
 571     DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid "
 572             "buffer %u.\n",tid, tid);
 573
 574     // If the skid bufffer is empty, signal back to previous stages to unblock.
 575     // Also switch status to running.
 576     if (skidBuffer[tid].empty()) {
 577         toRename->iewUnblock[tid] = true;
 578         wroteToTimeBuffer = true;
 579         DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid);
 580         dispatchStatus[tid] = Running;
 581     }
 582 }
 583
 584 template<class Impl>
 585 void
 586 DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst)
 587 {
 588     instQueue.wakeDependents(inst);
 589 }
 590
 591 template<class Impl>
 592 void
 593 DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst)
 594 {
 595     instQueue.rescheduleMemInst(inst);
 596 }
 597
 598 template<class Impl>
 599 void
 600 DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst)
 601 {
 602     instQueue.replayMemInst(inst);
 603 }
 604
 605 template<class Impl>
 606 void
 607 DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst)
 608 {
 609     instQueue.blockMemInst(inst);
 610 }
 611
 612 template<class Impl>
 613 void
 614 DefaultIEW<Impl>::cacheUnblocked()
 615 {
 616     instQueue.cacheUnblocked();
 617 }
 618
 619 template<class Impl>
 620 void
 621 DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst)
 622 {
 623     // This function should not be called after writebackInsts in a
 624     // single cycle.  That will cause problems with an instruction
 625     // being added to the queue to commit without being processed by
 626     // writebackInsts prior to being sent to commit.
 627
 628     // First check the time slot that this instruction will write
 629     // to.  If there are free write ports at the time, then go ahead
 630     // and write the instruction to that time.  If there are not,
 631     // keep looking back to see where's the first time there's a
 632     // free slot.
 633     while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
 634         ++wbNumInst;
 635         if (wbNumInst == wbWidth) {
 636             ++wbCycle;
 637             wbNumInst = 0;
 638         }
 639     }
 640
 641     DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
 642             wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
 643     // Add finished instruction to queue to commit.
 644     (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
 645     (*iewQueue)[wbCycle].size++;
 646 }
 647
 648 template <class Impl>
 649 unsigned
 650 DefaultIEW<Impl>::validInstsFromRename()
 651 {
 652     unsigned inst_count = 0;
 653
 654     for (int i=0; i<fromRename->size; i++) {
 655         if (!fromRename->insts[i]->isSquashed())
 656             inst_count++;
 657     }
 658
 659     return inst_count;
 660 }
 661
 662 template<class Impl>
 663 void
 664 DefaultIEW<Impl>::skidInsert(ThreadID tid)
 665 {
 666     DynInstPtr inst = NULL;
 667
 668     while (!insts[tid].empty()) {
 669         inst = insts[tid].front();
 670
 671         insts[tid].pop();
 672
 673         DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into "
 674                 "dispatch skidBuffer %i\n",tid, inst->seqNum,
 675                 inst->pcState(),tid);
 676
 677         skidBuffer[tid].push(inst);
 678     }
 679
 680     assert(skidBuffer[tid].size() <= skidBufferMax &&
 681            "Skidbuffer Exceeded Max Size");
 682 }
 683
 684 template<class Impl>
 685 int
 686 DefaultIEW<Impl>::skidCount()
 687 {
 688     int max=0;
 689
 690     list<ThreadID>::iterator threads = activeThreads->begin();
 691     list<ThreadID>::iterator end = activeThreads->end();
 692
 693     while (threads != end) {
 694         ThreadID tid = *threads++;
 695         unsigned thread_count = skidBuffer[tid].size();
 696         if (max < thread_count)
 697             max = thread_count;
 698     }
 699
 700     return max;
 701 }
 702
 703 template<class Impl>
 704 bool
 705 DefaultIEW<Impl>::skidsEmpty()
 706 {
 707     list<ThreadID>::iterator threads = activeThreads->begin();
 708     list<ThreadID>::iterator end = activeThreads->end();
 709
 710     while (threads != end) {
 711         ThreadID tid = *threads++;
 712
 713         if (!skidBuffer[tid].empty())
 714             return false;
 715     }
 716
 717     return true;
 718 }
 719
 720 template <class Impl>
 721 void
 722 DefaultIEW<Impl>::updateStatus()
 723 {
 724     bool any_unblocking = false;
 725
 726     list<ThreadID>::iterator threads = activeThreads->begin();
 727     list<ThreadID>::iterator end = activeThreads->end();
 728
 729     while (threads != end) {
 730         ThreadID tid = *threads++;
 731
 732         if (dispatchStatus[tid] == Unblocking) {
 733             any_unblocking = true;
 734             break;
 735         }
 736     }
 737
 738     // If there are no ready instructions waiting to be scheduled by the IQ,
 739     // and there's no stores waiting to write back, and dispatch is not
 740     // unblocking, then there is no internal activity for the IEW stage.
 741     instQueue.intInstQueueReads++;
 742     if (_status == Active && !instQueue.hasReadyInsts() &&
 743         !ldstQueue.willWB() && !any_unblocking) {
 744         DPRINTF(IEW, "IEW switching to idle\n");
 745
 746         deactivateStage();
 747
 748         _status = Inactive;
 749     } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
 750                                        ldstQueue.willWB() ||
 751                                        any_unblocking)) {
 752         // Otherwise there is internal activity.  Set to active.
 753         DPRINTF(IEW, "IEW switching to active\n");
 754
 755         activateStage();
 756
 757         _status = Active;
 758     }
 759 }
 760
 761 template <class Impl>
 762 bool
 763 DefaultIEW<Impl>::checkStall(ThreadID tid)
 764 {
 765     bool ret_val(false);
 766
 767     if (fromCommit->commitInfo[tid].robSquashing) {
 768         DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid);
 769         ret_val = true;
 770     } else if (instQueue.isFull(tid)) {
 771         DPRINTF(IEW,"[tid:%i] Stall: IQ  is full.\n",tid);
 772         ret_val = true;
 773     }
 774
 775     return ret_val;
 776 }
 777
 778 template <class Impl>
 779 void
 780 DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
 781 {
 782     // Check if there's a squash signal, squash if there is
 783     // Check stall signals, block if there is.
 784     // If status was Blocked
 785     //     if so then go to unblocking
 786     // If status was Squashing
 787     //     check if squashing is not high.  Switch to running this cycle.
 788
 789     if (fromCommit->commitInfo[tid].squash) {
 790         squash(tid);
 791
 792         if (dispatchStatus[tid] == Blocked ||
 793             dispatchStatus[tid] == Unblocking) {
 794             toRename->iewUnblock[tid] = true;
 795             wroteToTimeBuffer = true;
 796         }
 797
 798         dispatchStatus[tid] = Squashing;
 799         fetchRedirect[tid] = false;
 800         return;
 801     }
 802
 803     if (fromCommit->commitInfo[tid].robSquashing) {
 804         DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid);
 805
 806         dispatchStatus[tid] = Squashing;
 807         emptyRenameInsts(tid);
 808         wroteToTimeBuffer = true;
 809     }
 810
 811     if (checkStall(tid)) {
 812         block(tid);
 813         dispatchStatus[tid] = Blocked;
 814         return;
 815     }
 816
 817     if (dispatchStatus[tid] == Blocked) {
 818         // Status from previous cycle was blocked, but there are no more stall
 819         // conditions.  Switch over to unblocking.
 820         DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n",
 821                 tid);
 822
 823         dispatchStatus[tid] = Unblocking;
 824
 825         unblock(tid);
 826
 827         return;
 828     }
 829
 830     if (dispatchStatus[tid] == Squashing) {
 831         // Switch status to running if rename isn't being told to block or
 832         // squash this cycle.
 833         DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n",
 834                 tid);
 835
 836         dispatchStatus[tid] = Running;
 837
 838         return;
 839     }
 840 }
 841
 842 template <class Impl>
 843 void
 844 DefaultIEW<Impl>::sortInsts()
 845 {
 846     int insts_from_rename = fromRename->size;
 847 #ifdef DEBUG
 848     for (ThreadID tid = 0; tid < numThreads; tid++)
 849         assert(insts[tid].empty());
 850 #endif
 851     for (int i = 0; i < insts_from_rename; ++i) {
 852         insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
 853     }
 854 }
 855
 856 template <class Impl>
 857 void
 858 DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
 859 {
 860     DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid);
 861
 862     while (!insts[tid].empty()) {
 863
 864         if (insts[tid].front()->isLoad()) {
 865             toRename->iewInfo[tid].dispatchedToLQ++;
 866         }
 867         if (insts[tid].front()->isStore() ||
 868             insts[tid].front()->isAtomic()) {
 869             toRename->iewInfo[tid].dispatchedToSQ++;
 870         }
 871
 872         toRename->iewInfo[tid].dispatched++;
 873
 874         insts[tid].pop();
 875     }
 876 }
 877
 878 template <class Impl>
 879 void
 880 DefaultIEW<Impl>::wakeCPU()
 881 {
 882     cpu->wakeCPU();
 883 }
 884
 885 template <class Impl>
 886 void
 887 DefaultIEW<Impl>::activityThisCycle()
 888 {
 889     DPRINTF(Activity, "Activity this cycle.\n");
 890     cpu->activityThisCycle();
 891 }
 892
 893 template <class Impl>
 894 inline void
 895 DefaultIEW<Impl>::activateStage()
 896 {
 897     DPRINTF(Activity, "Activating stage.\n");
 898     cpu->activateStage(O3CPU::IEWIdx);
 899 }
 900
 901 template <class Impl>
 902 inline void
 903 DefaultIEW<Impl>::deactivateStage()
 904 {
 905     DPRINTF(Activity, "Deactivating stage.\n");
 906     cpu->deactivateStage(O3CPU::IEWIdx);
 907 }
 908
 909 template<class Impl>
 910 void
 911 DefaultIEW<Impl>::dispatch(ThreadID tid)
 912 {
 913     // If status is Running or idle,
 914     //     call dispatchInsts()
 915     // If status is Unblocking,
 916     //     buffer any instructions coming from rename
 917     //     continue trying to empty skid buffer
 918     //     check if stall conditions have passed
 919
 920     if (dispatchStatus[tid] == Blocked) {
 921         ++iewBlockCycles;
 922
 923     } else if (dispatchStatus[tid] == Squashing) {
 924         ++iewSquashCycles;
 925     }
 926
 927     // Dispatch should try to dispatch as many instructions as its bandwidth
 928     // will allow, as long as it is not currently blocked.
 929     if (dispatchStatus[tid] == Running ||
 930         dispatchStatus[tid] == Idle) {
 931         DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
 932                 "dispatch.\n", tid);
 933
 934         dispatchInsts(tid);
 935     } else if (dispatchStatus[tid] == Unblocking) {
 936         // Make sure that the skid buffer has something in it if the
 937         // status is unblocking.
 938         assert(!skidsEmpty());
 939
 940         // If the status was unblocking, then instructions from the skid
 941         // buffer were used.  Remove those instructions and handle
 942         // the rest of unblocking.
 943         dispatchInsts(tid);
 944
 945         ++iewUnblockCycles;
 946
 947         if (validInstsFromRename()) {
 948             // Add the current inputs to the skid buffer so they can be
 949             // reprocessed when this stage unblocks.
 950             skidInsert(tid);
 951         }
 952
 953         unblock(tid);
 954     }
 955 }
 956
 957 template <class Impl>
 958 void
 959 DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
 960 {
 961     // Obtain instructions from skid buffer if unblocking, or queue from rename
 962     // otherwise.
 963     std::queue<DynInstPtr> &insts_to_dispatch =
 964         dispatchStatus[tid] == Unblocking ?
 965         skidBuffer[tid] : insts[tid];
 966
 967     int insts_to_add = insts_to_dispatch.size();
 968
 969     DynInstPtr inst;
 970     bool add_to_iq = false;
 971     int dis_num_inst = 0;
 972
 973     // Loop through the instructions, putting them in the instruction
 974     // queue.
 975     for ( ; dis_num_inst < insts_to_add &&
 976               dis_num_inst < dispatchWidth;
 977           ++dis_num_inst)
 978     {
 979         inst = insts_to_dispatch.front();
 980
 981         if (dispatchStatus[tid] == Unblocking) {
 982             DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid "
 983                     "buffer\n", tid);
 984         }
 985
 986         // Make sure there's a valid instruction there.
 987         assert(inst);
 988
 989         DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to "
 990                 "IQ.\n",
 991                 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
 992
 993         // Be sure to mark these instructions as ready so that the
 994         // commit stage can go ahead and execute them, and mark
 995         // them as issued so the IQ doesn't reprocess them.
 996
 997         // Check for squashed instructions.
 998         if (inst->isSquashed()) {
 999             DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, "
1000                     "not adding to IQ.\n", tid);
1001
1002             ++iewDispSquashedInsts;
1003
1004             insts_to_dispatch.pop();
1005
1006             //Tell Rename That An Instruction has been processed
1007             if (inst->isLoad()) {
1008                 toRename->iewInfo[tid].dispatchedToLQ++;
1009             }
1010             if (inst->isStore() || inst->isAtomic()) {
1011                 toRename->iewInfo[tid].dispatchedToSQ++;
1012             }
1013
1014             toRename->iewInfo[tid].dispatched++;
1015
1016             continue;
1017         }
1018
1019         // Check for full conditions.
1020         if (instQueue.isFull(tid)) {
1021             DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid);
1022
1023             // Call function to start blocking.
1024             block(tid);
1025
1026             // Set unblock to false. Special case where we are using
1027             // skidbuffer (unblocking) instructions but then we still
1028             // get full in the IQ.
1029             toRename->iewUnblock[tid] = false;
1030
1031             ++iewIQFullEvents;
1032             break;
1033         }
1034
1035         // Check LSQ if inst is LD/ST
1036         if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
1037             (inst->isLoad() && ldstQueue.lqFull(tid)) ||
1038             (inst->isStore() && ldstQueue.sqFull(tid))) {
1039             DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid,
1040                     inst->isLoad() ? "LQ" : "SQ");
1041
1042             // Call function to start blocking.
1043             block(tid);
1044
1045             // Set unblock to false. Special case where we are using
1046             // skidbuffer (unblocking) instructions but then we still
1047             // get full in the IQ.
1048             toRename->iewUnblock[tid] = false;
1049
1050             ++iewLSQFullEvents;
1051             break;
1052         }
1053
1054         // Otherwise issue the instruction just fine.
1055         if (inst->isAtomic()) {
1056             DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1057                     "encountered, adding to LSQ.\n", tid);
1058
1059             ldstQueue.insertStore(inst);
1060
1061             ++iewDispStoreInsts;
1062
1063             // AMOs need to be set as "canCommit()"
1064             // so that commit can process them when they reach the
1065             // head of commit.
1066             inst->setCanCommit();
1067             instQueue.insertNonSpec(inst);
1068             add_to_iq = false;
1069
1070             ++iewDispNonSpecInsts;
1071
1072             toRename->iewInfo[tid].dispatchedToSQ++;
1073         } else if (inst->isLoad()) {
1074             DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1075                     "encountered, adding to LSQ.\n", tid);
1076
1077             // Reserve a spot in the load store queue for this
1078             // memory access.
1079             ldstQueue.insertLoad(inst);
1080
1081             ++iewDispLoadInsts;
1082
1083             add_to_iq = true;
1084
1085             toRename->iewInfo[tid].dispatchedToLQ++;
1086         } else if (inst->isStore()) {
1087             DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1088                     "encountered, adding to LSQ.\n", tid);
1089
1090             ldstQueue.insertStore(inst);
1091
1092             ++iewDispStoreInsts;
1093
1094             if (inst->isStoreConditional()) {
1095                 // Store conditionals need to be set as "canCommit()"
1096                 // so that commit can process them when they reach the
1097                 // head of commit.
1098                 // @todo: This is somewhat specific to Alpha.
1099                 inst->setCanCommit();
1100                 instQueue.insertNonSpec(inst);
1101                 add_to_iq = false;
1102
1103                 ++iewDispNonSpecInsts;
1104             } else {
1105                 add_to_iq = true;
1106             }
1107
1108             toRename->iewInfo[tid].dispatchedToSQ++;
1109         } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1110             // Same as non-speculative stores.
1111             inst->setCanCommit();
1112             instQueue.insertBarrier(inst);
1113             add_to_iq = false;
1114         } else if (inst->isNop()) {
1115             DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, "
1116                     "skipping.\n", tid);
1117
1118             inst->setIssued();
1119             inst->setExecuted();
1120             inst->setCanCommit();
1121
1122             instQueue.recordProducer(inst);
1123
1124             iewExecutedNop[tid]++;
1125
1126             add_to_iq = false;
1127         } else {
1128             assert(!inst->isExecuted());
1129             add_to_iq = true;
1130         }
1131
1132         if (add_to_iq && inst->isNonSpeculative()) {
1133             DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction "
1134                     "encountered, skipping.\n", tid);
1135
1136             // Same as non-speculative stores.
1137             inst->setCanCommit();
1138
1139             // Specifically insert it as nonspeculative.
1140             instQueue.insertNonSpec(inst);
1141
1142             ++iewDispNonSpecInsts;
1143
1144             add_to_iq = false;
1145         }
1146
1147         // If the instruction queue is not full, then add the
1148         // instruction.
1149         if (add_to_iq) {
1150             instQueue.insert(inst);
1151         }
1152
1153         insts_to_dispatch.pop();
1154
1155         toRename->iewInfo[tid].dispatched++;
1156
1157         ++iewDispatchedInsts;
1158
1159 #if TRACING_ON
1160         inst->dispatchTick = curTick() - inst->fetchTick;
1161 #endif
1162         ppDispatch->notify(inst);
1163     }
1164
1165     if (!insts_to_dispatch.empty()) {
1166         DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid);
1167         block(tid);
1168         toRename->iewUnblock[tid] = false;
1169     }
1170
1171     if (dispatchStatus[tid] == Idle && dis_num_inst) {
1172         dispatchStatus[tid] = Running;
1173
1174         updatedQueues = true;
1175     }
1176
1177     dis_num_inst = 0;
1178 }
1179
1180 template <class Impl>
1181 void
1182 DefaultIEW<Impl>::printAvailableInsts()
1183 {
1184     int inst = 0;
1185
1186     std::cout << "Available Instructions: ";
1187
1188     while (fromIssue->insts[inst]) {
1189
1190         if (inst%3==0) std::cout << "\n\t";
1191
1192         std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1193              << " TN: " << fromIssue->insts[inst]->threadNumber
1194              << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1195
1196         inst++;
1197
1198     }
1199
1200     std::cout << "\n";
1201 }
1202
1203 template <class Impl>
1204 void
1205 DefaultIEW<Impl>::executeInsts()
1206 {
1207     wbNumInst = 0;
1208     wbCycle = 0;
1209
1210     list<ThreadID>::iterator threads = activeThreads->begin();
1211     list<ThreadID>::iterator end = activeThreads->end();
1212
1213     while (threads != end) {
1214         ThreadID tid = *threads++;
1215         fetchRedirect[tid] = false;
1216     }
1217
1218     // Uncomment this if you want to see all available instructions.
1219     // @todo This doesn't actually work anymore, we should fix it.
1220 //    printAvailableInsts();
1221
1222     // Execute/writeback any instructions that are available.
1223     int insts_to_execute = fromIssue->size;
1224     int inst_num = 0;
1225     for (; inst_num < insts_to_execute;
1226           ++inst_num) {
1227
1228         DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1229
1230         DynInstPtr inst = instQueue.getInstToExecute();
1231
1232         DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n",
1233                 inst->pcState(), inst->threadNumber,inst->seqNum);
1234
1235         // Notify potential listeners that this instruction has started
1236         // executing
1237         ppExecute->notify(inst);
1238
1239         // Check if the instruction is squashed; if so then skip it
1240         if (inst->isSquashed()) {
1241             DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1242                          " [sn:%llu]\n", inst->pcState(), inst->threadNumber,
1243                          inst->seqNum);
1244
1245             // Consider this instruction executed so that commit can go
1246             // ahead and retire the instruction.
1247             inst->setExecuted();
1248
1249             // Not sure if I should set this here or just let commit try to
1250             // commit any squashed instructions.  I like the latter a bit more.
1251             inst->setCanCommit();
1252
1253             ++iewExecSquashedInsts;
1254
1255             continue;
1256         }
1257
1258         Fault fault = NoFault;
1259
1260         // Execute instruction.
1261         // Note that if the instruction faults, it will be handled
1262         // at the commit stage.
1263         if (inst->isMemRef()) {
1264             DPRINTF(IEW, "Execute: Calculating address for memory "
1265                     "reference.\n");
1266
1267             // Tell the LDSTQ to execute this instruction (if it is a load).
1268             if (inst->isAtomic()) {
1269                 // AMOs are treated like store requests
1270                 fault = ldstQueue.executeStore(inst);
1271
1272                 if (inst->isTranslationDelayed() &&
1273                     fault == NoFault) {
1274                     // A hw page table walk is currently going on; the
1275                     // instruction must be deferred.
1276                     DPRINTF(IEW, "Execute: Delayed translation, deferring "
1277                             "store.\n");
1278                     instQueue.deferMemInst(inst);
1279                     continue;
1280                 }
1281             } else if (inst->isLoad()) {
1282                 // Loads will mark themselves as executed, and their writeback
1283                 // event adds the instruction to the queue to commit
1284                 fault = ldstQueue.executeLoad(inst);
1285
1286                 if (inst->isTranslationDelayed() &&
1287                     fault == NoFault) {
1288                     // A hw page table walk is currently going on; the
1289                     // instruction must be deferred.
1290                     DPRINTF(IEW, "Execute: Delayed translation, deferring "
1291                             "load.\n");
1292                     instQueue.deferMemInst(inst);
1293                     continue;
1294                 }
1295
1296                 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1297                     inst->fault = NoFault;
1298                 }
1299             } else if (inst->isStore()) {
1300                 fault = ldstQueue.executeStore(inst);
1301
1302                 if (inst->isTranslationDelayed() &&
1303                     fault == NoFault) {
1304                     // A hw page table walk is currently going on; the
1305                     // instruction must be deferred.
1306                     DPRINTF(IEW, "Execute: Delayed translation, deferring "
1307                             "store.\n");
1308                     instQueue.deferMemInst(inst);
1309                     continue;
1310                 }
1311
1312                 // If the store had a fault then it may not have a mem req
1313                 if (fault != NoFault || !inst->readPredicate() ||
1314                         !inst->isStoreConditional()) {
1315                     // If the instruction faulted, then we need to send it along
1316                     // to commit without the instruction completing.
1317                     // Send this instruction to commit, also make sure iew stage
1318                     // realizes there is activity.
1319                     inst->setExecuted();
1320                     instToCommit(inst);
1321                     activityThisCycle();
1322                 }
1323
1324                 // Store conditionals will mark themselves as
1325                 // executed, and their writeback event will add the
1326                 // instruction to the queue to commit.
1327             } else {
1328                 panic("Unexpected memory type!\n");
1329             }
1330
1331         } else {
1332             // If the instruction has already faulted, then skip executing it.
1333             // Such case can happen when it faulted during ITLB translation.
1334             // If we execute the instruction (even if it's a nop) the fault
1335             // will be replaced and we will lose it.
1336             if (inst->getFault() == NoFault) {
1337                 inst->execute();
1338                 if (!inst->readPredicate())
1339                     inst->forwardOldRegs();
1340             }
1341
1342             inst->setExecuted();
1343
1344             instToCommit(inst);
1345         }
1346
1347         updateExeInstStats(inst);
1348
1349         // Check if branch prediction was correct, if not then we need
1350         // to tell commit to squash in flight instructions.  Only
1351         // handle this if there hasn't already been something that
1352         // redirects fetch in this group of instructions.
1353
1354         // This probably needs to prioritize the redirects if a different
1355         // scheduler is used.  Currently the scheduler schedules the oldest
1356         // instruction first, so the branch resolution order will be correct.
1357         ThreadID tid = inst->threadNumber;
1358
1359         if (!fetchRedirect[tid] ||
1360             !toCommit->squash[tid] ||
1361             toCommit->squashedSeqNum[tid] > inst->seqNum) {
1362
1363             // Prevent testing for misprediction on load instructions,
1364             // that have not been executed.
1365             bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1366
1367             if (inst->mispredicted() && !loadNotExecuted) {
1368                 fetchRedirect[tid] = true;
1369
1370                 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1371                         "Branch mispredict detected.\n",
1372                         tid,inst->seqNum);
1373                 DPRINTF(IEW, "[tid:%i] [sn:%llu] "
1374                         "Predicted target was PC: %s\n",
1375                         tid,inst->seqNum,inst->readPredTarg());
1376                 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1377                         "Redirecting fetch to PC: %s\n",
1378                         tid,inst->seqNum,inst->pcState());
1379                 // If incorrect, then signal the ROB that it must be squashed.
1380                 squashDueToBranch(inst, tid);
1381
1382                 ppMispredict->notify(inst);
1383
1384                 if (inst->readPredTaken()) {
1385                     predictedTakenIncorrect++;
1386                 } else {
1387                     predictedNotTakenIncorrect++;
1388                 }
1389             } else if (ldstQueue.violation(tid)) {
1390                 assert(inst->isMemRef());
1391                 // If there was an ordering violation, then get the
1392                 // DynInst that caused the violation.  Note that this
1393                 // clears the violation signal.
1394                 DynInstPtr violator;
1395                 violator = ldstQueue.getMemDepViolator(tid);
1396
1397                 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1398                         "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1399                         violator->pcState(), violator->seqNum,
1400                         inst->pcState(), inst->seqNum, inst->physEffAddr);
1401
1402                 fetchRedirect[tid] = true;
1403
1404                 // Tell the instruction queue that a violation has occured.
1405                 instQueue.violation(inst, violator);
1406
1407                 // Squash.
1408                 squashDueToMemOrder(violator, tid);
1409
1410                 ++memOrderViolationEvents;
1411             }
1412         } else {
1413             // Reset any state associated with redirects that will not
1414             // be used.
1415             if (ldstQueue.violation(tid)) {
1416                 assert(inst->isMemRef());
1417
1418                 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1419
1420                 DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1421                         "%s, inst PC: %s.  Addr is: %#x.\n",
1422                         violator->pcState(), inst->pcState(),
1423                         inst->physEffAddr);
1424                 DPRINTF(IEW, "Violation will not be handled because "
1425                         "already squashing\n");
1426
1427                 ++memOrderViolationEvents;
1428             }
1429         }
1430     }
1431
1432     // Update and record activity if we processed any instructions.
1433     if (inst_num) {
1434         if (exeStatus == Idle) {
1435             exeStatus = Running;
1436         }
1437
1438         updatedQueues = true;
1439
1440         cpu->activityThisCycle();
1441     }
1442
1443     // Need to reset this in case a writeback event needs to write into the
1444     // iew queue.  That way the writeback event will write into the correct
1445     // spot in the queue.
1446     wbNumInst = 0;
1447
1448 }
1449
1450 template <class Impl>
1451 void
1452 DefaultIEW<Impl>::writebackInsts()
1453 {
1454     // Loop through the head of the time buffer and wake any
1455     // dependents.  These instructions are about to write back.  Also
1456     // mark scoreboard that this instruction is finally complete.
1457     // Either have IEW have direct access to scoreboard, or have this
1458     // as part of backwards communication.
1459     for (int inst_num = 0; inst_num < wbWidth &&
1460              toCommit->insts[inst_num]; inst_num++) {
1461         DynInstPtr inst = toCommit->insts[inst_num];
1462         ThreadID tid = inst->threadNumber;
1463
1464         DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1465                 inst->seqNum, inst->pcState());
1466
1467         iewInstsToCommit[tid]++;
1468         // Notify potential listeners that execution is complete for this
1469         // instruction.
1470         ppToCommit->notify(inst);
1471
1472         // Some instructions will be sent to commit without having
1473         // executed because they need commit to handle them.
1474         // E.g. Strictly ordered loads have not actually executed when they
1475         // are first sent to commit.  Instead commit must tell the LSQ
1476         // when it's ready to execute the strictly ordered load.
1477         if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1478             int dependents = instQueue.wakeDependents(inst);
1479
1480             for (int i = 0; i < inst->numDestRegs(); i++) {
1481                 // Mark register as ready if not pinned
1482                 if (inst->renamedDestRegIdx(i)->
1483                         getNumPinnedWritesToComplete() == 0) {
1484                     DPRINTF(IEW,"Setting Destination Register %i (%s)\n",
1485                             inst->renamedDestRegIdx(i)->index(),
1486                             inst->renamedDestRegIdx(i)->className());
1487                     scoreboard->setReg(inst->renamedDestRegIdx(i));
1488                 }
1489             }
1490
1491             if (dependents) {
1492                 producerInst[tid]++;
1493                 consumerInst[tid]+= dependents;
1494             }
1495             writebackCount[tid]++;
1496         }
1497     }
1498 }
1499
1500 template<class Impl>
1501 void
1502 DefaultIEW<Impl>::tick()
1503 {
1504     wbNumInst = 0;
1505     wbCycle = 0;
1506
1507     wroteToTimeBuffer = false;
1508     updatedQueues = false;
1509
1510     ldstQueue.tick();
1511
1512     sortInsts();
1513
1514     // Free function units marked as being freed this cycle.
1515     fuPool->processFreeUnits();
1516
1517     list<ThreadID>::iterator threads = activeThreads->begin();
1518     list<ThreadID>::iterator end = activeThreads->end();
1519
1520     // Check stall and squash signals, dispatch any instructions.
1521     while (threads != end) {
1522         ThreadID tid = *threads++;
1523
1524         DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1525
1526         checkSignalsAndUpdate(tid);
1527         dispatch(tid);
1528     }
1529
1530     if (exeStatus != Squashing) {
1531         executeInsts();
1532
1533         writebackInsts();
1534
1535         // Have the instruction queue try to schedule any ready instructions.
1536         // (In actuality, this scheduling is for instructions that will
1537         // be executed next cycle.)
1538         instQueue.scheduleReadyInsts();
1539
1540         // Also should advance its own time buffers if the stage ran.
1541         // Not the best place for it, but this works (hopefully).
1542         issueToExecQueue.advance();
1543     }
1544
1545     bool broadcast_free_entries = false;
1546
1547     if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1548         exeStatus = Idle;
1549         updateLSQNextCycle = false;
1550
1551         broadcast_free_entries = true;
1552     }
1553
1554     // Writeback any stores using any leftover bandwidth.
1555     ldstQueue.writebackStores();
1556
1557     // Check the committed load/store signals to see if there's a load
1558     // or store to commit.  Also check if it's being told to execute a
1559     // nonspeculative instruction.
1560     // This is pretty inefficient...
1561
1562     threads = activeThreads->begin();
1563     while (threads != end) {
1564         ThreadID tid = (*threads++);
1565
1566         DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1567
1568         // Update structures based on instructions committed.
1569         if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1570             !fromCommit->commitInfo[tid].squash &&
1571             !fromCommit->commitInfo[tid].robSquashing) {
1572
1573             ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1574
1575             ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1576
1577             updateLSQNextCycle = true;
1578             instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1579         }
1580
1581         if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1582
1583             //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1584             if (fromCommit->commitInfo[tid].strictlyOrdered) {
1585                 instQueue.replayMemInst(
1586                     fromCommit->commitInfo[tid].strictlyOrderedLoad);
1587                 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1588             } else {
1589                 instQueue.scheduleNonSpec(
1590                     fromCommit->commitInfo[tid].nonSpecSeqNum);
1591             }
1592         }
1593
1594         if (broadcast_free_entries) {
1595             toFetch->iewInfo[tid].iqCount =
1596                 instQueue.getCount(tid);
1597             toFetch->iewInfo[tid].ldstqCount =
1598                 ldstQueue.getCount(tid);
1599
1600             toRename->iewInfo[tid].usedIQ = true;
1601             toRename->iewInfo[tid].freeIQEntries =
1602                 instQueue.numFreeEntries(tid);
1603             toRename->iewInfo[tid].usedLSQ = true;
1604
1605             toRename->iewInfo[tid].freeLQEntries =
1606                 ldstQueue.numFreeLoadEntries(tid);
1607             toRename->iewInfo[tid].freeSQEntries =
1608                 ldstQueue.numFreeStoreEntries(tid);
1609
1610             wroteToTimeBuffer = true;
1611         }
1612
1613         DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1614                 tid, toRename->iewInfo[tid].dispatched);
1615     }
1616
1617     DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1618             "LQ has %i free entries. SQ has %i free entries.\n",
1619             instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1620             ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries());
1621
1622     updateStatus();
1623
1624     if (wroteToTimeBuffer) {
1625         DPRINTF(Activity, "Activity this cycle.\n");
1626         cpu->activityThisCycle();
1627     }
1628 }
1629
1630 template <class Impl>
1631 void
1632 DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst)
1633 {
1634     ThreadID tid = inst->threadNumber;
1635
1636     iewExecutedInsts++;
1637
1638 #if TRACING_ON
1639     if (DTRACE(O3PipeView)) {
1640         inst->completeTick = curTick() - inst->fetchTick;
1641     }
1642 #endif
1643
1644     //
1645     //  Control operations
1646     //
1647     if (inst->isControl())
1648         iewExecutedBranches[tid]++;
1649
1650     //
1651     //  Memory operations
1652     //
1653     if (inst->isMemRef()) {
1654         iewExecutedRefs[tid]++;
1655
1656         if (inst->isLoad()) {
1657             iewExecLoadInsts[tid]++;
1658         }
1659     }
1660 }
1661
1662 template <class Impl>
1663 void
1664 DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst)
1665 {
1666     ThreadID tid = inst->threadNumber;
1667
1668     if (!fetchRedirect[tid] ||
1669         !toCommit->squash[tid] ||
1670         toCommit->squashedSeqNum[tid] > inst->seqNum) {
1671
1672         if (inst->mispredicted()) {
1673             fetchRedirect[tid] = true;
1674
1675             DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1676                     "Branch mispredict detected.\n",
1677                     tid,inst->seqNum);
1678             DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target "
1679                     "was PC:%#x, NPC:%#x\n",
1680                     tid,inst->seqNum,
1681                     inst->predInstAddr(), inst->predNextInstAddr());
1682             DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1683                     "Redirecting fetch to PC: %#x, "
1684                     "NPC: %#x.\n",
1685                     tid,inst->seqNum,
1686                     inst->nextInstAddr(),
1687                     inst->nextInstAddr());
1688             // If incorrect, then signal the ROB that it must be squashed.
1689             squashDueToBranch(inst, tid);
1690
1691             if (inst->readPredTaken()) {
1692                 predictedTakenIncorrect++;
1693             } else {
1694                 predictedNotTakenIncorrect++;
1695             }
1696         }
1697     }
1698 }
1699
1700 #endif//__CPU_O3_IEW_IMPL_IMPL_HH__