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44 #ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
45 #define __CPU_O3_IEW_IMPL_IMPL_HH__
47 // @todo: Fix the instantaneous communication among all the stages within
48 // iew. There's a clear delay between issue and execute, yet backwards
49 // communication happens simultaneously.
53 #include "arch/utility.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/checker/cpu.hh"
56 #include "cpu/o3/fu_pool.hh"
57 #include "cpu/o3/iew.hh"
58 #include "cpu/timebuf.hh"
59 #include "debug/Activity.hh"
60 #include "debug/Drain.hh"
61 #include "debug/IEW.hh"
62 #include "debug/O3PipeView.hh"
63 #include "params/DerivO3CPU.hh"
68 DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
69 : issueToExecQueue(params->backComSize, params->forwardComSize),
71 instQueue(_cpu, this, params),
72 ldstQueue(_cpu, this, params),
73 fuPool(params->fuPool),
74 commitToIEWDelay(params->commitToIEWDelay),
75 renameToIEWDelay(params->renameToIEWDelay),
76 issueToExecuteDelay(params->issueToExecuteDelay),
77 dispatchWidth(params->dispatchWidth),
78 issueWidth(params->issueWidth),
79 wbWidth(params->wbWidth),
80 numThreads(params->numThreads)
82 if (dispatchWidth > Impl::MaxWidth)
83 fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
84 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
85 dispatchWidth, static_cast<int>(Impl::MaxWidth));
86 if (issueWidth > Impl::MaxWidth)
87 fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
88 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
89 issueWidth, static_cast<int>(Impl::MaxWidth));
90 if (wbWidth > Impl::MaxWidth)
91 fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
92 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
93 wbWidth, static_cast<int>(Impl::MaxWidth));
99 // Setup wire to read instructions coming from issue.
100 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
102 // Instruction queue needs the queue between issue and execute.
103 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
106 dispatchStatus[tid] = Running;
107 fetchRedirect[tid] = false;
110 updateLSQNextCycle = false;
112 skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
115 template <class Impl>
117 DefaultIEW<Impl>::name() const
119 return cpu->name() + ".iew";
122 template <class Impl>
124 DefaultIEW<Impl>::regProbePoints()
126 ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
127 ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
129 * Probe point with dynamic instruction as the argument used to probe when
130 * an instruction starts to execute.
132 ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
135 * Probe point with dynamic instruction as the argument used to probe when
136 * an instruction execution completes and it is marked ready to commit.
138 ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
142 template <class Impl>
144 DefaultIEW<Impl>::regStats()
146 using namespace Stats;
148 instQueue.regStats();
149 ldstQueue.regStats();
152 .name(name() + ".iewIdleCycles")
153 .desc("Number of cycles IEW is idle");
156 .name(name() + ".iewSquashCycles")
157 .desc("Number of cycles IEW is squashing");
160 .name(name() + ".iewBlockCycles")
161 .desc("Number of cycles IEW is blocking");
164 .name(name() + ".iewUnblockCycles")
165 .desc("Number of cycles IEW is unblocking");
168 .name(name() + ".iewDispatchedInsts")
169 .desc("Number of instructions dispatched to IQ");
172 .name(name() + ".iewDispSquashedInsts")
173 .desc("Number of squashed instructions skipped by dispatch");
176 .name(name() + ".iewDispLoadInsts")
177 .desc("Number of dispatched load instructions");
180 .name(name() + ".iewDispStoreInsts")
181 .desc("Number of dispatched store instructions");
184 .name(name() + ".iewDispNonSpecInsts")
185 .desc("Number of dispatched non-speculative instructions");
188 .name(name() + ".iewIQFullEvents")
189 .desc("Number of times the IQ has become full, causing a stall");
192 .name(name() + ".iewLSQFullEvents")
193 .desc("Number of times the LSQ has become full, causing a stall");
195 memOrderViolationEvents
196 .name(name() + ".memOrderViolationEvents")
197 .desc("Number of memory order violations");
199 predictedTakenIncorrect
200 .name(name() + ".predictedTakenIncorrect")
201 .desc("Number of branches that were predicted taken incorrectly");
203 predictedNotTakenIncorrect
204 .name(name() + ".predictedNotTakenIncorrect")
205 .desc("Number of branches that were predicted not taken incorrectly");
208 .name(name() + ".branchMispredicts")
209 .desc("Number of branch mispredicts detected at execute");
211 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
214 .name(name() + ".iewExecutedInsts")
215 .desc("Number of executed instructions");
218 .init(cpu->numThreads)
219 .name(name() + ".iewExecLoadInsts")
220 .desc("Number of load instructions executed")
224 .name(name() + ".iewExecSquashedInsts")
225 .desc("Number of squashed instructions skipped in execute");
228 .init(cpu->numThreads)
229 .name(name() + ".exec_swp")
230 .desc("number of swp insts executed")
234 .init(cpu->numThreads)
235 .name(name() + ".exec_nop")
236 .desc("number of nop insts executed")
240 .init(cpu->numThreads)
241 .name(name() + ".exec_refs")
242 .desc("number of memory reference insts executed")
246 .init(cpu->numThreads)
247 .name(name() + ".exec_branches")
248 .desc("Number of branches executed")
252 .name(name() + ".exec_stores")
253 .desc("Number of stores executed")
255 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
258 .name(name() + ".exec_rate")
259 .desc("Inst execution rate")
262 iewExecRate = iewExecutedInsts / cpu->numCycles;
265 .init(cpu->numThreads)
266 .name(name() + ".wb_sent")
267 .desc("cumulative count of insts sent to commit")
271 .init(cpu->numThreads)
272 .name(name() + ".wb_count")
273 .desc("cumulative count of insts written-back")
277 .init(cpu->numThreads)
278 .name(name() + ".wb_producers")
279 .desc("num instructions producing a value")
283 .init(cpu->numThreads)
284 .name(name() + ".wb_consumers")
285 .desc("num instructions consuming a value")
289 .name(name() + ".wb_fanout")
290 .desc("average fanout of values written-back")
293 wbFanout = producerInst / consumerInst;
296 .name(name() + ".wb_rate")
297 .desc("insts written-back per cycle")
299 wbRate = writebackCount / cpu->numCycles;
304 DefaultIEW<Impl>::startupStage()
306 for (ThreadID tid = 0; tid < numThreads; tid++) {
307 toRename->iewInfo[tid].usedIQ = true;
308 toRename->iewInfo[tid].freeIQEntries =
309 instQueue.numFreeEntries(tid);
311 toRename->iewInfo[tid].usedLSQ = true;
312 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
313 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
316 // Initialize the checker's dcache port here
318 cpu->checker->setDcachePort(&cpu->getDataPort());
321 cpu->activateStage(O3CPU::IEWIdx);
326 DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
330 // Setup wire to read information from time buffer, from commit.
331 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
333 // Setup wire to write information back to previous stages.
334 toRename = timeBuffer->getWire(0);
336 toFetch = timeBuffer->getWire(0);
338 // Instruction queue also needs main time buffer.
339 instQueue.setTimeBuffer(tb_ptr);
344 DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
346 renameQueue = rq_ptr;
348 // Setup wire to read information from rename queue.
349 fromRename = renameQueue->getWire(-renameToIEWDelay);
354 DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
358 // Setup wire to write instructions to commit.
359 toCommit = iewQueue->getWire(0);
364 DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
366 activeThreads = at_ptr;
368 ldstQueue.setActiveThreads(at_ptr);
369 instQueue.setActiveThreads(at_ptr);
374 DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
379 template <class Impl>
381 DefaultIEW<Impl>::isDrained() const
383 bool drained = ldstQueue.isDrained() && instQueue.isDrained();
385 for (ThreadID tid = 0; tid < numThreads; tid++) {
386 if (!insts[tid].empty()) {
387 DPRINTF(Drain, "%i: Insts not empty.\n", tid);
390 if (!skidBuffer[tid].empty()) {
391 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
394 drained = drained && dispatchStatus[tid] == Running;
397 // Also check the FU pool as instructions are "stored" in FU
398 // completion events until they are done and not accounted for
400 if (drained && !fuPool->isDrained()) {
401 DPRINTF(Drain, "FU pool still busy.\n");
408 template <class Impl>
410 DefaultIEW<Impl>::drainSanityCheck() const
414 instQueue.drainSanityCheck();
415 ldstQueue.drainSanityCheck();
418 template <class Impl>
420 DefaultIEW<Impl>::takeOverFrom()
427 instQueue.takeOverFrom();
428 ldstQueue.takeOverFrom();
429 fuPool->takeOverFrom();
432 cpu->activityThisCycle();
434 for (ThreadID tid = 0; tid < numThreads; tid++) {
435 dispatchStatus[tid] = Running;
436 fetchRedirect[tid] = false;
439 updateLSQNextCycle = false;
441 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
442 issueToExecQueue.advance();
448 DefaultIEW<Impl>::squash(ThreadID tid)
450 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
452 // Tell the IQ to start squashing.
453 instQueue.squash(tid);
455 // Tell the LDSTQ to start squashing.
456 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
457 updatedQueues = true;
459 // Clear the skid buffer in case it has any data in it.
460 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
461 tid, fromCommit->commitInfo[tid].doneSeqNum);
463 while (!skidBuffer[tid].empty()) {
464 if (skidBuffer[tid].front()->isLoad()) {
465 toRename->iewInfo[tid].dispatchedToLQ++;
467 if (skidBuffer[tid].front()->isStore()) {
468 toRename->iewInfo[tid].dispatchedToSQ++;
471 toRename->iewInfo[tid].dispatched++;
473 skidBuffer[tid].pop();
476 emptyRenameInsts(tid);
481 DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
483 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
484 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
486 if (!toCommit->squash[tid] ||
487 inst->seqNum < toCommit->squashedSeqNum[tid]) {
488 toCommit->squash[tid] = true;
489 toCommit->squashedSeqNum[tid] = inst->seqNum;
490 toCommit->branchTaken[tid] = inst->pcState().branching();
492 TheISA::PCState pc = inst->pcState();
493 TheISA::advancePC(pc, inst->staticInst);
495 toCommit->pc[tid] = pc;
496 toCommit->mispredictInst[tid] = inst;
497 toCommit->includeSquashInst[tid] = false;
499 wroteToTimeBuffer = true;
506 DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
508 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
509 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
510 // Need to include inst->seqNum in the following comparison to cover the
511 // corner case when a branch misprediction and a memory violation for the
512 // same instruction (e.g. load PC) are detected in the same cycle. In this
513 // case the memory violator should take precedence over the branch
514 // misprediction because it requires the violator itself to be included in
516 if (!toCommit->squash[tid] ||
517 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
518 toCommit->squash[tid] = true;
520 toCommit->squashedSeqNum[tid] = inst->seqNum;
521 toCommit->pc[tid] = inst->pcState();
522 toCommit->mispredictInst[tid] = NULL;
524 // Must include the memory violator in the squash.
525 toCommit->includeSquashInst[tid] = true;
527 wroteToTimeBuffer = true;
533 DefaultIEW<Impl>::block(ThreadID tid)
535 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
537 if (dispatchStatus[tid] != Blocked &&
538 dispatchStatus[tid] != Unblocking) {
539 toRename->iewBlock[tid] = true;
540 wroteToTimeBuffer = true;
543 // Add the current inputs to the skid buffer so they can be
544 // reprocessed when this stage unblocks.
547 dispatchStatus[tid] = Blocked;
552 DefaultIEW<Impl>::unblock(ThreadID tid)
554 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
555 "buffer %u.\n",tid, tid);
557 // If the skid bufffer is empty, signal back to previous stages to unblock.
558 // Also switch status to running.
559 if (skidBuffer[tid].empty()) {
560 toRename->iewUnblock[tid] = true;
561 wroteToTimeBuffer = true;
562 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
563 dispatchStatus[tid] = Running;
569 DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst)
571 instQueue.wakeDependents(inst);
576 DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst)
578 instQueue.rescheduleMemInst(inst);
583 DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst)
585 instQueue.replayMemInst(inst);
590 DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst)
592 instQueue.blockMemInst(inst);
597 DefaultIEW<Impl>::cacheUnblocked()
599 instQueue.cacheUnblocked();
604 DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst)
606 // This function should not be called after writebackInsts in a
607 // single cycle. That will cause problems with an instruction
608 // being added to the queue to commit without being processed by
609 // writebackInsts prior to being sent to commit.
611 // First check the time slot that this instruction will write
612 // to. If there are free write ports at the time, then go ahead
613 // and write the instruction to that time. If there are not,
614 // keep looking back to see where's the first time there's a
616 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
618 if (wbNumInst == wbWidth) {
624 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
625 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
626 // Add finished instruction to queue to commit.
627 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
628 (*iewQueue)[wbCycle].size++;
631 template <class Impl>
633 DefaultIEW<Impl>::validInstsFromRename()
635 unsigned inst_count = 0;
637 for (int i=0; i<fromRename->size; i++) {
638 if (!fromRename->insts[i]->isSquashed())
647 DefaultIEW<Impl>::skidInsert(ThreadID tid)
649 DynInstPtr inst = NULL;
651 while (!insts[tid].empty()) {
652 inst = insts[tid].front();
656 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
657 "dispatch skidBuffer %i\n",tid, inst->seqNum,
658 inst->pcState(),tid);
660 skidBuffer[tid].push(inst);
663 assert(skidBuffer[tid].size() <= skidBufferMax &&
664 "Skidbuffer Exceeded Max Size");
669 DefaultIEW<Impl>::skidCount()
673 list<ThreadID>::iterator threads = activeThreads->begin();
674 list<ThreadID>::iterator end = activeThreads->end();
676 while (threads != end) {
677 ThreadID tid = *threads++;
678 unsigned thread_count = skidBuffer[tid].size();
679 if (max < thread_count)
688 DefaultIEW<Impl>::skidsEmpty()
690 list<ThreadID>::iterator threads = activeThreads->begin();
691 list<ThreadID>::iterator end = activeThreads->end();
693 while (threads != end) {
694 ThreadID tid = *threads++;
696 if (!skidBuffer[tid].empty())
703 template <class Impl>
705 DefaultIEW<Impl>::updateStatus()
707 bool any_unblocking = false;
709 list<ThreadID>::iterator threads = activeThreads->begin();
710 list<ThreadID>::iterator end = activeThreads->end();
712 while (threads != end) {
713 ThreadID tid = *threads++;
715 if (dispatchStatus[tid] == Unblocking) {
716 any_unblocking = true;
721 // If there are no ready instructions waiting to be scheduled by the IQ,
722 // and there's no stores waiting to write back, and dispatch is not
723 // unblocking, then there is no internal activity for the IEW stage.
724 instQueue.intInstQueueReads++;
725 if (_status == Active && !instQueue.hasReadyInsts() &&
726 !ldstQueue.willWB() && !any_unblocking) {
727 DPRINTF(IEW, "IEW switching to idle\n");
732 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
733 ldstQueue.willWB() ||
735 // Otherwise there is internal activity. Set to active.
736 DPRINTF(IEW, "IEW switching to active\n");
744 template <class Impl>
746 DefaultIEW<Impl>::resetEntries()
748 instQueue.resetEntries();
749 ldstQueue.resetEntries();
752 template <class Impl>
754 DefaultIEW<Impl>::checkStall(ThreadID tid)
758 if (fromCommit->commitInfo[tid].robSquashing) {
759 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
761 } else if (instQueue.isFull(tid)) {
762 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
769 template <class Impl>
771 DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
773 // Check if there's a squash signal, squash if there is
774 // Check stall signals, block if there is.
775 // If status was Blocked
776 // if so then go to unblocking
777 // If status was Squashing
778 // check if squashing is not high. Switch to running this cycle.
780 if (fromCommit->commitInfo[tid].squash) {
783 if (dispatchStatus[tid] == Blocked ||
784 dispatchStatus[tid] == Unblocking) {
785 toRename->iewUnblock[tid] = true;
786 wroteToTimeBuffer = true;
789 dispatchStatus[tid] = Squashing;
790 fetchRedirect[tid] = false;
794 if (fromCommit->commitInfo[tid].robSquashing) {
795 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
797 dispatchStatus[tid] = Squashing;
798 emptyRenameInsts(tid);
799 wroteToTimeBuffer = true;
802 if (checkStall(tid)) {
804 dispatchStatus[tid] = Blocked;
808 if (dispatchStatus[tid] == Blocked) {
809 // Status from previous cycle was blocked, but there are no more stall
810 // conditions. Switch over to unblocking.
811 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
814 dispatchStatus[tid] = Unblocking;
821 if (dispatchStatus[tid] == Squashing) {
822 // Switch status to running if rename isn't being told to block or
823 // squash this cycle.
824 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
827 dispatchStatus[tid] = Running;
833 template <class Impl>
835 DefaultIEW<Impl>::sortInsts()
837 int insts_from_rename = fromRename->size;
839 for (ThreadID tid = 0; tid < numThreads; tid++)
840 assert(insts[tid].empty());
842 for (int i = 0; i < insts_from_rename; ++i) {
843 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
847 template <class Impl>
849 DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
851 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
853 while (!insts[tid].empty()) {
855 if (insts[tid].front()->isLoad()) {
856 toRename->iewInfo[tid].dispatchedToLQ++;
858 if (insts[tid].front()->isStore()) {
859 toRename->iewInfo[tid].dispatchedToSQ++;
862 toRename->iewInfo[tid].dispatched++;
868 template <class Impl>
870 DefaultIEW<Impl>::wakeCPU()
875 template <class Impl>
877 DefaultIEW<Impl>::activityThisCycle()
879 DPRINTF(Activity, "Activity this cycle.\n");
880 cpu->activityThisCycle();
883 template <class Impl>
885 DefaultIEW<Impl>::activateStage()
887 DPRINTF(Activity, "Activating stage.\n");
888 cpu->activateStage(O3CPU::IEWIdx);
891 template <class Impl>
893 DefaultIEW<Impl>::deactivateStage()
895 DPRINTF(Activity, "Deactivating stage.\n");
896 cpu->deactivateStage(O3CPU::IEWIdx);
901 DefaultIEW<Impl>::dispatch(ThreadID tid)
903 // If status is Running or idle,
904 // call dispatchInsts()
905 // If status is Unblocking,
906 // buffer any instructions coming from rename
907 // continue trying to empty skid buffer
908 // check if stall conditions have passed
910 if (dispatchStatus[tid] == Blocked) {
913 } else if (dispatchStatus[tid] == Squashing) {
917 // Dispatch should try to dispatch as many instructions as its bandwidth
918 // will allow, as long as it is not currently blocked.
919 if (dispatchStatus[tid] == Running ||
920 dispatchStatus[tid] == Idle) {
921 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
925 } else if (dispatchStatus[tid] == Unblocking) {
926 // Make sure that the skid buffer has something in it if the
927 // status is unblocking.
928 assert(!skidsEmpty());
930 // If the status was unblocking, then instructions from the skid
931 // buffer were used. Remove those instructions and handle
932 // the rest of unblocking.
937 if (validInstsFromRename()) {
938 // Add the current inputs to the skid buffer so they can be
939 // reprocessed when this stage unblocks.
947 template <class Impl>
949 DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
951 // Obtain instructions from skid buffer if unblocking, or queue from rename
953 std::queue<DynInstPtr> &insts_to_dispatch =
954 dispatchStatus[tid] == Unblocking ?
955 skidBuffer[tid] : insts[tid];
957 int insts_to_add = insts_to_dispatch.size();
960 bool add_to_iq = false;
961 int dis_num_inst = 0;
963 // Loop through the instructions, putting them in the instruction
965 for ( ; dis_num_inst < insts_to_add &&
966 dis_num_inst < dispatchWidth;
969 inst = insts_to_dispatch.front();
971 if (dispatchStatus[tid] == Unblocking) {
972 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
976 // Make sure there's a valid instruction there.
979 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
981 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
983 // Be sure to mark these instructions as ready so that the
984 // commit stage can go ahead and execute them, and mark
985 // them as issued so the IQ doesn't reprocess them.
987 // Check for squashed instructions.
988 if (inst->isSquashed()) {
989 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
990 "not adding to IQ.\n", tid);
992 ++iewDispSquashedInsts;
994 insts_to_dispatch.pop();
996 //Tell Rename That An Instruction has been processed
997 if (inst->isLoad()) {
998 toRename->iewInfo[tid].dispatchedToLQ++;
1000 if (inst->isStore()) {
1001 toRename->iewInfo[tid].dispatchedToSQ++;
1004 toRename->iewInfo[tid].dispatched++;
1009 // Check for full conditions.
1010 if (instQueue.isFull(tid)) {
1011 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1013 // Call function to start blocking.
1016 // Set unblock to false. Special case where we are using
1017 // skidbuffer (unblocking) instructions but then we still
1018 // get full in the IQ.
1019 toRename->iewUnblock[tid] = false;
1025 // Check LSQ if inst is LD/ST
1026 if ((inst->isLoad() && ldstQueue.lqFull(tid)) ||
1027 (inst->isStore() && ldstQueue.sqFull(tid))) {
1028 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
1029 inst->isLoad() ? "LQ" : "SQ");
1031 // Call function to start blocking.
1034 // Set unblock to false. Special case where we are using
1035 // skidbuffer (unblocking) instructions but then we still
1036 // get full in the IQ.
1037 toRename->iewUnblock[tid] = false;
1043 // Otherwise issue the instruction just fine.
1044 if (inst->isLoad()) {
1045 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1046 "encountered, adding to LSQ.\n", tid);
1048 // Reserve a spot in the load store queue for this
1050 ldstQueue.insertLoad(inst);
1056 toRename->iewInfo[tid].dispatchedToLQ++;
1057 } else if (inst->isStore()) {
1058 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1059 "encountered, adding to LSQ.\n", tid);
1061 ldstQueue.insertStore(inst);
1063 ++iewDispStoreInsts;
1065 if (inst->isStoreConditional()) {
1066 // Store conditionals need to be set as "canCommit()"
1067 // so that commit can process them when they reach the
1069 // @todo: This is somewhat specific to Alpha.
1070 inst->setCanCommit();
1071 instQueue.insertNonSpec(inst);
1074 ++iewDispNonSpecInsts;
1079 toRename->iewInfo[tid].dispatchedToSQ++;
1080 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1081 // Same as non-speculative stores.
1082 inst->setCanCommit();
1083 instQueue.insertBarrier(inst);
1085 } else if (inst->isNop()) {
1086 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1087 "skipping.\n", tid);
1090 inst->setExecuted();
1091 inst->setCanCommit();
1093 instQueue.recordProducer(inst);
1095 iewExecutedNop[tid]++;
1099 assert(!inst->isExecuted());
1103 if (add_to_iq && inst->isNonSpeculative()) {
1104 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1105 "encountered, skipping.\n", tid);
1107 // Same as non-speculative stores.
1108 inst->setCanCommit();
1110 // Specifically insert it as nonspeculative.
1111 instQueue.insertNonSpec(inst);
1113 ++iewDispNonSpecInsts;
1118 // If the instruction queue is not full, then add the
1121 instQueue.insert(inst);
1124 insts_to_dispatch.pop();
1126 toRename->iewInfo[tid].dispatched++;
1128 ++iewDispatchedInsts;
1131 inst->dispatchTick = curTick() - inst->fetchTick;
1133 ppDispatch->notify(inst);
1136 if (!insts_to_dispatch.empty()) {
1137 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1139 toRename->iewUnblock[tid] = false;
1142 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1143 dispatchStatus[tid] = Running;
1145 updatedQueues = true;
1151 template <class Impl>
1153 DefaultIEW<Impl>::printAvailableInsts()
1157 std::cout << "Available Instructions: ";
1159 while (fromIssue->insts[inst]) {
1161 if (inst%3==0) std::cout << "\n\t";
1163 std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1164 << " TN: " << fromIssue->insts[inst]->threadNumber
1165 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1174 template <class Impl>
1176 DefaultIEW<Impl>::executeInsts()
1181 list<ThreadID>::iterator threads = activeThreads->begin();
1182 list<ThreadID>::iterator end = activeThreads->end();
1184 while (threads != end) {
1185 ThreadID tid = *threads++;
1186 fetchRedirect[tid] = false;
1189 // Uncomment this if you want to see all available instructions.
1190 // @todo This doesn't actually work anymore, we should fix it.
1191 // printAvailableInsts();
1193 // Execute/writeback any instructions that are available.
1194 int insts_to_execute = fromIssue->size;
1196 for (; inst_num < insts_to_execute;
1199 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1201 DynInstPtr inst = instQueue.getInstToExecute();
1203 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1204 inst->pcState(), inst->threadNumber,inst->seqNum);
1206 // Notify potential listeners that this instruction has started
1208 ppExecute->notify(inst);
1210 // Check if the instruction is squashed; if so then skip it
1211 if (inst->isSquashed()) {
1212 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1213 " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1216 // Consider this instruction executed so that commit can go
1217 // ahead and retire the instruction.
1218 inst->setExecuted();
1220 // Not sure if I should set this here or just let commit try to
1221 // commit any squashed instructions. I like the latter a bit more.
1222 inst->setCanCommit();
1224 ++iewExecSquashedInsts;
1229 Fault fault = NoFault;
1231 // Execute instruction.
1232 // Note that if the instruction faults, it will be handled
1233 // at the commit stage.
1234 if (inst->isMemRef()) {
1235 DPRINTF(IEW, "Execute: Calculating address for memory "
1238 // Tell the LDSTQ to execute this instruction (if it is a load).
1239 if (inst->isLoad()) {
1240 // Loads will mark themselves as executed, and their writeback
1241 // event adds the instruction to the queue to commit
1242 fault = ldstQueue.executeLoad(inst);
1244 if (inst->isTranslationDelayed() &&
1246 // A hw page table walk is currently going on; the
1247 // instruction must be deferred.
1248 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1250 instQueue.deferMemInst(inst);
1254 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1255 inst->fault = NoFault;
1257 } else if (inst->isStore()) {
1258 fault = ldstQueue.executeStore(inst);
1260 if (inst->isTranslationDelayed() &&
1262 // A hw page table walk is currently going on; the
1263 // instruction must be deferred.
1264 DPRINTF(IEW, "Execute: Delayed translation, deferring "
1266 instQueue.deferMemInst(inst);
1270 // If the store had a fault then it may not have a mem req
1271 if (fault != NoFault || !inst->readPredicate() ||
1272 !inst->isStoreConditional()) {
1273 // If the instruction faulted, then we need to send it along
1274 // to commit without the instruction completing.
1275 // Send this instruction to commit, also make sure iew stage
1276 // realizes there is activity.
1277 inst->setExecuted();
1279 activityThisCycle();
1282 // Store conditionals will mark themselves as
1283 // executed, and their writeback event will add the
1284 // instruction to the queue to commit.
1286 panic("Unexpected memory type!\n");
1290 // If the instruction has already faulted, then skip executing it.
1291 // Such case can happen when it faulted during ITLB translation.
1292 // If we execute the instruction (even if it's a nop) the fault
1293 // will be replaced and we will lose it.
1294 if (inst->getFault() == NoFault) {
1296 if (!inst->readPredicate())
1297 inst->forwardOldRegs();
1300 inst->setExecuted();
1305 updateExeInstStats(inst);
1307 // Check if branch prediction was correct, if not then we need
1308 // to tell commit to squash in flight instructions. Only
1309 // handle this if there hasn't already been something that
1310 // redirects fetch in this group of instructions.
1312 // This probably needs to prioritize the redirects if a different
1313 // scheduler is used. Currently the scheduler schedules the oldest
1314 // instruction first, so the branch resolution order will be correct.
1315 ThreadID tid = inst->threadNumber;
1317 if (!fetchRedirect[tid] ||
1318 !toCommit->squash[tid] ||
1319 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1321 // Prevent testing for misprediction on load instructions,
1322 // that have not been executed.
1323 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1325 if (inst->mispredicted() && !loadNotExecuted) {
1326 fetchRedirect[tid] = true;
1328 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1329 DPRINTF(IEW, "Predicted target was PC: %s.\n",
1330 inst->readPredTarg());
1331 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1333 // If incorrect, then signal the ROB that it must be squashed.
1334 squashDueToBranch(inst, tid);
1336 ppMispredict->notify(inst);
1338 if (inst->readPredTaken()) {
1339 predictedTakenIncorrect++;
1341 predictedNotTakenIncorrect++;
1343 } else if (ldstQueue.violation(tid)) {
1344 assert(inst->isMemRef());
1345 // If there was an ordering violation, then get the
1346 // DynInst that caused the violation. Note that this
1347 // clears the violation signal.
1348 DynInstPtr violator;
1349 violator = ldstQueue.getMemDepViolator(tid);
1351 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1352 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1353 violator->pcState(), violator->seqNum,
1354 inst->pcState(), inst->seqNum, inst->physEffAddrLow);
1356 fetchRedirect[tid] = true;
1358 // Tell the instruction queue that a violation has occured.
1359 instQueue.violation(inst, violator);
1362 squashDueToMemOrder(violator, tid);
1364 ++memOrderViolationEvents;
1367 // Reset any state associated with redirects that will not
1369 if (ldstQueue.violation(tid)) {
1370 assert(inst->isMemRef());
1372 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1374 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1375 "%s, inst PC: %s. Addr is: %#x.\n",
1376 violator->pcState(), inst->pcState(),
1377 inst->physEffAddrLow);
1378 DPRINTF(IEW, "Violation will not be handled because "
1379 "already squashing\n");
1381 ++memOrderViolationEvents;
1386 // Update and record activity if we processed any instructions.
1388 if (exeStatus == Idle) {
1389 exeStatus = Running;
1392 updatedQueues = true;
1394 cpu->activityThisCycle();
1397 // Need to reset this in case a writeback event needs to write into the
1398 // iew queue. That way the writeback event will write into the correct
1399 // spot in the queue.
1404 template <class Impl>
1406 DefaultIEW<Impl>::writebackInsts()
1408 // Loop through the head of the time buffer and wake any
1409 // dependents. These instructions are about to write back. Also
1410 // mark scoreboard that this instruction is finally complete.
1411 // Either have IEW have direct access to scoreboard, or have this
1412 // as part of backwards communication.
1413 for (int inst_num = 0; inst_num < wbWidth &&
1414 toCommit->insts[inst_num]; inst_num++) {
1415 DynInstPtr inst = toCommit->insts[inst_num];
1416 ThreadID tid = inst->threadNumber;
1418 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1419 inst->seqNum, inst->pcState());
1421 iewInstsToCommit[tid]++;
1422 // Notify potential listeners that execution is complete for this
1424 ppToCommit->notify(inst);
1426 // Some instructions will be sent to commit without having
1427 // executed because they need commit to handle them.
1428 // E.g. Strictly ordered loads have not actually executed when they
1429 // are first sent to commit. Instead commit must tell the LSQ
1430 // when it's ready to execute the strictly ordered load.
1431 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1432 int dependents = instQueue.wakeDependents(inst);
1434 for (int i = 0; i < inst->numDestRegs(); i++) {
1436 DPRINTF(IEW,"Setting Destination Register %i (%s)\n",
1437 inst->renamedDestRegIdx(i)->index(),
1438 inst->renamedDestRegIdx(i)->className());
1439 scoreboard->setReg(inst->renamedDestRegIdx(i));
1443 producerInst[tid]++;
1444 consumerInst[tid]+= dependents;
1446 writebackCount[tid]++;
1451 template<class Impl>
1453 DefaultIEW<Impl>::tick()
1458 wroteToTimeBuffer = false;
1459 updatedQueues = false;
1463 // Free function units marked as being freed this cycle.
1464 fuPool->processFreeUnits();
1466 list<ThreadID>::iterator threads = activeThreads->begin();
1467 list<ThreadID>::iterator end = activeThreads->end();
1469 // Check stall and squash signals, dispatch any instructions.
1470 while (threads != end) {
1471 ThreadID tid = *threads++;
1473 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1475 checkSignalsAndUpdate(tid);
1479 if (exeStatus != Squashing) {
1484 // Have the instruction queue try to schedule any ready instructions.
1485 // (In actuality, this scheduling is for instructions that will
1486 // be executed next cycle.)
1487 instQueue.scheduleReadyInsts();
1489 // Also should advance its own time buffers if the stage ran.
1490 // Not the best place for it, but this works (hopefully).
1491 issueToExecQueue.advance();
1494 bool broadcast_free_entries = false;
1496 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1498 updateLSQNextCycle = false;
1500 broadcast_free_entries = true;
1503 // Writeback any stores using any leftover bandwidth.
1504 ldstQueue.writebackStores();
1506 // Check the committed load/store signals to see if there's a load
1507 // or store to commit. Also check if it's being told to execute a
1508 // nonspeculative instruction.
1509 // This is pretty inefficient...
1511 threads = activeThreads->begin();
1512 while (threads != end) {
1513 ThreadID tid = (*threads++);
1515 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1517 // Update structures based on instructions committed.
1518 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1519 !fromCommit->commitInfo[tid].squash &&
1520 !fromCommit->commitInfo[tid].robSquashing) {
1522 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1524 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1526 updateLSQNextCycle = true;
1527 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1530 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1532 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1533 if (fromCommit->commitInfo[tid].strictlyOrdered) {
1534 instQueue.replayMemInst(
1535 fromCommit->commitInfo[tid].strictlyOrderedLoad);
1536 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1538 instQueue.scheduleNonSpec(
1539 fromCommit->commitInfo[tid].nonSpecSeqNum);
1543 if (broadcast_free_entries) {
1544 toFetch->iewInfo[tid].iqCount =
1545 instQueue.getCount(tid);
1546 toFetch->iewInfo[tid].ldstqCount =
1547 ldstQueue.getCount(tid);
1549 toRename->iewInfo[tid].usedIQ = true;
1550 toRename->iewInfo[tid].freeIQEntries =
1551 instQueue.numFreeEntries(tid);
1552 toRename->iewInfo[tid].usedLSQ = true;
1554 toRename->iewInfo[tid].freeLQEntries =
1555 ldstQueue.numFreeLoadEntries(tid);
1556 toRename->iewInfo[tid].freeSQEntries =
1557 ldstQueue.numFreeStoreEntries(tid);
1559 wroteToTimeBuffer = true;
1562 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1563 tid, toRename->iewInfo[tid].dispatched);
1566 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1567 "LQ has %i free entries. SQ has %i free entries.\n",
1568 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1569 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries());
1573 if (wroteToTimeBuffer) {
1574 DPRINTF(Activity, "Activity this cycle.\n");
1575 cpu->activityThisCycle();
1579 template <class Impl>
1581 DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst)
1583 ThreadID tid = inst->threadNumber;
1588 if (DTRACE(O3PipeView)) {
1589 inst->completeTick = curTick() - inst->fetchTick;
1594 // Control operations
1596 if (inst->isControl())
1597 iewExecutedBranches[tid]++;
1600 // Memory operations
1602 if (inst->isMemRef()) {
1603 iewExecutedRefs[tid]++;
1605 if (inst->isLoad()) {
1606 iewExecLoadInsts[tid]++;
1611 template <class Impl>
1613 DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst)
1615 ThreadID tid = inst->threadNumber;
1617 if (!fetchRedirect[tid] ||
1618 !toCommit->squash[tid] ||
1619 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1621 if (inst->mispredicted()) {
1622 fetchRedirect[tid] = true;
1624 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1625 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1626 inst->predInstAddr(), inst->predNextInstAddr());
1627 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1628 " NPC: %#x.\n", inst->nextInstAddr(),
1629 inst->nextInstAddr());
1630 // If incorrect, then signal the ROB that it must be squashed.
1631 squashDueToBranch(inst, tid);
1633 if (inst->readPredTaken()) {
1634 predictedTakenIncorrect++;
1636 predictedNotTakenIncorrect++;
1642 #endif//__CPU_O3_IEW_IMPL_IMPL_HH__