src/cpu/o3/iew_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 // @todo: Fix the instantaneous communication among all the stages within
  32 // iew.  There's a clear delay between issue and execute, yet backwards
  33 // communication happens simultaneously.
  34
  35 #include <queue>
  36
  37 #include "base/timebuf.hh"
  38 #include "cpu/o3/fu_pool.hh"
  39 #include "cpu/o3/iew.hh"
  40
  41 template<class Impl>
  42 DefaultIEW<Impl>::DefaultIEW(Params *params)
  43     : issueToExecQueue(params->backComSize, params->forwardComSize),
  44       instQueue(params),
  45       ldstQueue(params),
  46       fuPool(params->fuPool),
  47       commitToIEWDelay(params->commitToIEWDelay),
  48       renameToIEWDelay(params->renameToIEWDelay),
  49       issueToExecuteDelay(params->issueToExecuteDelay),
  50       dispatchWidth(params->dispatchWidth),
  51       issueWidth(params->issueWidth),
  52       wbOutstanding(0),
  53       wbWidth(params->wbWidth),
  54       numThreads(params->numberOfThreads),
  55       switchedOut(false)
  56 {
  57     _status = Active;
  58     exeStatus = Running;
  59     wbStatus = Idle;
  60
  61     // Setup wire to read instructions coming from issue.
  62     fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
  63
  64     // Instruction queue needs the queue between issue and execute.
  65     instQueue.setIssueToExecuteQueue(&issueToExecQueue);
  66
  67     instQueue.setIEW(this);
  68     ldstQueue.setIEW(this);
  69
  70     for (int i=0; i < numThreads; i++) {
  71         dispatchStatus[i] = Running;
  72         stalls[i].commit = false;
  73         fetchRedirect[i] = false;
  74         bdelayDoneSeqNum[i] = 0;
  75     }
  76
  77     wbMax = wbWidth * params->wbDepth;
  78
  79     updateLSQNextCycle = false;
  80
  81     ableToIssue = true;
  82
  83     skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
  84 }
  85
  86 template <class Impl>
  87 std::string
  88 DefaultIEW<Impl>::name() const
  89 {
  90     return cpu->name() + ".iew";
  91 }
  92
  93 template <class Impl>
  94 void
  95 DefaultIEW<Impl>::regStats()
  96 {
  97     using namespace Stats;
  98
  99     instQueue.regStats();
 100     ldstQueue.regStats();
 101
 102     iewIdleCycles
 103         .name(name() + ".iewIdleCycles")
 104         .desc("Number of cycles IEW is idle");
 105
 106     iewSquashCycles
 107         .name(name() + ".iewSquashCycles")
 108         .desc("Number of cycles IEW is squashing");
 109
 110     iewBlockCycles
 111         .name(name() + ".iewBlockCycles")
 112         .desc("Number of cycles IEW is blocking");
 113
 114     iewUnblockCycles
 115         .name(name() + ".iewUnblockCycles")
 116         .desc("Number of cycles IEW is unblocking");
 117
 118     iewDispatchedInsts
 119         .name(name() + ".iewDispatchedInsts")
 120         .desc("Number of instructions dispatched to IQ");
 121
 122     iewDispSquashedInsts
 123         .name(name() + ".iewDispSquashedInsts")
 124         .desc("Number of squashed instructions skipped by dispatch");
 125
 126     iewDispLoadInsts
 127         .name(name() + ".iewDispLoadInsts")
 128         .desc("Number of dispatched load instructions");
 129
 130     iewDispStoreInsts
 131         .name(name() + ".iewDispStoreInsts")
 132         .desc("Number of dispatched store instructions");
 133
 134     iewDispNonSpecInsts
 135         .name(name() + ".iewDispNonSpecInsts")
 136         .desc("Number of dispatched non-speculative instructions");
 137
 138     iewIQFullEvents
 139         .name(name() + ".iewIQFullEvents")
 140         .desc("Number of times the IQ has become full, causing a stall");
 141
 142     iewLSQFullEvents
 143         .name(name() + ".iewLSQFullEvents")
 144         .desc("Number of times the LSQ has become full, causing a stall");
 145
 146     memOrderViolationEvents
 147         .name(name() + ".memOrderViolationEvents")
 148         .desc("Number of memory order violations");
 149
 150     predictedTakenIncorrect
 151         .name(name() + ".predictedTakenIncorrect")
 152         .desc("Number of branches that were predicted taken incorrectly");
 153
 154     predictedNotTakenIncorrect
 155         .name(name() + ".predictedNotTakenIncorrect")
 156         .desc("Number of branches that were predicted not taken incorrectly");
 157
 158     branchMispredicts
 159         .name(name() + ".branchMispredicts")
 160         .desc("Number of branch mispredicts detected at execute");
 161
 162     branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
 163
 164     iewExecutedInsts
 165         .name(name() + ".EXEC:insts")
 166         .desc("Number of executed instructions");
 167
 168     iewExecLoadInsts
 169         .init(cpu->number_of_threads)
 170         .name(name() + ".EXEC:loads")
 171         .desc("Number of load instructions executed")
 172         .flags(total);
 173
 174     iewExecSquashedInsts
 175         .name(name() + ".EXEC:squashedInsts")
 176         .desc("Number of squashed instructions skipped in execute");
 177
 178     iewExecutedSwp
 179         .init(cpu->number_of_threads)
 180         .name(name() + ".EXEC:swp")
 181         .desc("number of swp insts executed")
 182         .flags(total);
 183
 184     iewExecutedNop
 185         .init(cpu->number_of_threads)
 186         .name(name() + ".EXEC:nop")
 187         .desc("number of nop insts executed")
 188         .flags(total);
 189
 190     iewExecutedRefs
 191         .init(cpu->number_of_threads)
 192         .name(name() + ".EXEC:refs")
 193         .desc("number of memory reference insts executed")
 194         .flags(total);
 195
 196     iewExecutedBranches
 197         .init(cpu->number_of_threads)
 198         .name(name() + ".EXEC:branches")
 199         .desc("Number of branches executed")
 200         .flags(total);
 201
 202     iewExecStoreInsts
 203         .name(name() + ".EXEC:stores")
 204         .desc("Number of stores executed")
 205         .flags(total);
 206     iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
 207
 208     iewExecRate
 209         .name(name() + ".EXEC:rate")
 210         .desc("Inst execution rate")
 211         .flags(total);
 212
 213     iewExecRate = iewExecutedInsts / cpu->numCycles;
 214
 215     iewInstsToCommit
 216         .init(cpu->number_of_threads)
 217         .name(name() + ".WB:sent")
 218         .desc("cumulative count of insts sent to commit")
 219         .flags(total);
 220
 221     writebackCount
 222         .init(cpu->number_of_threads)
 223         .name(name() + ".WB:count")
 224         .desc("cumulative count of insts written-back")
 225         .flags(total);
 226
 227     producerInst
 228         .init(cpu->number_of_threads)
 229         .name(name() + ".WB:producers")
 230         .desc("num instructions producing a value")
 231         .flags(total);
 232
 233     consumerInst
 234         .init(cpu->number_of_threads)
 235         .name(name() + ".WB:consumers")
 236         .desc("num instructions consuming a value")
 237         .flags(total);
 238
 239     wbPenalized
 240         .init(cpu->number_of_threads)
 241         .name(name() + ".WB:penalized")
 242         .desc("number of instrctions required to write to 'other' IQ")
 243         .flags(total);
 244
 245     wbPenalizedRate
 246         .name(name() + ".WB:penalized_rate")
 247         .desc ("fraction of instructions written-back that wrote to 'other' IQ")
 248         .flags(total);
 249
 250     wbPenalizedRate = wbPenalized / writebackCount;
 251
 252     wbFanout
 253         .name(name() + ".WB:fanout")
 254         .desc("average fanout of values written-back")
 255         .flags(total);
 256
 257     wbFanout = producerInst / consumerInst;
 258
 259     wbRate
 260         .name(name() + ".WB:rate")
 261         .desc("insts written-back per cycle")
 262         .flags(total);
 263     wbRate = writebackCount / cpu->numCycles;
 264 }
 265
 266 template<class Impl>
 267 void
 268 DefaultIEW<Impl>::initStage()
 269 {
 270     for (int tid=0; tid < numThreads; tid++) {
 271         toRename->iewInfo[tid].usedIQ = true;
 272         toRename->iewInfo[tid].freeIQEntries =
 273             instQueue.numFreeEntries(tid);
 274
 275         toRename->iewInfo[tid].usedLSQ = true;
 276         toRename->iewInfo[tid].freeLSQEntries =
 277             ldstQueue.numFreeEntries(tid);
 278     }
 279 }
 280
 281 template<class Impl>
 282 void
 283 DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
 284 {
 285     DPRINTF(IEW, "Setting CPU pointer.\n");
 286     cpu = cpu_ptr;
 287
 288     instQueue.setCPU(cpu_ptr);
 289     ldstQueue.setCPU(cpu_ptr);
 290
 291     cpu->activateStage(O3CPU::IEWIdx);
 292 }
 293
 294 template<class Impl>
 295 void
 296 DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 297 {
 298     DPRINTF(IEW, "Setting time buffer pointer.\n");
 299     timeBuffer = tb_ptr;
 300
 301     // Setup wire to read information from time buffer, from commit.
 302     fromCommit = timeBuffer->getWire(-commitToIEWDelay);
 303
 304     // Setup wire to write information back to previous stages.
 305     toRename = timeBuffer->getWire(0);
 306
 307     toFetch = timeBuffer->getWire(0);
 308
 309     // Instruction queue also needs main time buffer.
 310     instQueue.setTimeBuffer(tb_ptr);
 311 }
 312
 313 template<class Impl>
 314 void
 315 DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 316 {
 317     DPRINTF(IEW, "Setting rename queue pointer.\n");
 318     renameQueue = rq_ptr;
 319
 320     // Setup wire to read information from rename queue.
 321     fromRename = renameQueue->getWire(-renameToIEWDelay);
 322 }
 323
 324 template<class Impl>
 325 void
 326 DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 327 {
 328     DPRINTF(IEW, "Setting IEW queue pointer.\n");
 329     iewQueue = iq_ptr;
 330
 331     // Setup wire to write instructions to commit.
 332     toCommit = iewQueue->getWire(0);
 333 }
 334
 335 template<class Impl>
 336 void
 337 DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 338 {
 339     DPRINTF(IEW, "Setting active threads list pointer.\n");
 340     activeThreads = at_ptr;
 341
 342     ldstQueue.setActiveThreads(at_ptr);
 343     instQueue.setActiveThreads(at_ptr);
 344 }
 345
 346 template<class Impl>
 347 void
 348 DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
 349 {
 350     DPRINTF(IEW, "Setting scoreboard pointer.\n");
 351     scoreboard = sb_ptr;
 352 }
 353
 354 template <class Impl>
 355 bool
 356 DefaultIEW<Impl>::drain()
 357 {
 358     // IEW is ready to drain at any time.
 359     cpu->signalDrained();
 360     return true;
 361 }
 362
 363 template <class Impl>
 364 void
 365 DefaultIEW<Impl>::resume()
 366 {
 367 }
 368
 369 template <class Impl>
 370 void
 371 DefaultIEW<Impl>::switchOut()
 372 {
 373     // Clear any state.
 374     switchedOut = true;
 375
 376     instQueue.switchOut();
 377     ldstQueue.switchOut();
 378     fuPool->switchOut();
 379
 380     for (int i = 0; i < numThreads; i++) {
 381         while (!insts[i].empty())
 382             insts[i].pop();
 383         while (!skidBuffer[i].empty())
 384             skidBuffer[i].pop();
 385     }
 386 }
 387
 388 template <class Impl>
 389 void
 390 DefaultIEW<Impl>::takeOverFrom()
 391 {
 392     // Reset all state.
 393     _status = Active;
 394     exeStatus = Running;
 395     wbStatus = Idle;
 396     switchedOut = false;
 397
 398     instQueue.takeOverFrom();
 399     ldstQueue.takeOverFrom();
 400     fuPool->takeOverFrom();
 401
 402     initStage();
 403     cpu->activityThisCycle();
 404
 405     for (int i=0; i < numThreads; i++) {
 406         dispatchStatus[i] = Running;
 407         stalls[i].commit = false;
 408         fetchRedirect[i] = false;
 409     }
 410
 411     updateLSQNextCycle = false;
 412
 413     // @todo: Fix hardcoded number
 414     for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
 415         issueToExecQueue.advance();
 416     }
 417 }
 418
 419 template<class Impl>
 420 void
 421 DefaultIEW<Impl>::squash(unsigned tid)
 422 {
 423     DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
 424             tid);
 425
 426     // Tell the IQ to start squashing.
 427     instQueue.squash(tid);
 428
 429     // Tell the LDSTQ to start squashing.
 430 #if ISA_HAS_DELAY_SLOT
 431     ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
 432 #else
 433     ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
 434 #endif
 435     updatedQueues = true;
 436
 437     // Clear the skid buffer in case it has any data in it.
 438     DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
 439             tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
 440
 441     while (!skidBuffer[tid].empty()) {
 442 #if ISA_HAS_DELAY_SLOT
 443         if (skidBuffer[tid].front()->seqNum <=
 444             fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
 445             DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
 446                     "that occur before delay slot [sn:%i].\n",
 447                     fromCommit->commitInfo[tid].bdelayDoneSeqNum,
 448                     tid);
 449             break;
 450         } else {
 451             DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
 452                     "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
 453         }
 454 #endif
 455         if (skidBuffer[tid].front()->isLoad() ||
 456             skidBuffer[tid].front()->isStore() ) {
 457             toRename->iewInfo[tid].dispatchedToLSQ++;
 458         }
 459
 460         toRename->iewInfo[tid].dispatched++;
 461
 462         skidBuffer[tid].pop();
 463     }
 464
 465     bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
 466
 467     emptyRenameInsts(tid);
 468 }
 469
 470 template<class Impl>
 471 void
 472 DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
 473 {
 474     DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
 475             "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
 476
 477     toCommit->squash[tid] = true;
 478     toCommit->squashedSeqNum[tid] = inst->seqNum;
 479     toCommit->mispredPC[tid] = inst->readPC();
 480     toCommit->branchMispredict[tid] = true;
 481
 482 #if ISA_HAS_DELAY_SLOT
 483     bool branch_taken = inst->readNextNPC() !=
 484         (inst->readNextPC() + sizeof(TheISA::MachInst));
 485
 486     toCommit->branchTaken[tid] = branch_taken;
 487
 488     toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
 489
 490     if (inst->isCondDelaySlot() && branch_taken) {
 491         toCommit->nextPC[tid] = inst->readNextPC();
 492     } else {
 493         toCommit->nextPC[tid] = inst->readNextNPC();
 494     }
 495 #else
 496     toCommit->branchTaken[tid] = inst->readNextPC() !=
 497         (inst->readPC() + sizeof(TheISA::MachInst));
 498     toCommit->nextPC[tid] = inst->readNextPC();
 499 #endif
 500
 501     toCommit->includeSquashInst[tid] = false;
 502
 503     wroteToTimeBuffer = true;
 504 }
 505
 506 template<class Impl>
 507 void
 508 DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
 509 {
 510     DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
 511             "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
 512
 513     toCommit->squash[tid] = true;
 514     toCommit->squashedSeqNum[tid] = inst->seqNum;
 515     toCommit->nextPC[tid] = inst->readNextPC();
 516
 517     toCommit->includeSquashInst[tid] = false;
 518
 519     wroteToTimeBuffer = true;
 520 }
 521
 522 template<class Impl>
 523 void
 524 DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
 525 {
 526     DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
 527             "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
 528
 529     toCommit->squash[tid] = true;
 530     toCommit->squashedSeqNum[tid] = inst->seqNum;
 531     toCommit->nextPC[tid] = inst->readPC();
 532
 533     // Must include the broadcasted SN in the squash.
 534     toCommit->includeSquashInst[tid] = true;
 535
 536     ldstQueue.setLoadBlockedHandled(tid);
 537
 538     wroteToTimeBuffer = true;
 539 }
 540
 541 template<class Impl>
 542 void
 543 DefaultIEW<Impl>::block(unsigned tid)
 544 {
 545     DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
 546
 547     if (dispatchStatus[tid] != Blocked &&
 548         dispatchStatus[tid] != Unblocking) {
 549         toRename->iewBlock[tid] = true;
 550         wroteToTimeBuffer = true;
 551     }
 552
 553     // Add the current inputs to the skid buffer so they can be
 554     // reprocessed when this stage unblocks.
 555     skidInsert(tid);
 556
 557     dispatchStatus[tid] = Blocked;
 558 }
 559
 560 template<class Impl>
 561 void
 562 DefaultIEW<Impl>::unblock(unsigned tid)
 563 {
 564     DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
 565             "buffer %u.\n",tid, tid);
 566
 567     // If the skid bufffer is empty, signal back to previous stages to unblock.
 568     // Also switch status to running.
 569     if (skidBuffer[tid].empty()) {
 570         toRename->iewUnblock[tid] = true;
 571         wroteToTimeBuffer = true;
 572         DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
 573         dispatchStatus[tid] = Running;
 574     }
 575 }
 576
 577 template<class Impl>
 578 void
 579 DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
 580 {
 581     instQueue.wakeDependents(inst);
 582 }
 583
 584 template<class Impl>
 585 void
 586 DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
 587 {
 588     instQueue.rescheduleMemInst(inst);
 589 }
 590
 591 template<class Impl>
 592 void
 593 DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
 594 {
 595     instQueue.replayMemInst(inst);
 596 }
 597
 598 template<class Impl>
 599 void
 600 DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
 601 {
 602     // First check the time slot that this instruction will write
 603     // to.  If there are free write ports at the time, then go ahead
 604     // and write the instruction to that time.  If there are not,
 605     // keep looking back to see where's the first time there's a
 606     // free slot.
 607     while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
 608         ++wbNumInst;
 609         if (wbNumInst == wbWidth) {
 610             ++wbCycle;
 611             wbNumInst = 0;
 612         }
 613
 614         assert((wbCycle * wbWidth + wbNumInst) < wbMax);
 615     }
 616
 617     // Add finished instruction to queue to commit.
 618     (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
 619     (*iewQueue)[wbCycle].size++;
 620 }
 621
 622 template <class Impl>
 623 unsigned
 624 DefaultIEW<Impl>::validInstsFromRename()
 625 {
 626     unsigned inst_count = 0;
 627
 628     for (int i=0; i<fromRename->size; i++) {
 629         if (!fromRename->insts[i]->isSquashed())
 630             inst_count++;
 631     }
 632
 633     return inst_count;
 634 }
 635
 636 template<class Impl>
 637 void
 638 DefaultIEW<Impl>::skidInsert(unsigned tid)
 639 {
 640     DynInstPtr inst = NULL;
 641
 642     while (!insts[tid].empty()) {
 643         inst = insts[tid].front();
 644
 645         insts[tid].pop();
 646
 647         DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
 648                 "dispatch skidBuffer %i\n",tid, inst->seqNum,
 649                 inst->readPC(),tid);
 650
 651         skidBuffer[tid].push(inst);
 652     }
 653
 654     assert(skidBuffer[tid].size() <= skidBufferMax &&
 655            "Skidbuffer Exceeded Max Size");
 656 }
 657
 658 template<class Impl>
 659 int
 660 DefaultIEW<Impl>::skidCount()
 661 {
 662     int max=0;
 663
 664     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 665
 666     while (threads != (*activeThreads).end()) {
 667         unsigned thread_count = skidBuffer[*threads++].size();
 668         if (max < thread_count)
 669             max = thread_count;
 670     }
 671
 672     return max;
 673 }
 674
 675 template<class Impl>
 676 bool
 677 DefaultIEW<Impl>::skidsEmpty()
 678 {
 679     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 680
 681     while (threads != (*activeThreads).end()) {
 682         if (!skidBuffer[*threads++].empty())
 683             return false;
 684     }
 685
 686     return true;
 687 }
 688
 689 template <class Impl>
 690 void
 691 DefaultIEW<Impl>::updateStatus()
 692 {
 693     bool any_unblocking = false;
 694
 695     std::list<unsigned>::iterator threads = (*activeThreads).begin();
 696
 697     threads = (*activeThreads).begin();
 698
 699     while (threads != (*activeThreads).end()) {
 700         unsigned tid = *threads++;
 701
 702         if (dispatchStatus[tid] == Unblocking) {
 703             any_unblocking = true;
 704             break;
 705         }
 706     }
 707
 708     // If there are no ready instructions waiting to be scheduled by the IQ,
 709     // and there's no stores waiting to write back, and dispatch is not
 710     // unblocking, then there is no internal activity for the IEW stage.
 711     if (_status == Active && !instQueue.hasReadyInsts() &&
 712         !ldstQueue.willWB() && !any_unblocking) {
 713         DPRINTF(IEW, "IEW switching to idle\n");
 714
 715         deactivateStage();
 716
 717         _status = Inactive;
 718     } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
 719                                        ldstQueue.willWB() ||
 720                                        any_unblocking)) {
 721         // Otherwise there is internal activity.  Set to active.
 722         DPRINTF(IEW, "IEW switching to active\n");
 723
 724         activateStage();
 725
 726         _status = Active;
 727     }
 728 }
 729
 730 template <class Impl>
 731 void
 732 DefaultIEW<Impl>::resetEntries()
 733 {
 734     instQueue.resetEntries();
 735     ldstQueue.resetEntries();
 736 }
 737
 738 template <class Impl>
 739 void
 740 DefaultIEW<Impl>::readStallSignals(unsigned tid)
 741 {
 742     if (fromCommit->commitBlock[tid]) {
 743         stalls[tid].commit = true;
 744     }
 745
 746     if (fromCommit->commitUnblock[tid]) {
 747         assert(stalls[tid].commit);
 748         stalls[tid].commit = false;
 749     }
 750 }
 751
 752 template <class Impl>
 753 bool
 754 DefaultIEW<Impl>::checkStall(unsigned tid)
 755 {
 756     bool ret_val(false);
 757
 758     if (stalls[tid].commit) {
 759         DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
 760         ret_val = true;
 761     } else if (instQueue.isFull(tid)) {
 762         DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
 763         ret_val = true;
 764     } else if (ldstQueue.isFull(tid)) {
 765         DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
 766
 767         if (ldstQueue.numLoads(tid) > 0 ) {
 768
 769             DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
 770                     tid,ldstQueue.getLoadHeadSeqNum(tid));
 771         }
 772
 773         if (ldstQueue.numStores(tid) > 0) {
 774
 775             DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
 776                     tid,ldstQueue.getStoreHeadSeqNum(tid));
 777         }
 778
 779         ret_val = true;
 780     } else if (ldstQueue.isStalled(tid)) {
 781         DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
 782         ret_val = true;
 783     }
 784
 785     return ret_val;
 786 }
 787
 788 template <class Impl>
 789 void
 790 DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
 791 {
 792     // Check if there's a squash signal, squash if there is
 793     // Check stall signals, block if there is.
 794     // If status was Blocked
 795     //     if so then go to unblocking
 796     // If status was Squashing
 797     //     check if squashing is not high.  Switch to running this cycle.
 798
 799     readStallSignals(tid);
 800
 801     if (fromCommit->commitInfo[tid].squash) {
 802         squash(tid);
 803
 804         if (dispatchStatus[tid] == Blocked ||
 805             dispatchStatus[tid] == Unblocking) {
 806             toRename->iewUnblock[tid] = true;
 807             wroteToTimeBuffer = true;
 808         }
 809
 810         dispatchStatus[tid] = Squashing;
 811
 812         fetchRedirect[tid] = false;
 813         return;
 814     }
 815
 816     if (fromCommit->commitInfo[tid].robSquashing) {
 817         DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
 818
 819         dispatchStatus[tid] = Squashing;
 820
 821         emptyRenameInsts(tid);
 822         wroteToTimeBuffer = true;
 823         return;
 824     }
 825
 826     if (checkStall(tid)) {
 827         block(tid);
 828         dispatchStatus[tid] = Blocked;
 829         return;
 830     }
 831
 832     if (dispatchStatus[tid] == Blocked) {
 833         // Status from previous cycle was blocked, but there are no more stall
 834         // conditions.  Switch over to unblocking.
 835         DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
 836                 tid);
 837
 838         dispatchStatus[tid] = Unblocking;
 839
 840         unblock(tid);
 841
 842         return;
 843     }
 844
 845     if (dispatchStatus[tid] == Squashing) {
 846         // Switch status to running if rename isn't being told to block or
 847         // squash this cycle.
 848         DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
 849                 tid);
 850
 851         dispatchStatus[tid] = Running;
 852
 853         return;
 854     }
 855 }
 856
 857 template <class Impl>
 858 void
 859 DefaultIEW<Impl>::sortInsts()
 860 {
 861     int insts_from_rename = fromRename->size;
 862 #ifdef DEBUG
 863 #if !ISA_HAS_DELAY_SLOT
 864     for (int i = 0; i < numThreads; i++)
 865         assert(insts[i].empty());
 866 #endif
 867 #endif
 868     for (int i = 0; i < insts_from_rename; ++i) {
 869         insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
 870     }
 871 }
 872
 873 template <class Impl>
 874 void
 875 DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
 876 {
 877     DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
 878             "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
 879
 880     while (!insts[tid].empty()) {
 881 #if ISA_HAS_DELAY_SLOT
 882         if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
 883             DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
 884                     " that occurs at or before delay slot [sn:%i].\n",
 885                     tid, bdelayDoneSeqNum[tid]);
 886             break;
 887         } else {
 888             DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
 889                     "[sn:%i].\n", tid, insts[tid].front()->seqNum);
 890         }
 891 #endif
 892
 893         if (insts[tid].front()->isLoad() ||
 894             insts[tid].front()->isStore() ) {
 895             toRename->iewInfo[tid].dispatchedToLSQ++;
 896         }
 897
 898         toRename->iewInfo[tid].dispatched++;
 899
 900         insts[tid].pop();
 901     }
 902 }
 903
 904 template <class Impl>
 905 void
 906 DefaultIEW<Impl>::wakeCPU()
 907 {
 908     cpu->wakeCPU();
 909 }
 910
 911 template <class Impl>
 912 void
 913 DefaultIEW<Impl>::activityThisCycle()
 914 {
 915     DPRINTF(Activity, "Activity this cycle.\n");
 916     cpu->activityThisCycle();
 917 }
 918
 919 template <class Impl>
 920 inline void
 921 DefaultIEW<Impl>::activateStage()
 922 {
 923     DPRINTF(Activity, "Activating stage.\n");
 924     cpu->activateStage(O3CPU::IEWIdx);
 925 }
 926
 927 template <class Impl>
 928 inline void
 929 DefaultIEW<Impl>::deactivateStage()
 930 {
 931     DPRINTF(Activity, "Deactivating stage.\n");
 932     cpu->deactivateStage(O3CPU::IEWIdx);
 933 }
 934
 935 template<class Impl>
 936 void
 937 DefaultIEW<Impl>::dispatch(unsigned tid)
 938 {
 939     // If status is Running or idle,
 940     //     call dispatchInsts()
 941     // If status is Unblocking,
 942     //     buffer any instructions coming from rename
 943     //     continue trying to empty skid buffer
 944     //     check if stall conditions have passed
 945
 946     if (dispatchStatus[tid] == Blocked) {
 947         ++iewBlockCycles;
 948
 949     } else if (dispatchStatus[tid] == Squashing) {
 950         ++iewSquashCycles;
 951     }
 952
 953     // Dispatch should try to dispatch as many instructions as its bandwidth
 954     // will allow, as long as it is not currently blocked.
 955     if (dispatchStatus[tid] == Running ||
 956         dispatchStatus[tid] == Idle) {
 957         DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
 958                 "dispatch.\n", tid);
 959
 960         dispatchInsts(tid);
 961     } else if (dispatchStatus[tid] == Unblocking) {
 962         // Make sure that the skid buffer has something in it if the
 963         // status is unblocking.
 964         assert(!skidsEmpty());
 965
 966         // If the status was unblocking, then instructions from the skid
 967         // buffer were used.  Remove those instructions and handle
 968         // the rest of unblocking.
 969         dispatchInsts(tid);
 970
 971         ++iewUnblockCycles;
 972
 973         if (validInstsFromRename() && dispatchedAllInsts) {
 974             // Add the current inputs to the skid buffer so they can be
 975             // reprocessed when this stage unblocks.
 976             skidInsert(tid);
 977         }
 978
 979         unblock(tid);
 980     }
 981 }
 982
 983 template <class Impl>
 984 void
 985 DefaultIEW<Impl>::dispatchInsts(unsigned tid)
 986 {
 987     dispatchedAllInsts = true;
 988
 989     // Obtain instructions from skid buffer if unblocking, or queue from rename
 990     // otherwise.
 991     std::queue<DynInstPtr> &insts_to_dispatch =
 992         dispatchStatus[tid] == Unblocking ?
 993         skidBuffer[tid] : insts[tid];
 994
 995     int insts_to_add = insts_to_dispatch.size();
 996
 997     DynInstPtr inst;
 998     bool add_to_iq = false;
 999     int dis_num_inst = 0;
1000
1001     // Loop through the instructions, putting them in the instruction
1002     // queue.
1003     for ( ; dis_num_inst < insts_to_add &&
1004               dis_num_inst < dispatchWidth;
1005           ++dis_num_inst)
1006     {
1007         inst = insts_to_dispatch.front();
1008
1009         if (dispatchStatus[tid] == Unblocking) {
1010             DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1011                     "buffer\n", tid);
1012         }
1013
1014         // Make sure there's a valid instruction there.
1015         assert(inst);
1016
1017         DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1018                 "IQ.\n",
1019                 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1020
1021         // Be sure to mark these instructions as ready so that the
1022         // commit stage can go ahead and execute them, and mark
1023         // them as issued so the IQ doesn't reprocess them.
1024
1025         // Check for squashed instructions.
1026         if (inst->isSquashed()) {
1027             DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1028                     "not adding to IQ.\n", tid);
1029
1030             ++iewDispSquashedInsts;
1031
1032             insts_to_dispatch.pop();
1033
1034             //Tell Rename That An Instruction has been processed
1035             if (inst->isLoad() || inst->isStore()) {
1036                 toRename->iewInfo[tid].dispatchedToLSQ++;
1037             }
1038             toRename->iewInfo[tid].dispatched++;
1039
1040             continue;
1041         }
1042
1043         // Check for full conditions.
1044         if (instQueue.isFull(tid)) {
1045             DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1046
1047             // Call function to start blocking.
1048             block(tid);
1049
1050             // Set unblock to false. Special case where we are using
1051             // skidbuffer (unblocking) instructions but then we still
1052             // get full in the IQ.
1053             toRename->iewUnblock[tid] = false;
1054
1055             dispatchedAllInsts = false;
1056
1057             ++iewIQFullEvents;
1058             break;
1059         } else if (ldstQueue.isFull(tid)) {
1060             DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1061
1062             // Call function to start blocking.
1063             block(tid);
1064
1065             // Set unblock to false. Special case where we are using
1066             // skidbuffer (unblocking) instructions but then we still
1067             // get full in the IQ.
1068             toRename->iewUnblock[tid] = false;
1069
1070             dispatchedAllInsts = false;
1071
1072             ++iewLSQFullEvents;
1073             break;
1074         }
1075
1076         // Otherwise issue the instruction just fine.
1077         if (inst->isLoad()) {
1078             DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1079                     "encountered, adding to LSQ.\n", tid);
1080
1081             // Reserve a spot in the load store queue for this
1082             // memory access.
1083             ldstQueue.insertLoad(inst);
1084
1085             ++iewDispLoadInsts;
1086
1087             add_to_iq = true;
1088
1089             toRename->iewInfo[tid].dispatchedToLSQ++;
1090         } else if (inst->isStore()) {
1091             DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1092                     "encountered, adding to LSQ.\n", tid);
1093
1094             ldstQueue.insertStore(inst);
1095
1096             ++iewDispStoreInsts;
1097
1098             if (inst->isStoreConditional()) {
1099                 // Store conditionals need to be set as "canCommit()"
1100                 // so that commit can process them when they reach the
1101                 // head of commit.
1102                 // @todo: This is somewhat specific to Alpha.
1103                 inst->setCanCommit();
1104                 instQueue.insertNonSpec(inst);
1105                 add_to_iq = false;
1106
1107                 ++iewDispNonSpecInsts;
1108             } else {
1109                 add_to_iq = true;
1110             }
1111
1112             toRename->iewInfo[tid].dispatchedToLSQ++;
1113 #if FULL_SYSTEM
1114         } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1115             // Same as non-speculative stores.
1116             inst->setCanCommit();
1117             instQueue.insertBarrier(inst);
1118             add_to_iq = false;
1119 #endif
1120         } else if (inst->isNonSpeculative()) {
1121             DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1122                     "encountered, skipping.\n", tid);
1123
1124             // Same as non-speculative stores.
1125             inst->setCanCommit();
1126
1127             // Specifically insert it as nonspeculative.
1128             instQueue.insertNonSpec(inst);
1129
1130             ++iewDispNonSpecInsts;
1131
1132             add_to_iq = false;
1133         } else if (inst->isNop()) {
1134             DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1135                     "skipping.\n", tid);
1136
1137             inst->setIssued();
1138             inst->setExecuted();
1139             inst->setCanCommit();
1140
1141             instQueue.recordProducer(inst);
1142
1143             iewExecutedNop[tid]++;
1144
1145             add_to_iq = false;
1146         } else if (inst->isExecuted()) {
1147             assert(0 && "Instruction shouldn't be executed.\n");
1148             DPRINTF(IEW, "Issue: Executed branch encountered, "
1149                     "skipping.\n");
1150
1151             inst->setIssued();
1152             inst->setCanCommit();
1153
1154             instQueue.recordProducer(inst);
1155
1156             add_to_iq = false;
1157         } else {
1158             add_to_iq = true;
1159         }
1160
1161         // If the instruction queue is not full, then add the
1162         // instruction.
1163         if (add_to_iq) {
1164             instQueue.insert(inst);
1165         }
1166
1167         insts_to_dispatch.pop();
1168
1169         toRename->iewInfo[tid].dispatched++;
1170
1171         ++iewDispatchedInsts;
1172     }
1173
1174     if (!insts_to_dispatch.empty()) {
1175         DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1176         block(tid);
1177         toRename->iewUnblock[tid] = false;
1178     }
1179
1180     if (dispatchStatus[tid] == Idle && dis_num_inst) {
1181         dispatchStatus[tid] = Running;
1182
1183         updatedQueues = true;
1184     }
1185
1186     dis_num_inst = 0;
1187 }
1188
1189 template <class Impl>
1190 void
1191 DefaultIEW<Impl>::printAvailableInsts()
1192 {
1193     int inst = 0;
1194
1195     std::cout << "Available Instructions: ";
1196
1197     while (fromIssue->insts[inst]) {
1198
1199         if (inst%3==0) std::cout << "\n\t";
1200
1201         std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1202              << " TN: " << fromIssue->insts[inst]->threadNumber
1203              << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1204
1205         inst++;
1206
1207     }
1208
1209     std::cout << "\n";
1210 }
1211
1212 template <class Impl>
1213 void
1214 DefaultIEW<Impl>::executeInsts()
1215 {
1216     wbNumInst = 0;
1217     wbCycle = 0;
1218
1219     std::list<unsigned>::iterator threads = (*activeThreads).begin();
1220
1221     while (threads != (*activeThreads).end()) {
1222         unsigned tid = *threads++;
1223         fetchRedirect[tid] = false;
1224     }
1225
1226     // Uncomment this if you want to see all available instructions.
1227 //    printAvailableInsts();
1228
1229     // Execute/writeback any instructions that are available.
1230     int insts_to_execute = fromIssue->size;
1231     int inst_num = 0;
1232     for (; inst_num < insts_to_execute;
1233           ++inst_num) {
1234
1235         DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1236
1237         DynInstPtr inst = instQueue.getInstToExecute();
1238
1239         DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1240                 inst->readPC(), inst->threadNumber,inst->seqNum);
1241
1242         // Check if the instruction is squashed; if so then skip it
1243         if (inst->isSquashed()) {
1244             DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1245
1246             // Consider this instruction executed so that commit can go
1247             // ahead and retire the instruction.
1248             inst->setExecuted();
1249
1250             // Not sure if I should set this here or just let commit try to
1251             // commit any squashed instructions.  I like the latter a bit more.
1252             inst->setCanCommit();
1253
1254             ++iewExecSquashedInsts;
1255
1256             decrWb(inst->seqNum);
1257             continue;
1258         }
1259
1260         Fault fault = NoFault;
1261
1262         // Execute instruction.
1263         // Note that if the instruction faults, it will be handled
1264         // at the commit stage.
1265         if (inst->isMemRef() &&
1266             (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1267             DPRINTF(IEW, "Execute: Calculating address for memory "
1268                     "reference.\n");
1269
1270             // Tell the LDSTQ to execute this instruction (if it is a load).
1271             if (inst->isLoad()) {
1272                 // Loads will mark themselves as executed, and their writeback
1273                 // event adds the instruction to the queue to commit
1274                 fault = ldstQueue.executeLoad(inst);
1275             } else if (inst->isStore()) {
1276                 ldstQueue.executeStore(inst);
1277
1278                 // If the store had a fault then it may not have a mem req
1279                 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1280                     inst->setExecuted();
1281
1282                     instToCommit(inst);
1283                 }
1284
1285                 // Store conditionals will mark themselves as
1286                 // executed, and their writeback event will add the
1287                 // instruction to the queue to commit.
1288             } else {
1289                 panic("Unexpected memory type!\n");
1290             }
1291
1292         } else {
1293             inst->execute();
1294
1295             inst->setExecuted();
1296
1297             instToCommit(inst);
1298         }
1299
1300         updateExeInstStats(inst);
1301
1302         // Check if branch prediction was correct, if not then we need
1303         // to tell commit to squash in flight instructions.  Only
1304         // handle this if there hasn't already been something that
1305         // redirects fetch in this group of instructions.
1306
1307         // This probably needs to prioritize the redirects if a different
1308         // scheduler is used.  Currently the scheduler schedules the oldest
1309         // instruction first, so the branch resolution order will be correct.
1310         unsigned tid = inst->threadNumber;
1311
1312         if (!fetchRedirect[tid]) {
1313
1314             if (inst->mispredicted()) {
1315                 fetchRedirect[tid] = true;
1316
1317                 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1318 #if ISA_HAS_DELAY_SLOT
1319                 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1320                         inst->nextNPC);
1321 #else
1322                 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1323                         inst->nextPC);
1324 #endif
1325                 // If incorrect, then signal the ROB that it must be squashed.
1326                 squashDueToBranch(inst, tid);
1327
1328                 if (inst->predTaken()) {
1329                     predictedTakenIncorrect++;
1330                 } else {
1331                     predictedNotTakenIncorrect++;
1332                 }
1333             } else if (ldstQueue.violation(tid)) {
1334                 fetchRedirect[tid] = true;
1335
1336                 // If there was an ordering violation, then get the
1337                 // DynInst that caused the violation.  Note that this
1338                 // clears the violation signal.
1339                 DynInstPtr violator;
1340                 violator = ldstQueue.getMemDepViolator(tid);
1341
1342                 DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1343                         "%#x, inst PC: %#x.  Addr is: %#x.\n",
1344                         violator->readPC(), inst->readPC(), inst->physEffAddr);
1345
1346                 // Tell the instruction queue that a violation has occured.
1347                 instQueue.violation(inst, violator);
1348
1349                 // Squash.
1350                 squashDueToMemOrder(inst,tid);
1351
1352                 ++memOrderViolationEvents;
1353             } else if (ldstQueue.loadBlocked(tid) &&
1354                        !ldstQueue.isLoadBlockedHandled(tid)) {
1355                 fetchRedirect[tid] = true;
1356
1357                 DPRINTF(IEW, "Load operation couldn't execute because the "
1358                         "memory system is blocked.  PC: %#x [sn:%lli]\n",
1359                         inst->readPC(), inst->seqNum);
1360
1361                 squashDueToMemBlocked(inst, tid);
1362             }
1363         }
1364     }
1365
1366     // Update and record activity if we processed any instructions.
1367     if (inst_num) {
1368         if (exeStatus == Idle) {
1369             exeStatus = Running;
1370         }
1371
1372         updatedQueues = true;
1373
1374         cpu->activityThisCycle();
1375     }
1376
1377     // Need to reset this in case a writeback event needs to write into the
1378     // iew queue.  That way the writeback event will write into the correct
1379     // spot in the queue.
1380     wbNumInst = 0;
1381 }
1382
1383 template <class Impl>
1384 void
1385 DefaultIEW<Impl>::writebackInsts()
1386 {
1387     // Loop through the head of the time buffer and wake any
1388     // dependents.  These instructions are about to write back.  Also
1389     // mark scoreboard that this instruction is finally complete.
1390     // Either have IEW have direct access to scoreboard, or have this
1391     // as part of backwards communication.
1392     for (int inst_num = 0; inst_num < issueWidth &&
1393              toCommit->insts[inst_num]; inst_num++) {
1394         DynInstPtr inst = toCommit->insts[inst_num];
1395         int tid = inst->threadNumber;
1396
1397         DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1398                 inst->seqNum, inst->readPC());
1399
1400         iewInstsToCommit[tid]++;
1401
1402         // Some instructions will be sent to commit without having
1403         // executed because they need commit to handle them.
1404         // E.g. Uncached loads have not actually executed when they
1405         // are first sent to commit.  Instead commit must tell the LSQ
1406         // when it's ready to execute the uncached load.
1407         if (!inst->isSquashed() && inst->isExecuted()) {
1408             int dependents = instQueue.wakeDependents(inst);
1409
1410             for (int i = 0; i < inst->numDestRegs(); i++) {
1411                 //mark as Ready
1412                 DPRINTF(IEW,"Setting Destination Register %i\n",
1413                         inst->renamedDestRegIdx(i));
1414                 scoreboard->setReg(inst->renamedDestRegIdx(i));
1415             }
1416
1417             if (dependents) {
1418                 producerInst[tid]++;
1419                 consumerInst[tid]+= dependents;
1420             }
1421             writebackCount[tid]++;
1422         }
1423
1424         decrWb(inst->seqNum);
1425     }
1426 }
1427
1428 template<class Impl>
1429 void
1430 DefaultIEW<Impl>::tick()
1431 {
1432     wbNumInst = 0;
1433     wbCycle = 0;
1434
1435     wroteToTimeBuffer = false;
1436     updatedQueues = false;
1437
1438     sortInsts();
1439
1440     // Free function units marked as being freed this cycle.
1441     fuPool->processFreeUnits();
1442
1443     std::list<unsigned>::iterator threads = (*activeThreads).begin();
1444
1445     // Check stall and squash signals, dispatch any instructions.
1446     while (threads != (*activeThreads).end()) {
1447            unsigned tid = *threads++;
1448
1449         DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1450
1451         checkSignalsAndUpdate(tid);
1452         dispatch(tid);
1453     }
1454
1455     if (exeStatus != Squashing) {
1456         executeInsts();
1457
1458         writebackInsts();
1459
1460         // Have the instruction queue try to schedule any ready instructions.
1461         // (In actuality, this scheduling is for instructions that will
1462         // be executed next cycle.)
1463         instQueue.scheduleReadyInsts();
1464
1465         // Also should advance its own time buffers if the stage ran.
1466         // Not the best place for it, but this works (hopefully).
1467         issueToExecQueue.advance();
1468     }
1469
1470     bool broadcast_free_entries = false;
1471
1472     if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1473         exeStatus = Idle;
1474         updateLSQNextCycle = false;
1475
1476         broadcast_free_entries = true;
1477     }
1478
1479     // Writeback any stores using any leftover bandwidth.
1480     ldstQueue.writebackStores();
1481
1482     // Check the committed load/store signals to see if there's a load
1483     // or store to commit.  Also check if it's being told to execute a
1484     // nonspeculative instruction.
1485     // This is pretty inefficient...
1486
1487     threads = (*activeThreads).begin();
1488     while (threads != (*activeThreads).end()) {
1489         unsigned tid = (*threads++);
1490
1491         DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1492
1493         // Update structures based on instructions committed.
1494         if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1495             !fromCommit->commitInfo[tid].squash &&
1496             !fromCommit->commitInfo[tid].robSquashing) {
1497
1498             ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1499
1500             ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1501
1502             updateLSQNextCycle = true;
1503             instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1504         }
1505
1506         if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1507
1508             //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1509             if (fromCommit->commitInfo[tid].uncached) {
1510                 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1511             } else {
1512                 instQueue.scheduleNonSpec(
1513                     fromCommit->commitInfo[tid].nonSpecSeqNum);
1514             }
1515         }
1516
1517         if (broadcast_free_entries) {
1518             toFetch->iewInfo[tid].iqCount =
1519                 instQueue.getCount(tid);
1520             toFetch->iewInfo[tid].ldstqCount =
1521                 ldstQueue.getCount(tid);
1522
1523             toRename->iewInfo[tid].usedIQ = true;
1524             toRename->iewInfo[tid].freeIQEntries =
1525                 instQueue.numFreeEntries();
1526             toRename->iewInfo[tid].usedLSQ = true;
1527             toRename->iewInfo[tid].freeLSQEntries =
1528                 ldstQueue.numFreeEntries(tid);
1529
1530             wroteToTimeBuffer = true;
1531         }
1532
1533         DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1534                 tid, toRename->iewInfo[tid].dispatched);
1535     }
1536
1537     DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1538             "LSQ has %i free entries.\n",
1539             instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1540             ldstQueue.numFreeEntries());
1541
1542     updateStatus();
1543
1544     if (wroteToTimeBuffer) {
1545         DPRINTF(Activity, "Activity this cycle.\n");
1546         cpu->activityThisCycle();
1547     }
1548 }
1549
1550 template <class Impl>
1551 void
1552 DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1553 {
1554     int thread_number = inst->threadNumber;
1555
1556     //
1557     //  Pick off the software prefetches
1558     //
1559 #ifdef TARGET_ALPHA
1560     if (inst->isDataPrefetch())
1561         iewExecutedSwp[thread_number]++;
1562     else
1563         iewIewExecutedcutedInsts++;
1564 #else
1565     iewExecutedInsts++;
1566 #endif
1567
1568     //
1569     //  Control operations
1570     //
1571     if (inst->isControl())
1572         iewExecutedBranches[thread_number]++;
1573
1574     //
1575     //  Memory operations
1576     //
1577     if (inst->isMemRef()) {
1578         iewExecutedRefs[thread_number]++;
1579
1580         if (inst->isLoad()) {
1581             iewExecLoadInsts[thread_number]++;
1582         }
1583     }
1584 }