2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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31 // @todo: Fix the instantaneous communication among all the stages within
32 // iew. There's a clear delay between issue and execute, yet backwards
33 // communication happens simultaneously.
37 #include "base/timebuf.hh"
38 #include "cpu/o3/fu_pool.hh"
39 #include "cpu/o3/iew.hh"
42 DefaultIEW<Impl>::DefaultIEW(Params *params)
43 : issueToExecQueue(params->backComSize, params->forwardComSize),
46 fuPool(params->fuPool),
47 commitToIEWDelay(params->commitToIEWDelay),
48 renameToIEWDelay(params->renameToIEWDelay),
49 issueToExecuteDelay(params->issueToExecuteDelay),
50 dispatchWidth(params->dispatchWidth),
51 issueWidth(params->issueWidth),
53 wbWidth(params->wbWidth),
54 numThreads(params->numberOfThreads),
61 // Setup wire to read instructions coming from issue.
62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
64 // Instruction queue needs the queue between issue and execute.
65 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
67 instQueue.setIEW(this);
68 ldstQueue.setIEW(this);
70 for (int i=0; i < numThreads; i++) {
71 dispatchStatus[i] = Running;
72 stalls[i].commit = false;
73 fetchRedirect[i] = false;
74 bdelayDoneSeqNum[i] = 0;
77 wbMax = wbWidth * params->wbDepth;
79 updateLSQNextCycle = false;
83 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
88 DefaultIEW<Impl>::name() const
90 return cpu->name() + ".iew";
95 DefaultIEW<Impl>::regStats()
97 using namespace Stats;
100 ldstQueue.regStats();
103 .name(name() + ".iewIdleCycles")
104 .desc("Number of cycles IEW is idle");
107 .name(name() + ".iewSquashCycles")
108 .desc("Number of cycles IEW is squashing");
111 .name(name() + ".iewBlockCycles")
112 .desc("Number of cycles IEW is blocking");
115 .name(name() + ".iewUnblockCycles")
116 .desc("Number of cycles IEW is unblocking");
119 .name(name() + ".iewDispatchedInsts")
120 .desc("Number of instructions dispatched to IQ");
123 .name(name() + ".iewDispSquashedInsts")
124 .desc("Number of squashed instructions skipped by dispatch");
127 .name(name() + ".iewDispLoadInsts")
128 .desc("Number of dispatched load instructions");
131 .name(name() + ".iewDispStoreInsts")
132 .desc("Number of dispatched store instructions");
135 .name(name() + ".iewDispNonSpecInsts")
136 .desc("Number of dispatched non-speculative instructions");
139 .name(name() + ".iewIQFullEvents")
140 .desc("Number of times the IQ has become full, causing a stall");
143 .name(name() + ".iewLSQFullEvents")
144 .desc("Number of times the LSQ has become full, causing a stall");
146 memOrderViolationEvents
147 .name(name() + ".memOrderViolationEvents")
148 .desc("Number of memory order violations");
150 predictedTakenIncorrect
151 .name(name() + ".predictedTakenIncorrect")
152 .desc("Number of branches that were predicted taken incorrectly");
154 predictedNotTakenIncorrect
155 .name(name() + ".predictedNotTakenIncorrect")
156 .desc("Number of branches that were predicted not taken incorrectly");
159 .name(name() + ".branchMispredicts")
160 .desc("Number of branch mispredicts detected at execute");
162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
165 .name(name() + ".iewExecutedInsts")
166 .desc("Number of executed instructions");
169 .init(cpu->number_of_threads)
170 .name(name() + ".iewExecLoadInsts")
171 .desc("Number of load instructions executed")
175 .name(name() + ".iewExecSquashedInsts")
176 .desc("Number of squashed instructions skipped in execute");
179 .init(cpu->number_of_threads)
180 .name(name() + ".EXEC:swp")
181 .desc("number of swp insts executed")
185 .init(cpu->number_of_threads)
186 .name(name() + ".EXEC:nop")
187 .desc("number of nop insts executed")
191 .init(cpu->number_of_threads)
192 .name(name() + ".EXEC:refs")
193 .desc("number of memory reference insts executed")
197 .init(cpu->number_of_threads)
198 .name(name() + ".EXEC:branches")
199 .desc("Number of branches executed")
203 .name(name() + ".EXEC:stores")
204 .desc("Number of stores executed")
206 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
209 .name(name() + ".EXEC:rate")
210 .desc("Inst execution rate")
213 iewExecRate = iewExecutedInsts / cpu->numCycles;
216 .init(cpu->number_of_threads)
217 .name(name() + ".WB:sent")
218 .desc("cumulative count of insts sent to commit")
222 .init(cpu->number_of_threads)
223 .name(name() + ".WB:count")
224 .desc("cumulative count of insts written-back")
228 .init(cpu->number_of_threads)
229 .name(name() + ".WB:producers")
230 .desc("num instructions producing a value")
234 .init(cpu->number_of_threads)
235 .name(name() + ".WB:consumers")
236 .desc("num instructions consuming a value")
240 .init(cpu->number_of_threads)
241 .name(name() + ".WB:penalized")
242 .desc("number of instrctions required to write to 'other' IQ")
246 .name(name() + ".WB:penalized_rate")
247 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
250 wbPenalizedRate = wbPenalized / writebackCount;
253 .name(name() + ".WB:fanout")
254 .desc("average fanout of values written-back")
257 wbFanout = producerInst / consumerInst;
260 .name(name() + ".WB:rate")
261 .desc("insts written-back per cycle")
263 wbRate = writebackCount / cpu->numCycles;
268 DefaultIEW<Impl>::initStage()
270 for (int tid=0; tid < numThreads; tid++) {
271 toRename->iewInfo[tid].usedIQ = true;
272 toRename->iewInfo[tid].freeIQEntries =
273 instQueue.numFreeEntries(tid);
275 toRename->iewInfo[tid].usedLSQ = true;
276 toRename->iewInfo[tid].freeLSQEntries =
277 ldstQueue.numFreeEntries(tid);
283 DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
285 DPRINTF(IEW, "Setting CPU pointer.\n");
288 instQueue.setCPU(cpu_ptr);
289 ldstQueue.setCPU(cpu_ptr);
291 cpu->activateStage(O3CPU::IEWIdx);
296 DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
298 DPRINTF(IEW, "Setting time buffer pointer.\n");
301 // Setup wire to read information from time buffer, from commit.
302 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
304 // Setup wire to write information back to previous stages.
305 toRename = timeBuffer->getWire(0);
307 toFetch = timeBuffer->getWire(0);
309 // Instruction queue also needs main time buffer.
310 instQueue.setTimeBuffer(tb_ptr);
315 DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
317 DPRINTF(IEW, "Setting rename queue pointer.\n");
318 renameQueue = rq_ptr;
320 // Setup wire to read information from rename queue.
321 fromRename = renameQueue->getWire(-renameToIEWDelay);
326 DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
328 DPRINTF(IEW, "Setting IEW queue pointer.\n");
331 // Setup wire to write instructions to commit.
332 toCommit = iewQueue->getWire(0);
337 DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
339 DPRINTF(IEW, "Setting active threads list pointer.\n");
340 activeThreads = at_ptr;
342 ldstQueue.setActiveThreads(at_ptr);
343 instQueue.setActiveThreads(at_ptr);
348 DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
350 DPRINTF(IEW, "Setting scoreboard pointer.\n");
354 template <class Impl>
356 DefaultIEW<Impl>::drain()
358 // IEW is ready to drain at any time.
359 cpu->signalDrained();
363 template <class Impl>
365 DefaultIEW<Impl>::resume()
369 template <class Impl>
371 DefaultIEW<Impl>::switchOut()
375 assert(insts[0].empty());
376 assert(skidBuffer[0].empty());
378 instQueue.switchOut();
379 ldstQueue.switchOut();
382 for (int i = 0; i < numThreads; i++) {
383 while (!insts[i].empty())
385 while (!skidBuffer[i].empty())
390 template <class Impl>
392 DefaultIEW<Impl>::takeOverFrom()
400 instQueue.takeOverFrom();
401 ldstQueue.takeOverFrom();
402 fuPool->takeOverFrom();
405 cpu->activityThisCycle();
407 for (int i=0; i < numThreads; i++) {
408 dispatchStatus[i] = Running;
409 stalls[i].commit = false;
410 fetchRedirect[i] = false;
413 updateLSQNextCycle = false;
415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416 issueToExecQueue.advance();
422 DefaultIEW<Impl>::squash(unsigned tid)
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
430 // Tell the LDSTQ to start squashing.
431 #if ISA_HAS_DELAY_SLOT
432 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
434 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
436 updatedQueues = true;
438 // Clear the skid buffer in case it has any data in it.
439 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
442 while (!skidBuffer[tid].empty()) {
443 #if ISA_HAS_DELAY_SLOT
444 if (skidBuffer[tid].front()->seqNum <=
445 fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447 "that occur before delay slot [sn:%i].\n",
448 fromCommit->commitInfo[tid].bdelayDoneSeqNum,
452 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
456 if (skidBuffer[tid].front()->isLoad() ||
457 skidBuffer[tid].front()->isStore() ) {
458 toRename->iewInfo[tid].dispatchedToLSQ++;
461 toRename->iewInfo[tid].dispatched++;
463 skidBuffer[tid].pop();
466 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
468 emptyRenameInsts(tid);
473 DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->mispredPC[tid] = inst->readPC();
481 toCommit->branchMispredict[tid] = true;
483 int instSize = sizeof(TheISA::MachInst);
484 #if ISA_HAS_DELAY_SLOT
486 !(inst->readNextPC() + instSize == inst->readNextNPC() &&
487 (inst->readNextPC() == inst->readPC() + instSize ||
488 inst->readNextPC() == inst->readPC() + 2 * instSize));
489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
490 branch_taken ? "true": "false", inst->seqNum);
492 toCommit->branchTaken[tid] = branch_taken;
494 bool squashDelaySlot = true;
495 // (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
496 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
497 squashDelaySlot ? "true": "false", inst->seqNum);
498 toCommit->squashDelaySlot[tid] = squashDelaySlot;
499 //If we're squashing the delay slot, we need to pick back up at NextPC.
500 //Otherwise, NextPC isn't being squashed, so we should pick back up at
502 if (squashDelaySlot) {
503 toCommit->nextPC[tid] = inst->readNextPC();
504 toCommit->nextNPC[tid] = inst->readNextNPC();
506 toCommit->nextPC[tid] = inst->readNextNPC();
507 toCommit->nextNPC[tid] = inst->readNextNPC() + instSize;
510 toCommit->branchTaken[tid] = inst->readNextPC() !=
511 (inst->readPC() + sizeof(TheISA::MachInst));
512 toCommit->nextPC[tid] = inst->readNextPC();
513 toCommit->nextNPC[tid] = inst->readNextPC() + instSize;
516 toCommit->includeSquashInst[tid] = false;
518 wroteToTimeBuffer = true;
523 DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
525 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
526 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
528 toCommit->squash[tid] = true;
529 toCommit->squashedSeqNum[tid] = inst->seqNum;
530 toCommit->nextPC[tid] = inst->readNextPC();
531 #if ISA_HAS_DELAY_SLOT
532 toCommit->nextNPC[tid] = inst->readNextNPC();
534 toCommit->nextNPC[tid] = inst->readNextPC() + sizeof(TheISA::MachInst);
536 toCommit->branchMispredict[tid] = false;
538 toCommit->includeSquashInst[tid] = false;
540 wroteToTimeBuffer = true;
545 DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
547 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
548 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
550 toCommit->squash[tid] = true;
551 toCommit->squashedSeqNum[tid] = inst->seqNum;
552 toCommit->nextPC[tid] = inst->readPC();
553 #if ISA_HAS_DELAY_SLOT
554 toCommit->nextNPC[tid] = inst->readNextPC();
556 toCommit->nextNPC[tid] = inst->readPC() + sizeof(TheISA::MachInst);
558 toCommit->branchMispredict[tid] = false;
560 // Must include the broadcasted SN in the squash.
561 toCommit->includeSquashInst[tid] = true;
563 ldstQueue.setLoadBlockedHandled(tid);
565 wroteToTimeBuffer = true;
570 DefaultIEW<Impl>::block(unsigned tid)
572 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
574 if (dispatchStatus[tid] != Blocked &&
575 dispatchStatus[tid] != Unblocking) {
576 toRename->iewBlock[tid] = true;
577 wroteToTimeBuffer = true;
580 // Add the current inputs to the skid buffer so they can be
581 // reprocessed when this stage unblocks.
584 dispatchStatus[tid] = Blocked;
589 DefaultIEW<Impl>::unblock(unsigned tid)
591 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
592 "buffer %u.\n",tid, tid);
594 // If the skid bufffer is empty, signal back to previous stages to unblock.
595 // Also switch status to running.
596 if (skidBuffer[tid].empty()) {
597 toRename->iewUnblock[tid] = true;
598 wroteToTimeBuffer = true;
599 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
600 dispatchStatus[tid] = Running;
606 DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
608 instQueue.wakeDependents(inst);
613 DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
615 instQueue.rescheduleMemInst(inst);
620 DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
622 instQueue.replayMemInst(inst);
627 DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
629 // This function should not be called after writebackInsts in a
630 // single cycle. That will cause problems with an instruction
631 // being added to the queue to commit without being processed by
632 // writebackInsts prior to being sent to commit.
634 // First check the time slot that this instruction will write
635 // to. If there are free write ports at the time, then go ahead
636 // and write the instruction to that time. If there are not,
637 // keep looking back to see where's the first time there's a
639 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
641 if (wbNumInst == wbWidth) {
646 assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
649 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
650 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
651 // Add finished instruction to queue to commit.
652 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
653 (*iewQueue)[wbCycle].size++;
656 template <class Impl>
658 DefaultIEW<Impl>::validInstsFromRename()
660 unsigned inst_count = 0;
662 for (int i=0; i<fromRename->size; i++) {
663 if (!fromRename->insts[i]->isSquashed())
672 DefaultIEW<Impl>::skidInsert(unsigned tid)
674 DynInstPtr inst = NULL;
676 while (!insts[tid].empty()) {
677 inst = insts[tid].front();
681 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
682 "dispatch skidBuffer %i\n",tid, inst->seqNum,
685 skidBuffer[tid].push(inst);
688 assert(skidBuffer[tid].size() <= skidBufferMax &&
689 "Skidbuffer Exceeded Max Size");
694 DefaultIEW<Impl>::skidCount()
698 std::list<unsigned>::iterator threads = activeThreads->begin();
699 std::list<unsigned>::iterator end = activeThreads->end();
701 while (threads != end) {
702 unsigned tid = *threads++;
703 unsigned thread_count = skidBuffer[tid].size();
704 if (max < thread_count)
713 DefaultIEW<Impl>::skidsEmpty()
715 std::list<unsigned>::iterator threads = activeThreads->begin();
716 std::list<unsigned>::iterator end = activeThreads->end();
718 while (threads != end) {
719 unsigned tid = *threads++;
721 if (!skidBuffer[tid].empty())
728 template <class Impl>
730 DefaultIEW<Impl>::updateStatus()
732 bool any_unblocking = false;
734 std::list<unsigned>::iterator threads = activeThreads->begin();
735 std::list<unsigned>::iterator end = activeThreads->end();
737 while (threads != end) {
738 unsigned tid = *threads++;
740 if (dispatchStatus[tid] == Unblocking) {
741 any_unblocking = true;
746 // If there are no ready instructions waiting to be scheduled by the IQ,
747 // and there's no stores waiting to write back, and dispatch is not
748 // unblocking, then there is no internal activity for the IEW stage.
749 if (_status == Active && !instQueue.hasReadyInsts() &&
750 !ldstQueue.willWB() && !any_unblocking) {
751 DPRINTF(IEW, "IEW switching to idle\n");
756 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
757 ldstQueue.willWB() ||
759 // Otherwise there is internal activity. Set to active.
760 DPRINTF(IEW, "IEW switching to active\n");
768 template <class Impl>
770 DefaultIEW<Impl>::resetEntries()
772 instQueue.resetEntries();
773 ldstQueue.resetEntries();
776 template <class Impl>
778 DefaultIEW<Impl>::readStallSignals(unsigned tid)
780 if (fromCommit->commitBlock[tid]) {
781 stalls[tid].commit = true;
784 if (fromCommit->commitUnblock[tid]) {
785 assert(stalls[tid].commit);
786 stalls[tid].commit = false;
790 template <class Impl>
792 DefaultIEW<Impl>::checkStall(unsigned tid)
796 if (stalls[tid].commit) {
797 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
799 } else if (instQueue.isFull(tid)) {
800 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
802 } else if (ldstQueue.isFull(tid)) {
803 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
805 if (ldstQueue.numLoads(tid) > 0 ) {
807 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
808 tid,ldstQueue.getLoadHeadSeqNum(tid));
811 if (ldstQueue.numStores(tid) > 0) {
813 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
814 tid,ldstQueue.getStoreHeadSeqNum(tid));
818 } else if (ldstQueue.isStalled(tid)) {
819 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
826 template <class Impl>
828 DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
830 // Check if there's a squash signal, squash if there is
831 // Check stall signals, block if there is.
832 // If status was Blocked
833 // if so then go to unblocking
834 // If status was Squashing
835 // check if squashing is not high. Switch to running this cycle.
837 readStallSignals(tid);
839 if (fromCommit->commitInfo[tid].squash) {
842 if (dispatchStatus[tid] == Blocked ||
843 dispatchStatus[tid] == Unblocking) {
844 toRename->iewUnblock[tid] = true;
845 wroteToTimeBuffer = true;
848 dispatchStatus[tid] = Squashing;
850 fetchRedirect[tid] = false;
854 if (fromCommit->commitInfo[tid].robSquashing) {
855 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
857 dispatchStatus[tid] = Squashing;
859 emptyRenameInsts(tid);
860 wroteToTimeBuffer = true;
864 if (checkStall(tid)) {
866 dispatchStatus[tid] = Blocked;
870 if (dispatchStatus[tid] == Blocked) {
871 // Status from previous cycle was blocked, but there are no more stall
872 // conditions. Switch over to unblocking.
873 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
876 dispatchStatus[tid] = Unblocking;
883 if (dispatchStatus[tid] == Squashing) {
884 // Switch status to running if rename isn't being told to block or
885 // squash this cycle.
886 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
889 dispatchStatus[tid] = Running;
895 template <class Impl>
897 DefaultIEW<Impl>::sortInsts()
899 int insts_from_rename = fromRename->size;
901 #if !ISA_HAS_DELAY_SLOT
902 for (int i = 0; i < numThreads; i++)
903 assert(insts[i].empty());
906 for (int i = 0; i < insts_from_rename; ++i) {
907 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
911 template <class Impl>
913 DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
915 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
916 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
918 while (!insts[tid].empty()) {
919 #if ISA_HAS_DELAY_SLOT
920 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
921 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
922 " that occurs at or before delay slot [sn:%i].\n",
923 tid, bdelayDoneSeqNum[tid]);
926 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
927 "[sn:%i].\n", tid, insts[tid].front()->seqNum);
931 if (insts[tid].front()->isLoad() ||
932 insts[tid].front()->isStore() ) {
933 toRename->iewInfo[tid].dispatchedToLSQ++;
936 toRename->iewInfo[tid].dispatched++;
942 template <class Impl>
944 DefaultIEW<Impl>::wakeCPU()
949 template <class Impl>
951 DefaultIEW<Impl>::activityThisCycle()
953 DPRINTF(Activity, "Activity this cycle.\n");
954 cpu->activityThisCycle();
957 template <class Impl>
959 DefaultIEW<Impl>::activateStage()
961 DPRINTF(Activity, "Activating stage.\n");
962 cpu->activateStage(O3CPU::IEWIdx);
965 template <class Impl>
967 DefaultIEW<Impl>::deactivateStage()
969 DPRINTF(Activity, "Deactivating stage.\n");
970 cpu->deactivateStage(O3CPU::IEWIdx);
975 DefaultIEW<Impl>::dispatch(unsigned tid)
977 // If status is Running or idle,
978 // call dispatchInsts()
979 // If status is Unblocking,
980 // buffer any instructions coming from rename
981 // continue trying to empty skid buffer
982 // check if stall conditions have passed
984 if (dispatchStatus[tid] == Blocked) {
987 } else if (dispatchStatus[tid] == Squashing) {
991 // Dispatch should try to dispatch as many instructions as its bandwidth
992 // will allow, as long as it is not currently blocked.
993 if (dispatchStatus[tid] == Running ||
994 dispatchStatus[tid] == Idle) {
995 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
999 } else if (dispatchStatus[tid] == Unblocking) {
1000 // Make sure that the skid buffer has something in it if the
1001 // status is unblocking.
1002 assert(!skidsEmpty());
1004 // If the status was unblocking, then instructions from the skid
1005 // buffer were used. Remove those instructions and handle
1006 // the rest of unblocking.
1011 if (validInstsFromRename() && dispatchedAllInsts) {
1012 // Add the current inputs to the skid buffer so they can be
1013 // reprocessed when this stage unblocks.
1021 template <class Impl>
1023 DefaultIEW<Impl>::dispatchInsts(unsigned tid)
1025 dispatchedAllInsts = true;
1027 // Obtain instructions from skid buffer if unblocking, or queue from rename
1029 std::queue<DynInstPtr> &insts_to_dispatch =
1030 dispatchStatus[tid] == Unblocking ?
1031 skidBuffer[tid] : insts[tid];
1033 int insts_to_add = insts_to_dispatch.size();
1036 bool add_to_iq = false;
1037 int dis_num_inst = 0;
1039 // Loop through the instructions, putting them in the instruction
1041 for ( ; dis_num_inst < insts_to_add &&
1042 dis_num_inst < dispatchWidth;
1045 inst = insts_to_dispatch.front();
1047 if (dispatchStatus[tid] == Unblocking) {
1048 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1052 // Make sure there's a valid instruction there.
1055 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1057 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1059 // Be sure to mark these instructions as ready so that the
1060 // commit stage can go ahead and execute them, and mark
1061 // them as issued so the IQ doesn't reprocess them.
1063 // Check for squashed instructions.
1064 if (inst->isSquashed()) {
1065 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1066 "not adding to IQ.\n", tid);
1068 ++iewDispSquashedInsts;
1070 insts_to_dispatch.pop();
1072 //Tell Rename That An Instruction has been processed
1073 if (inst->isLoad() || inst->isStore()) {
1074 toRename->iewInfo[tid].dispatchedToLSQ++;
1076 toRename->iewInfo[tid].dispatched++;
1081 // Check for full conditions.
1082 if (instQueue.isFull(tid)) {
1083 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1085 // Call function to start blocking.
1088 // Set unblock to false. Special case where we are using
1089 // skidbuffer (unblocking) instructions but then we still
1090 // get full in the IQ.
1091 toRename->iewUnblock[tid] = false;
1093 dispatchedAllInsts = false;
1097 } else if (ldstQueue.isFull(tid)) {
1098 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1100 // Call function to start blocking.
1103 // Set unblock to false. Special case where we are using
1104 // skidbuffer (unblocking) instructions but then we still
1105 // get full in the IQ.
1106 toRename->iewUnblock[tid] = false;
1108 dispatchedAllInsts = false;
1114 // Otherwise issue the instruction just fine.
1115 if (inst->isLoad()) {
1116 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1117 "encountered, adding to LSQ.\n", tid);
1119 // Reserve a spot in the load store queue for this
1121 ldstQueue.insertLoad(inst);
1127 toRename->iewInfo[tid].dispatchedToLSQ++;
1128 } else if (inst->isStore()) {
1129 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1130 "encountered, adding to LSQ.\n", tid);
1132 ldstQueue.insertStore(inst);
1134 ++iewDispStoreInsts;
1136 if (inst->isStoreConditional()) {
1137 // Store conditionals need to be set as "canCommit()"
1138 // so that commit can process them when they reach the
1140 // @todo: This is somewhat specific to Alpha.
1141 inst->setCanCommit();
1142 instQueue.insertNonSpec(inst);
1145 ++iewDispNonSpecInsts;
1150 toRename->iewInfo[tid].dispatchedToLSQ++;
1151 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1152 // Same as non-speculative stores.
1153 inst->setCanCommit();
1154 instQueue.insertBarrier(inst);
1156 } else if (inst->isNop()) {
1157 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1158 "skipping.\n", tid);
1161 inst->setExecuted();
1162 inst->setCanCommit();
1164 instQueue.recordProducer(inst);
1166 iewExecutedNop[tid]++;
1169 } else if (inst->isExecuted()) {
1170 assert(0 && "Instruction shouldn't be executed.\n");
1171 DPRINTF(IEW, "Issue: Executed branch encountered, "
1175 inst->setCanCommit();
1177 instQueue.recordProducer(inst);
1183 if (inst->isNonSpeculative()) {
1184 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1185 "encountered, skipping.\n", tid);
1187 // Same as non-speculative stores.
1188 inst->setCanCommit();
1190 // Specifically insert it as nonspeculative.
1191 instQueue.insertNonSpec(inst);
1193 ++iewDispNonSpecInsts;
1198 // If the instruction queue is not full, then add the
1201 instQueue.insert(inst);
1204 insts_to_dispatch.pop();
1206 toRename->iewInfo[tid].dispatched++;
1208 ++iewDispatchedInsts;
1211 if (!insts_to_dispatch.empty()) {
1212 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1214 toRename->iewUnblock[tid] = false;
1217 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1218 dispatchStatus[tid] = Running;
1220 updatedQueues = true;
1226 template <class Impl>
1228 DefaultIEW<Impl>::printAvailableInsts()
1232 std::cout << "Available Instructions: ";
1234 while (fromIssue->insts[inst]) {
1236 if (inst%3==0) std::cout << "\n\t";
1238 std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1239 << " TN: " << fromIssue->insts[inst]->threadNumber
1240 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1249 template <class Impl>
1251 DefaultIEW<Impl>::executeInsts()
1256 std::list<unsigned>::iterator threads = activeThreads->begin();
1257 std::list<unsigned>::iterator end = activeThreads->end();
1259 while (threads != end) {
1260 unsigned tid = *threads++;
1261 fetchRedirect[tid] = false;
1264 // Uncomment this if you want to see all available instructions.
1265 // printAvailableInsts();
1267 // Execute/writeback any instructions that are available.
1268 int insts_to_execute = fromIssue->size;
1270 for (; inst_num < insts_to_execute;
1273 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1275 DynInstPtr inst = instQueue.getInstToExecute();
1277 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1278 inst->readPC(), inst->threadNumber,inst->seqNum);
1280 // Check if the instruction is squashed; if so then skip it
1281 if (inst->isSquashed()) {
1282 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1284 // Consider this instruction executed so that commit can go
1285 // ahead and retire the instruction.
1286 inst->setExecuted();
1288 // Not sure if I should set this here or just let commit try to
1289 // commit any squashed instructions. I like the latter a bit more.
1290 inst->setCanCommit();
1292 ++iewExecSquashedInsts;
1294 decrWb(inst->seqNum);
1298 Fault fault = NoFault;
1300 // Execute instruction.
1301 // Note that if the instruction faults, it will be handled
1302 // at the commit stage.
1303 if (inst->isMemRef() &&
1304 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1305 DPRINTF(IEW, "Execute: Calculating address for memory "
1308 // Tell the LDSTQ to execute this instruction (if it is a load).
1309 if (inst->isLoad()) {
1310 // Loads will mark themselves as executed, and their writeback
1311 // event adds the instruction to the queue to commit
1312 fault = ldstQueue.executeLoad(inst);
1313 } else if (inst->isStore()) {
1314 fault = ldstQueue.executeStore(inst);
1316 // If the store had a fault then it may not have a mem req
1317 if (!inst->isStoreConditional() && fault == NoFault) {
1318 inst->setExecuted();
1321 } else if (fault != NoFault) {
1322 // If the instruction faulted, then we need to send it along to commit
1323 // without the instruction completing.
1324 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1325 fault->name(), inst->seqNum);
1327 // Send this instruction to commit, also make sure iew stage
1328 // realizes there is activity.
1329 inst->setExecuted();
1332 activityThisCycle();
1335 // Store conditionals will mark themselves as
1336 // executed, and their writeback event will add the
1337 // instruction to the queue to commit.
1339 panic("Unexpected memory type!\n");
1345 inst->setExecuted();
1350 updateExeInstStats(inst);
1352 // Check if branch prediction was correct, if not then we need
1353 // to tell commit to squash in flight instructions. Only
1354 // handle this if there hasn't already been something that
1355 // redirects fetch in this group of instructions.
1357 // This probably needs to prioritize the redirects if a different
1358 // scheduler is used. Currently the scheduler schedules the oldest
1359 // instruction first, so the branch resolution order will be correct.
1360 unsigned tid = inst->threadNumber;
1362 if (!fetchRedirect[tid] ||
1363 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1365 if (inst->mispredicted()) {
1366 fetchRedirect[tid] = true;
1368 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1369 DPRINTF(IEW, "Predicted target was %#x, %#x.\n",
1370 inst->readPredPC(), inst->readPredNPC());
1371 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1372 " NPC: %#x.\n", inst->readNextPC(),
1373 inst->readNextNPC());
1374 // If incorrect, then signal the ROB that it must be squashed.
1375 squashDueToBranch(inst, tid);
1377 if (inst->readPredTaken()) {
1378 predictedTakenIncorrect++;
1380 predictedNotTakenIncorrect++;
1382 } else if (ldstQueue.violation(tid)) {
1383 assert(inst->isMemRef());
1384 // If there was an ordering violation, then get the
1385 // DynInst that caused the violation. Note that this
1386 // clears the violation signal.
1387 DynInstPtr violator;
1388 violator = ldstQueue.getMemDepViolator(tid);
1390 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1391 "%#x, inst PC: %#x. Addr is: %#x.\n",
1392 violator->readPC(), inst->readPC(), inst->physEffAddr);
1394 // Ensure the violating instruction is older than
1396 /* if (fetchRedirect[tid] &&
1397 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1)
1400 fetchRedirect[tid] = true;
1402 // Tell the instruction queue that a violation has occured.
1403 instQueue.violation(inst, violator);
1406 squashDueToMemOrder(inst,tid);
1408 ++memOrderViolationEvents;
1409 } else if (ldstQueue.loadBlocked(tid) &&
1410 !ldstQueue.isLoadBlockedHandled(tid)) {
1411 fetchRedirect[tid] = true;
1413 DPRINTF(IEW, "Load operation couldn't execute because the "
1414 "memory system is blocked. PC: %#x [sn:%lli]\n",
1415 inst->readPC(), inst->seqNum);
1417 squashDueToMemBlocked(inst, tid);
1420 // Reset any state associated with redirects that will not
1422 if (ldstQueue.violation(tid)) {
1423 assert(inst->isMemRef());
1425 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1427 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1428 "%#x, inst PC: %#x. Addr is: %#x.\n",
1429 violator->readPC(), inst->readPC(), inst->physEffAddr);
1430 DPRINTF(IEW, "Violation will not be handled because "
1431 "already squashing\n");
1433 ++memOrderViolationEvents;
1435 if (ldstQueue.loadBlocked(tid) &&
1436 !ldstQueue.isLoadBlockedHandled(tid)) {
1437 DPRINTF(IEW, "Load operation couldn't execute because the "
1438 "memory system is blocked. PC: %#x [sn:%lli]\n",
1439 inst->readPC(), inst->seqNum);
1440 DPRINTF(IEW, "Blocked load will not be handled because "
1441 "already squashing\n");
1443 ldstQueue.setLoadBlockedHandled(tid);
1449 // Update and record activity if we processed any instructions.
1451 if (exeStatus == Idle) {
1452 exeStatus = Running;
1455 updatedQueues = true;
1457 cpu->activityThisCycle();
1460 // Need to reset this in case a writeback event needs to write into the
1461 // iew queue. That way the writeback event will write into the correct
1462 // spot in the queue.
1466 template <class Impl>
1468 DefaultIEW<Impl>::writebackInsts()
1470 // Loop through the head of the time buffer and wake any
1471 // dependents. These instructions are about to write back. Also
1472 // mark scoreboard that this instruction is finally complete.
1473 // Either have IEW have direct access to scoreboard, or have this
1474 // as part of backwards communication.
1475 for (int inst_num = 0; inst_num < wbWidth &&
1476 toCommit->insts[inst_num]; inst_num++) {
1477 DynInstPtr inst = toCommit->insts[inst_num];
1478 int tid = inst->threadNumber;
1480 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1481 inst->seqNum, inst->readPC());
1483 iewInstsToCommit[tid]++;
1485 // Some instructions will be sent to commit without having
1486 // executed because they need commit to handle them.
1487 // E.g. Uncached loads have not actually executed when they
1488 // are first sent to commit. Instead commit must tell the LSQ
1489 // when it's ready to execute the uncached load.
1490 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1491 int dependents = instQueue.wakeDependents(inst);
1493 for (int i = 0; i < inst->numDestRegs(); i++) {
1495 DPRINTF(IEW,"Setting Destination Register %i\n",
1496 inst->renamedDestRegIdx(i));
1497 scoreboard->setReg(inst->renamedDestRegIdx(i));
1501 producerInst[tid]++;
1502 consumerInst[tid]+= dependents;
1504 writebackCount[tid]++;
1507 decrWb(inst->seqNum);
1511 template<class Impl>
1513 DefaultIEW<Impl>::tick()
1518 wroteToTimeBuffer = false;
1519 updatedQueues = false;
1523 // Free function units marked as being freed this cycle.
1524 fuPool->processFreeUnits();
1526 std::list<unsigned>::iterator threads = activeThreads->begin();
1527 std::list<unsigned>::iterator end = activeThreads->end();
1529 // Check stall and squash signals, dispatch any instructions.
1530 while (threads != end) {
1531 unsigned tid = *threads++;
1533 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1535 checkSignalsAndUpdate(tid);
1539 if (exeStatus != Squashing) {
1544 // Have the instruction queue try to schedule any ready instructions.
1545 // (In actuality, this scheduling is for instructions that will
1546 // be executed next cycle.)
1547 instQueue.scheduleReadyInsts();
1549 // Also should advance its own time buffers if the stage ran.
1550 // Not the best place for it, but this works (hopefully).
1551 issueToExecQueue.advance();
1554 bool broadcast_free_entries = false;
1556 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1558 updateLSQNextCycle = false;
1560 broadcast_free_entries = true;
1563 // Writeback any stores using any leftover bandwidth.
1564 ldstQueue.writebackStores();
1566 // Check the committed load/store signals to see if there's a load
1567 // or store to commit. Also check if it's being told to execute a
1568 // nonspeculative instruction.
1569 // This is pretty inefficient...
1571 threads = activeThreads->begin();
1572 while (threads != end) {
1573 unsigned tid = (*threads++);
1575 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1577 // Update structures based on instructions committed.
1578 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1579 !fromCommit->commitInfo[tid].squash &&
1580 !fromCommit->commitInfo[tid].robSquashing) {
1582 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1584 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1586 updateLSQNextCycle = true;
1587 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1590 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1592 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1593 if (fromCommit->commitInfo[tid].uncached) {
1594 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1595 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1597 instQueue.scheduleNonSpec(
1598 fromCommit->commitInfo[tid].nonSpecSeqNum);
1602 if (broadcast_free_entries) {
1603 toFetch->iewInfo[tid].iqCount =
1604 instQueue.getCount(tid);
1605 toFetch->iewInfo[tid].ldstqCount =
1606 ldstQueue.getCount(tid);
1608 toRename->iewInfo[tid].usedIQ = true;
1609 toRename->iewInfo[tid].freeIQEntries =
1610 instQueue.numFreeEntries();
1611 toRename->iewInfo[tid].usedLSQ = true;
1612 toRename->iewInfo[tid].freeLSQEntries =
1613 ldstQueue.numFreeEntries(tid);
1615 wroteToTimeBuffer = true;
1618 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1619 tid, toRename->iewInfo[tid].dispatched);
1622 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1623 "LSQ has %i free entries.\n",
1624 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1625 ldstQueue.numFreeEntries());
1629 if (wroteToTimeBuffer) {
1630 DPRINTF(Activity, "Activity this cycle.\n");
1631 cpu->activityThisCycle();
1635 template <class Impl>
1637 DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1639 int thread_number = inst->threadNumber;
1642 // Pick off the software prefetches
1645 if (inst->isDataPrefetch())
1646 iewExecutedSwp[thread_number]++;
1648 iewIewExecutedcutedInsts++;
1654 // Control operations
1656 if (inst->isControl())
1657 iewExecutedBranches[thread_number]++;
1660 // Memory operations
1662 if (inst->isMemRef()) {
1663 iewExecutedRefs[thread_number]++;
1665 if (inst->isLoad()) {
1666 iewExecLoadInsts[thread_number]++;