2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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31 // @todo: Fix the instantaneous communication among all the stages within
32 // iew. There's a clear delay between issue and execute, yet backwards
33 // communication happens simultaneously.
37 #include "base/timebuf.hh"
38 #include "cpu/o3/fu_pool.hh"
39 #include "cpu/o3/iew.hh"
44 DefaultIEW<Impl>::DefaultIEW(Params *params)
45 : // @todo: Make this into a parameter.
46 issueToExecQueue(5, 5),
49 fuPool(params->fuPool),
50 commitToIEWDelay(params->commitToIEWDelay),
51 renameToIEWDelay(params->renameToIEWDelay),
52 issueToExecuteDelay(params->issueToExecuteDelay),
53 dispatchWidth(params->dispatchWidth),
54 issueWidth(params->issueWidth),
56 wbWidth(params->wbWidth),
57 numThreads(params->numberOfThreads),
64 // Setup wire to read instructions coming from issue.
65 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
67 // Instruction queue needs the queue between issue and execute.
68 instQueue.setIssueToExecuteQueue(&issueToExecQueue);
70 instQueue.setIEW(this);
71 ldstQueue.setIEW(this);
73 for (int i=0; i < numThreads; i++) {
74 dispatchStatus[i] = Running;
75 stalls[i].commit = false;
76 fetchRedirect[i] = false;
79 wbMax = wbWidth * params->wbDepth;
81 updateLSQNextCycle = false;
85 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
90 DefaultIEW<Impl>::name() const
92 return cpu->name() + ".iew";
97 DefaultIEW<Impl>::regStats()
99 using namespace Stats;
101 instQueue.regStats();
102 ldstQueue.regStats();
105 .name(name() + ".iewIdleCycles")
106 .desc("Number of cycles IEW is idle");
109 .name(name() + ".iewSquashCycles")
110 .desc("Number of cycles IEW is squashing");
113 .name(name() + ".iewBlockCycles")
114 .desc("Number of cycles IEW is blocking");
117 .name(name() + ".iewUnblockCycles")
118 .desc("Number of cycles IEW is unblocking");
121 .name(name() + ".iewDispatchedInsts")
122 .desc("Number of instructions dispatched to IQ");
125 .name(name() + ".iewDispSquashedInsts")
126 .desc("Number of squashed instructions skipped by dispatch");
129 .name(name() + ".iewDispLoadInsts")
130 .desc("Number of dispatched load instructions");
133 .name(name() + ".iewDispStoreInsts")
134 .desc("Number of dispatched store instructions");
137 .name(name() + ".iewDispNonSpecInsts")
138 .desc("Number of dispatched non-speculative instructions");
141 .name(name() + ".iewIQFullEvents")
142 .desc("Number of times the IQ has become full, causing a stall");
145 .name(name() + ".iewLSQFullEvents")
146 .desc("Number of times the LSQ has become full, causing a stall");
148 memOrderViolationEvents
149 .name(name() + ".memOrderViolationEvents")
150 .desc("Number of memory order violations");
152 predictedTakenIncorrect
153 .name(name() + ".predictedTakenIncorrect")
154 .desc("Number of branches that were predicted taken incorrectly");
156 predictedNotTakenIncorrect
157 .name(name() + ".predictedNotTakenIncorrect")
158 .desc("Number of branches that were predicted not taken incorrectly");
161 .name(name() + ".branchMispredicts")
162 .desc("Number of branch mispredicts detected at execute");
164 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
167 .name(name() + ".EXEC:insts")
168 .desc("Number of executed instructions");
171 .init(cpu->number_of_threads)
172 .name(name() + ".EXEC:loads")
173 .desc("Number of load instructions executed")
177 .name(name() + ".EXEC:squashedInsts")
178 .desc("Number of squashed instructions skipped in execute");
181 .init(cpu->number_of_threads)
182 .name(name() + ".EXEC:swp")
183 .desc("number of swp insts executed")
187 .init(cpu->number_of_threads)
188 .name(name() + ".EXEC:nop")
189 .desc("number of nop insts executed")
193 .init(cpu->number_of_threads)
194 .name(name() + ".EXEC:refs")
195 .desc("number of memory reference insts executed")
199 .init(cpu->number_of_threads)
200 .name(name() + ".EXEC:branches")
201 .desc("Number of branches executed")
205 .name(name() + ".EXEC:stores")
206 .desc("Number of stores executed")
208 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
211 .name(name() + ".EXEC:rate")
212 .desc("Inst execution rate")
215 iewExecRate = iewExecutedInsts / cpu->numCycles;
218 .init(cpu->number_of_threads)
219 .name(name() + ".WB:sent")
220 .desc("cumulative count of insts sent to commit")
224 .init(cpu->number_of_threads)
225 .name(name() + ".WB:count")
226 .desc("cumulative count of insts written-back")
230 .init(cpu->number_of_threads)
231 .name(name() + ".WB:producers")
232 .desc("num instructions producing a value")
236 .init(cpu->number_of_threads)
237 .name(name() + ".WB:consumers")
238 .desc("num instructions consuming a value")
242 .init(cpu->number_of_threads)
243 .name(name() + ".WB:penalized")
244 .desc("number of instrctions required to write to 'other' IQ")
248 .name(name() + ".WB:penalized_rate")
249 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
252 wbPenalizedRate = wbPenalized / writebackCount;
255 .name(name() + ".WB:fanout")
256 .desc("average fanout of values written-back")
259 wbFanout = producerInst / consumerInst;
262 .name(name() + ".WB:rate")
263 .desc("insts written-back per cycle")
265 wbRate = writebackCount / cpu->numCycles;
270 DefaultIEW<Impl>::initStage()
272 for (int tid=0; tid < numThreads; tid++) {
273 toRename->iewInfo[tid].usedIQ = true;
274 toRename->iewInfo[tid].freeIQEntries =
275 instQueue.numFreeEntries(tid);
277 toRename->iewInfo[tid].usedLSQ = true;
278 toRename->iewInfo[tid].freeLSQEntries =
279 ldstQueue.numFreeEntries(tid);
285 DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
287 DPRINTF(IEW, "Setting CPU pointer.\n");
290 instQueue.setCPU(cpu_ptr);
291 ldstQueue.setCPU(cpu_ptr);
293 cpu->activateStage(O3CPU::IEWIdx);
298 DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
300 DPRINTF(IEW, "Setting time buffer pointer.\n");
303 // Setup wire to read information from time buffer, from commit.
304 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
306 // Setup wire to write information back to previous stages.
307 toRename = timeBuffer->getWire(0);
309 toFetch = timeBuffer->getWire(0);
311 // Instruction queue also needs main time buffer.
312 instQueue.setTimeBuffer(tb_ptr);
317 DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
319 DPRINTF(IEW, "Setting rename queue pointer.\n");
320 renameQueue = rq_ptr;
322 // Setup wire to read information from rename queue.
323 fromRename = renameQueue->getWire(-renameToIEWDelay);
328 DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
330 DPRINTF(IEW, "Setting IEW queue pointer.\n");
333 // Setup wire to write instructions to commit.
334 toCommit = iewQueue->getWire(0);
339 DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
341 DPRINTF(IEW, "Setting active threads list pointer.\n");
342 activeThreads = at_ptr;
344 ldstQueue.setActiveThreads(at_ptr);
345 instQueue.setActiveThreads(at_ptr);
350 DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
352 DPRINTF(IEW, "Setting scoreboard pointer.\n");
356 template <class Impl>
358 DefaultIEW<Impl>::drain()
360 // IEW is ready to drain at any time.
361 cpu->signalDrained();
364 template <class Impl>
366 DefaultIEW<Impl>::resume()
370 template <class Impl>
372 DefaultIEW<Impl>::switchOut()
377 instQueue.switchOut();
378 ldstQueue.switchOut();
381 for (int i = 0; i < numThreads; i++) {
382 while (!insts[i].empty())
384 while (!skidBuffer[i].empty())
389 template <class Impl>
391 DefaultIEW<Impl>::takeOverFrom()
399 instQueue.takeOverFrom();
400 ldstQueue.takeOverFrom();
401 fuPool->takeOverFrom();
404 cpu->activityThisCycle();
406 for (int i=0; i < numThreads; i++) {
407 dispatchStatus[i] = Running;
408 stalls[i].commit = false;
409 fetchRedirect[i] = false;
412 updateLSQNextCycle = false;
414 // @todo: Fix hardcoded number
415 for (int i = 0; i < 6; ++i) {
416 issueToExecQueue.advance();
422 DefaultIEW<Impl>::squash(unsigned tid)
424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
427 // Tell the IQ to start squashing.
428 instQueue.squash(tid);
430 // Tell the LDSTQ to start squashing.
431 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
433 updatedQueues = true;
435 // Clear the skid buffer in case it has any data in it.
436 while (!skidBuffer[tid].empty()) {
438 if (skidBuffer[tid].front()->isLoad() ||
439 skidBuffer[tid].front()->isStore() ) {
440 toRename->iewInfo[tid].dispatchedToLSQ++;
443 toRename->iewInfo[tid].dispatched++;
445 skidBuffer[tid].pop();
448 emptyRenameInsts(tid);
453 DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
455 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
456 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
458 toCommit->squash[tid] = true;
459 toCommit->squashedSeqNum[tid] = inst->seqNum;
460 toCommit->mispredPC[tid] = inst->readPC();
461 toCommit->nextPC[tid] = inst->readNextPC();
462 toCommit->branchMispredict[tid] = true;
463 toCommit->branchTaken[tid] = inst->readNextPC() !=
464 (inst->readPC() + sizeof(TheISA::MachInst));
466 toCommit->includeSquashInst[tid] = false;
468 wroteToTimeBuffer = true;
473 DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
476 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
478 toCommit->squash[tid] = true;
479 toCommit->squashedSeqNum[tid] = inst->seqNum;
480 toCommit->nextPC[tid] = inst->readNextPC();
482 toCommit->includeSquashInst[tid] = false;
484 wroteToTimeBuffer = true;
489 DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
491 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
492 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
494 toCommit->squash[tid] = true;
495 toCommit->squashedSeqNum[tid] = inst->seqNum;
496 toCommit->nextPC[tid] = inst->readPC();
498 // Must include the broadcasted SN in the squash.
499 toCommit->includeSquashInst[tid] = true;
501 ldstQueue.setLoadBlockedHandled(tid);
503 wroteToTimeBuffer = true;
508 DefaultIEW<Impl>::block(unsigned tid)
510 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
512 if (dispatchStatus[tid] != Blocked &&
513 dispatchStatus[tid] != Unblocking) {
514 toRename->iewBlock[tid] = true;
515 wroteToTimeBuffer = true;
518 // Add the current inputs to the skid buffer so they can be
519 // reprocessed when this stage unblocks.
522 dispatchStatus[tid] = Blocked;
527 DefaultIEW<Impl>::unblock(unsigned tid)
529 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
530 "buffer %u.\n",tid, tid);
532 // If the skid bufffer is empty, signal back to previous stages to unblock.
533 // Also switch status to running.
534 if (skidBuffer[tid].empty()) {
535 toRename->iewUnblock[tid] = true;
536 wroteToTimeBuffer = true;
537 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
538 dispatchStatus[tid] = Running;
544 DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
546 instQueue.wakeDependents(inst);
551 DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
553 instQueue.rescheduleMemInst(inst);
558 DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
560 instQueue.replayMemInst(inst);
565 DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
567 // First check the time slot that this instruction will write
568 // to. If there are free write ports at the time, then go ahead
569 // and write the instruction to that time. If there are not,
570 // keep looking back to see where's the first time there's a
572 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
574 if (wbNumInst == wbWidth) {
579 assert((wbCycle * wbWidth + wbNumInst) < wbMax);
582 // Add finished instruction to queue to commit.
583 (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
584 (*iewQueue)[wbCycle].size++;
587 template <class Impl>
589 DefaultIEW<Impl>::validInstsFromRename()
591 unsigned inst_count = 0;
593 for (int i=0; i<fromRename->size; i++) {
594 if (!fromRename->insts[i]->isSquashed())
603 DefaultIEW<Impl>::skidInsert(unsigned tid)
605 DynInstPtr inst = NULL;
607 while (!insts[tid].empty()) {
608 inst = insts[tid].front();
612 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
613 "dispatch skidBuffer %i\n",tid, inst->seqNum,
616 skidBuffer[tid].push(inst);
619 assert(skidBuffer[tid].size() <= skidBufferMax &&
620 "Skidbuffer Exceeded Max Size");
625 DefaultIEW<Impl>::skidCount()
629 list<unsigned>::iterator threads = (*activeThreads).begin();
631 while (threads != (*activeThreads).end()) {
632 unsigned thread_count = skidBuffer[*threads++].size();
633 if (max < thread_count)
642 DefaultIEW<Impl>::skidsEmpty()
644 list<unsigned>::iterator threads = (*activeThreads).begin();
646 while (threads != (*activeThreads).end()) {
647 if (!skidBuffer[*threads++].empty())
654 template <class Impl>
656 DefaultIEW<Impl>::updateStatus()
658 bool any_unblocking = false;
660 list<unsigned>::iterator threads = (*activeThreads).begin();
662 threads = (*activeThreads).begin();
664 while (threads != (*activeThreads).end()) {
665 unsigned tid = *threads++;
667 if (dispatchStatus[tid] == Unblocking) {
668 any_unblocking = true;
673 // If there are no ready instructions waiting to be scheduled by the IQ,
674 // and there's no stores waiting to write back, and dispatch is not
675 // unblocking, then there is no internal activity for the IEW stage.
676 if (_status == Active && !instQueue.hasReadyInsts() &&
677 !ldstQueue.willWB() && !any_unblocking) {
678 DPRINTF(IEW, "IEW switching to idle\n");
683 } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
684 ldstQueue.willWB() ||
686 // Otherwise there is internal activity. Set to active.
687 DPRINTF(IEW, "IEW switching to active\n");
695 template <class Impl>
697 DefaultIEW<Impl>::resetEntries()
699 instQueue.resetEntries();
700 ldstQueue.resetEntries();
703 template <class Impl>
705 DefaultIEW<Impl>::readStallSignals(unsigned tid)
707 if (fromCommit->commitBlock[tid]) {
708 stalls[tid].commit = true;
711 if (fromCommit->commitUnblock[tid]) {
712 assert(stalls[tid].commit);
713 stalls[tid].commit = false;
717 template <class Impl>
719 DefaultIEW<Impl>::checkStall(unsigned tid)
723 if (stalls[tid].commit) {
724 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
726 } else if (instQueue.isFull(tid)) {
727 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
729 } else if (ldstQueue.isFull(tid)) {
730 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
732 if (ldstQueue.numLoads(tid) > 0 ) {
734 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
735 tid,ldstQueue.getLoadHeadSeqNum(tid));
738 if (ldstQueue.numStores(tid) > 0) {
740 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
741 tid,ldstQueue.getStoreHeadSeqNum(tid));
745 } else if (ldstQueue.isStalled(tid)) {
746 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
753 template <class Impl>
755 DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
757 // Check if there's a squash signal, squash if there is
758 // Check stall signals, block if there is.
759 // If status was Blocked
760 // if so then go to unblocking
761 // If status was Squashing
762 // check if squashing is not high. Switch to running this cycle.
764 readStallSignals(tid);
766 if (fromCommit->commitInfo[tid].squash) {
769 if (dispatchStatus[tid] == Blocked ||
770 dispatchStatus[tid] == Unblocking) {
771 toRename->iewUnblock[tid] = true;
772 wroteToTimeBuffer = true;
775 dispatchStatus[tid] = Squashing;
777 fetchRedirect[tid] = false;
781 if (fromCommit->commitInfo[tid].robSquashing) {
782 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
784 dispatchStatus[tid] = Squashing;
786 emptyRenameInsts(tid);
787 wroteToTimeBuffer = true;
791 if (checkStall(tid)) {
793 dispatchStatus[tid] = Blocked;
797 if (dispatchStatus[tid] == Blocked) {
798 // Status from previous cycle was blocked, but there are no more stall
799 // conditions. Switch over to unblocking.
800 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
803 dispatchStatus[tid] = Unblocking;
810 if (dispatchStatus[tid] == Squashing) {
811 // Switch status to running if rename isn't being told to block or
812 // squash this cycle.
813 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
816 dispatchStatus[tid] = Running;
822 template <class Impl>
824 DefaultIEW<Impl>::sortInsts()
826 int insts_from_rename = fromRename->size;
828 for (int i = 0; i < numThreads; i++)
829 assert(insts[i].empty());
831 for (int i = 0; i < insts_from_rename; ++i) {
832 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
836 template <class Impl>
838 DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
840 while (!insts[tid].empty()) {
841 if (insts[tid].front()->isLoad() ||
842 insts[tid].front()->isStore() ) {
843 toRename->iewInfo[tid].dispatchedToLSQ++;
846 toRename->iewInfo[tid].dispatched++;
852 template <class Impl>
854 DefaultIEW<Impl>::wakeCPU()
859 template <class Impl>
861 DefaultIEW<Impl>::activityThisCycle()
863 DPRINTF(Activity, "Activity this cycle.\n");
864 cpu->activityThisCycle();
867 template <class Impl>
869 DefaultIEW<Impl>::activateStage()
871 DPRINTF(Activity, "Activating stage.\n");
872 cpu->activateStage(O3CPU::IEWIdx);
875 template <class Impl>
877 DefaultIEW<Impl>::deactivateStage()
879 DPRINTF(Activity, "Deactivating stage.\n");
880 cpu->deactivateStage(O3CPU::IEWIdx);
885 DefaultIEW<Impl>::dispatch(unsigned tid)
887 // If status is Running or idle,
888 // call dispatchInsts()
889 // If status is Unblocking,
890 // buffer any instructions coming from rename
891 // continue trying to empty skid buffer
892 // check if stall conditions have passed
894 if (dispatchStatus[tid] == Blocked) {
897 } else if (dispatchStatus[tid] == Squashing) {
901 // Dispatch should try to dispatch as many instructions as its bandwidth
902 // will allow, as long as it is not currently blocked.
903 if (dispatchStatus[tid] == Running ||
904 dispatchStatus[tid] == Idle) {
905 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
909 } else if (dispatchStatus[tid] == Unblocking) {
910 // Make sure that the skid buffer has something in it if the
911 // status is unblocking.
912 assert(!skidsEmpty());
914 // If the status was unblocking, then instructions from the skid
915 // buffer were used. Remove those instructions and handle
916 // the rest of unblocking.
921 if (validInstsFromRename() && dispatchedAllInsts) {
922 // Add the current inputs to the skid buffer so they can be
923 // reprocessed when this stage unblocks.
931 template <class Impl>
933 DefaultIEW<Impl>::dispatchInsts(unsigned tid)
935 dispatchedAllInsts = true;
937 // Obtain instructions from skid buffer if unblocking, or queue from rename
939 std::queue<DynInstPtr> &insts_to_dispatch =
940 dispatchStatus[tid] == Unblocking ?
941 skidBuffer[tid] : insts[tid];
943 int insts_to_add = insts_to_dispatch.size();
946 bool add_to_iq = false;
947 int dis_num_inst = 0;
949 // Loop through the instructions, putting them in the instruction
951 for ( ; dis_num_inst < insts_to_add &&
952 dis_num_inst < dispatchWidth;
955 inst = insts_to_dispatch.front();
957 if (dispatchStatus[tid] == Unblocking) {
958 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
962 // Make sure there's a valid instruction there.
965 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
967 tid, inst->readPC(), inst->seqNum, inst->threadNumber);
969 // Be sure to mark these instructions as ready so that the
970 // commit stage can go ahead and execute them, and mark
971 // them as issued so the IQ doesn't reprocess them.
973 // Check for squashed instructions.
974 if (inst->isSquashed()) {
975 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
976 "not adding to IQ.\n", tid);
978 ++iewDispSquashedInsts;
980 insts_to_dispatch.pop();
982 //Tell Rename That An Instruction has been processed
983 if (inst->isLoad() || inst->isStore()) {
984 toRename->iewInfo[tid].dispatchedToLSQ++;
986 toRename->iewInfo[tid].dispatched++;
991 // Check for full conditions.
992 if (instQueue.isFull(tid)) {
993 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
995 // Call function to start blocking.
998 // Set unblock to false. Special case where we are using
999 // skidbuffer (unblocking) instructions but then we still
1000 // get full in the IQ.
1001 toRename->iewUnblock[tid] = false;
1003 dispatchedAllInsts = false;
1007 } else if (ldstQueue.isFull(tid)) {
1008 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1010 // Call function to start blocking.
1013 // Set unblock to false. Special case where we are using
1014 // skidbuffer (unblocking) instructions but then we still
1015 // get full in the IQ.
1016 toRename->iewUnblock[tid] = false;
1018 dispatchedAllInsts = false;
1024 // Otherwise issue the instruction just fine.
1025 if (inst->isLoad()) {
1026 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1027 "encountered, adding to LSQ.\n", tid);
1029 // Reserve a spot in the load store queue for this
1031 ldstQueue.insertLoad(inst);
1037 toRename->iewInfo[tid].dispatchedToLSQ++;
1038 } else if (inst->isStore()) {
1039 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1040 "encountered, adding to LSQ.\n", tid);
1042 ldstQueue.insertStore(inst);
1044 ++iewDispStoreInsts;
1046 if (inst->isStoreConditional()) {
1047 // Store conditionals need to be set as "canCommit()"
1048 // so that commit can process them when they reach the
1050 // @todo: This is somewhat specific to Alpha.
1051 inst->setCanCommit();
1052 instQueue.insertNonSpec(inst);
1055 ++iewDispNonSpecInsts;
1060 toRename->iewInfo[tid].dispatchedToLSQ++;
1062 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1063 // Same as non-speculative stores.
1064 inst->setCanCommit();
1065 instQueue.insertBarrier(inst);
1068 } else if (inst->isNonSpeculative()) {
1069 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1070 "encountered, skipping.\n", tid);
1072 // Same as non-speculative stores.
1073 inst->setCanCommit();
1075 // Specifically insert it as nonspeculative.
1076 instQueue.insertNonSpec(inst);
1078 ++iewDispNonSpecInsts;
1081 } else if (inst->isNop()) {
1082 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1083 "skipping.\n", tid);
1086 inst->setExecuted();
1087 inst->setCanCommit();
1089 instQueue.recordProducer(inst);
1091 iewExecutedNop[tid]++;
1094 } else if (inst->isExecuted()) {
1095 assert(0 && "Instruction shouldn't be executed.\n");
1096 DPRINTF(IEW, "Issue: Executed branch encountered, "
1100 inst->setCanCommit();
1102 instQueue.recordProducer(inst);
1109 // If the instruction queue is not full, then add the
1112 instQueue.insert(inst);
1115 insts_to_dispatch.pop();
1117 toRename->iewInfo[tid].dispatched++;
1119 ++iewDispatchedInsts;
1122 if (!insts_to_dispatch.empty()) {
1123 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1125 toRename->iewUnblock[tid] = false;
1128 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1129 dispatchStatus[tid] = Running;
1131 updatedQueues = true;
1137 template <class Impl>
1139 DefaultIEW<Impl>::printAvailableInsts()
1143 cout << "Available Instructions: ";
1145 while (fromIssue->insts[inst]) {
1147 if (inst%3==0) cout << "\n\t";
1149 cout << "PC: " << fromIssue->insts[inst]->readPC()
1150 << " TN: " << fromIssue->insts[inst]->threadNumber
1151 << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1160 template <class Impl>
1162 DefaultIEW<Impl>::executeInsts()
1167 list<unsigned>::iterator threads = (*activeThreads).begin();
1169 while (threads != (*activeThreads).end()) {
1170 unsigned tid = *threads++;
1171 fetchRedirect[tid] = false;
1174 // Uncomment this if you want to see all available instructions.
1175 // printAvailableInsts();
1177 // Execute/writeback any instructions that are available.
1178 int insts_to_execute = fromIssue->size;
1180 for (; inst_num < insts_to_execute;
1183 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1185 DynInstPtr inst = instQueue.getInstToExecute();
1187 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1188 inst->readPC(), inst->threadNumber,inst->seqNum);
1190 // Check if the instruction is squashed; if so then skip it
1191 if (inst->isSquashed()) {
1192 DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1194 // Consider this instruction executed so that commit can go
1195 // ahead and retire the instruction.
1196 inst->setExecuted();
1198 // Not sure if I should set this here or just let commit try to
1199 // commit any squashed instructions. I like the latter a bit more.
1200 inst->setCanCommit();
1202 ++iewExecSquashedInsts;
1204 decrWb(inst->seqNum);
1208 Fault fault = NoFault;
1210 // Execute instruction.
1211 // Note that if the instruction faults, it will be handled
1212 // at the commit stage.
1213 if (inst->isMemRef() &&
1214 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1215 DPRINTF(IEW, "Execute: Calculating address for memory "
1218 // Tell the LDSTQ to execute this instruction (if it is a load).
1219 if (inst->isLoad()) {
1220 // Loads will mark themselves as executed, and their writeback
1221 // event adds the instruction to the queue to commit
1222 fault = ldstQueue.executeLoad(inst);
1223 } else if (inst->isStore()) {
1224 ldstQueue.executeStore(inst);
1226 // If the store had a fault then it may not have a mem req
1227 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1228 inst->setExecuted();
1233 // Store conditionals will mark themselves as
1234 // executed, and their writeback event will add the
1235 // instruction to the queue to commit.
1237 panic("Unexpected memory type!\n");
1243 inst->setExecuted();
1248 updateExeInstStats(inst);
1250 // Check if branch prediction was correct, if not then we need
1251 // to tell commit to squash in flight instructions. Only
1252 // handle this if there hasn't already been something that
1253 // redirects fetch in this group of instructions.
1255 // This probably needs to prioritize the redirects if a different
1256 // scheduler is used. Currently the scheduler schedules the oldest
1257 // instruction first, so the branch resolution order will be correct.
1258 unsigned tid = inst->threadNumber;
1260 if (!fetchRedirect[tid]) {
1262 if (inst->mispredicted()) {
1263 fetchRedirect[tid] = true;
1265 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1266 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1269 // If incorrect, then signal the ROB that it must be squashed.
1270 squashDueToBranch(inst, tid);
1272 if (inst->predTaken()) {
1273 predictedTakenIncorrect++;
1275 predictedNotTakenIncorrect++;
1277 } else if (ldstQueue.violation(tid)) {
1278 fetchRedirect[tid] = true;
1280 // If there was an ordering violation, then get the
1281 // DynInst that caused the violation. Note that this
1282 // clears the violation signal.
1283 DynInstPtr violator;
1284 violator = ldstQueue.getMemDepViolator(tid);
1286 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1287 "%#x, inst PC: %#x. Addr is: %#x.\n",
1288 violator->readPC(), inst->readPC(), inst->physEffAddr);
1290 // Tell the instruction queue that a violation has occured.
1291 instQueue.violation(inst, violator);
1294 squashDueToMemOrder(inst,tid);
1296 ++memOrderViolationEvents;
1297 } else if (ldstQueue.loadBlocked(tid) &&
1298 !ldstQueue.isLoadBlockedHandled(tid)) {
1299 fetchRedirect[tid] = true;
1301 DPRINTF(IEW, "Load operation couldn't execute because the "
1302 "memory system is blocked. PC: %#x [sn:%lli]\n",
1303 inst->readPC(), inst->seqNum);
1305 squashDueToMemBlocked(inst, tid);
1310 // Update and record activity if we processed any instructions.
1312 if (exeStatus == Idle) {
1313 exeStatus = Running;
1316 updatedQueues = true;
1318 cpu->activityThisCycle();
1321 // Need to reset this in case a writeback event needs to write into the
1322 // iew queue. That way the writeback event will write into the correct
1323 // spot in the queue.
1327 template <class Impl>
1329 DefaultIEW<Impl>::writebackInsts()
1331 // Loop through the head of the time buffer and wake any
1332 // dependents. These instructions are about to write back. Also
1333 // mark scoreboard that this instruction is finally complete.
1334 // Either have IEW have direct access to scoreboard, or have this
1335 // as part of backwards communication.
1336 for (int inst_num = 0; inst_num < issueWidth &&
1337 toCommit->insts[inst_num]; inst_num++) {
1338 DynInstPtr inst = toCommit->insts[inst_num];
1339 int tid = inst->threadNumber;
1341 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1342 inst->seqNum, inst->readPC());
1344 iewInstsToCommit[tid]++;
1346 // Some instructions will be sent to commit without having
1347 // executed because they need commit to handle them.
1348 // E.g. Uncached loads have not actually executed when they
1349 // are first sent to commit. Instead commit must tell the LSQ
1350 // when it's ready to execute the uncached load.
1351 if (!inst->isSquashed() && inst->isExecuted()) {
1352 int dependents = instQueue.wakeDependents(inst);
1354 for (int i = 0; i < inst->numDestRegs(); i++) {
1356 DPRINTF(IEW,"Setting Destination Register %i\n",
1357 inst->renamedDestRegIdx(i));
1358 scoreboard->setReg(inst->renamedDestRegIdx(i));
1362 producerInst[tid]++;
1363 consumerInst[tid]+= dependents;
1365 writebackCount[tid]++;
1368 decrWb(inst->seqNum);
1372 template<class Impl>
1374 DefaultIEW<Impl>::tick()
1379 wroteToTimeBuffer = false;
1380 updatedQueues = false;
1384 // Free function units marked as being freed this cycle.
1385 fuPool->processFreeUnits();
1387 list<unsigned>::iterator threads = (*activeThreads).begin();
1389 // Check stall and squash signals, dispatch any instructions.
1390 while (threads != (*activeThreads).end()) {
1391 unsigned tid = *threads++;
1393 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1395 checkSignalsAndUpdate(tid);
1399 if (exeStatus != Squashing) {
1404 // Have the instruction queue try to schedule any ready instructions.
1405 // (In actuality, this scheduling is for instructions that will
1406 // be executed next cycle.)
1407 instQueue.scheduleReadyInsts();
1409 // Also should advance its own time buffers if the stage ran.
1410 // Not the best place for it, but this works (hopefully).
1411 issueToExecQueue.advance();
1414 bool broadcast_free_entries = false;
1416 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1418 updateLSQNextCycle = false;
1420 broadcast_free_entries = true;
1423 // Writeback any stores using any leftover bandwidth.
1424 ldstQueue.writebackStores();
1426 // Check the committed load/store signals to see if there's a load
1427 // or store to commit. Also check if it's being told to execute a
1428 // nonspeculative instruction.
1429 // This is pretty inefficient...
1431 threads = (*activeThreads).begin();
1432 while (threads != (*activeThreads).end()) {
1433 unsigned tid = (*threads++);
1435 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1437 // Update structures based on instructions committed.
1438 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1439 !fromCommit->commitInfo[tid].squash &&
1440 !fromCommit->commitInfo[tid].robSquashing) {
1442 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1444 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1446 updateLSQNextCycle = true;
1447 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1450 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1452 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1453 if (fromCommit->commitInfo[tid].uncached) {
1454 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1456 instQueue.scheduleNonSpec(
1457 fromCommit->commitInfo[tid].nonSpecSeqNum);
1461 if (broadcast_free_entries) {
1462 toFetch->iewInfo[tid].iqCount =
1463 instQueue.getCount(tid);
1464 toFetch->iewInfo[tid].ldstqCount =
1465 ldstQueue.getCount(tid);
1467 toRename->iewInfo[tid].usedIQ = true;
1468 toRename->iewInfo[tid].freeIQEntries =
1469 instQueue.numFreeEntries();
1470 toRename->iewInfo[tid].usedLSQ = true;
1471 toRename->iewInfo[tid].freeLSQEntries =
1472 ldstQueue.numFreeEntries(tid);
1474 wroteToTimeBuffer = true;
1477 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1478 tid, toRename->iewInfo[tid].dispatched);
1481 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1482 "LSQ has %i free entries.\n",
1483 instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1484 ldstQueue.numFreeEntries());
1488 if (wroteToTimeBuffer) {
1489 DPRINTF(Activity, "Activity this cycle.\n");
1490 cpu->activityThisCycle();
1494 template <class Impl>
1496 DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1498 int thread_number = inst->threadNumber;
1501 // Pick off the software prefetches
1504 if (inst->isDataPrefetch())
1505 iewExecutedSwp[thread_number]++;
1507 iewIewExecutedcutedInsts++;
1513 // Control operations
1515 if (inst->isControl())
1516 iewExecutedBranches[thread_number]++;
1519 // Memory operations
1521 if (inst->isMemRef()) {
1522 iewExecutedRefs[thread_number]++;
1524 if (inst->isLoad()) {
1525 iewExecLoadInsts[thread_number]++;