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31 #ifndef __CPU_O3_INST_QUEUE_HH__
32 #define __CPU_O3_INST_QUEUE_HH__
39 #include "base/statistics.hh"
40 #include "base/timebuf.hh"
41 #include "cpu/inst_seq.hh"
42 #include "cpu/o3/dep_graph.hh"
43 #include "cpu/op_class.hh"
44 #include "sim/host.hh"
50 * A standard instruction queue class. It holds ready instructions, in
51 * order, in seperate priority queues to facilitate the scheduling of
52 * instructions. The IQ uses a separate linked list to track dependencies.
53 * Similar to the rename map and the free list, it expects that
54 * floating point registers have their indices start after the integer
55 * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
56 * and 96-191 are fp). This remains true even for both logical and
57 * physical register indices. The IQ depends on the memory dependence unit to
58 * track when memory operations are ready in terms of ordering; register
59 * dependencies are tracked normally. Right now the IQ also handles the
60 * execution timing; this is mainly to allow back-to-back scheduling without
61 * requiring IEW to be able to peek into the IQ. At the end of the execution
62 * latency, the instruction is put into the queue to execute, where it will
63 * have the execute() function called on it.
64 * @todo: Make IQ able to handle multiple FU pools.
67 class InstructionQueue
70 //Typedefs from the Impl.
71 typedef typename Impl::FullCPU FullCPU;
72 typedef typename Impl::DynInstPtr DynInstPtr;
73 typedef typename Impl::Params Params;
75 typedef typename Impl::CPUPol::IEW IEW;
76 typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
77 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
78 typedef typename Impl::CPUPol::TimeStruct TimeStruct;
80 // Typedef of iterator through the list of instructions.
81 typedef typename std::list<DynInstPtr>::iterator ListIt;
83 friend class Impl::FullCPU;
85 /** FU completion event class. */
86 class FUCompletion : public Event {
88 /** Executing instruction. */
91 /** Index of the FU used for executing. */
94 /** Pointer back to the instruction queue. */
95 InstructionQueue<Impl> *iqPtr;
97 /** Should the FU be added to the list to be freed upon
98 * completing this event.
103 /** Construct a FU completion event. */
104 FUCompletion(DynInstPtr &_inst, int fu_idx,
105 InstructionQueue<Impl> *iq_ptr);
107 virtual void process();
108 virtual const char *description();
109 void setFreeFU() { freeFU = true; }
112 /** Constructs an IQ. */
113 InstructionQueue(Params *params);
115 /** Destructs the IQ. */
118 /** Returns the name of the IQ. */
119 std::string name() const;
121 /** Registers statistics. */
124 /** Resets all instruction queue state. */
127 /** Sets CPU pointer. */
128 void setCPU(FullCPU *_cpu) { cpu = _cpu; }
130 /** Sets active threads list. */
131 void setActiveThreads(std::list<unsigned> *at_ptr);
133 /** Sets the IEW pointer. */
134 void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
136 /** Sets the timer buffer between issue and execute. */
137 void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
139 /** Sets the global time buffer. */
140 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
142 /** Switches out the instruction queue. */
145 /** Takes over execution from another CPU's thread. */
148 /** Returns if the IQ is switched out. */
149 bool isSwitchedOut() { return switchedOut; }
151 /** Number of entries needed for given amount of threads. */
152 int entryAmount(int num_threads);
154 /** Resets max entries for all threads. */
157 /** Returns total number of free entries. */
158 unsigned numFreeEntries();
160 /** Returns number of free entries for a thread. */
161 unsigned numFreeEntries(unsigned tid);
163 /** Returns whether or not the IQ is full. */
166 /** Returns whether or not the IQ is full for a specific thread. */
167 bool isFull(unsigned tid);
169 /** Returns if there are any ready instructions in the IQ. */
170 bool hasReadyInsts();
172 /** Inserts a new instruction into the IQ. */
173 void insert(DynInstPtr &new_inst);
175 /** Inserts a new, non-speculative instruction into the IQ. */
176 void insertNonSpec(DynInstPtr &new_inst);
178 /** Inserts a memory or write barrier into the IQ to make sure
179 * loads and stores are ordered properly.
181 void insertBarrier(DynInstPtr &barr_inst);
183 /** Returns the oldest scheduled instruction, and removes it from
184 * the list of instructions waiting to execute.
186 DynInstPtr getInstToExecute();
189 * Records the instruction as the producer of a register without
190 * adding it to the rest of the IQ.
192 void recordProducer(DynInstPtr &inst)
193 { addToProducers(inst); }
195 /** Process FU completion event. */
196 void processFUCompletion(DynInstPtr &inst, int fu_idx);
199 * Schedules ready instructions, adding the ready ones (oldest first) to
200 * the queue to execute.
202 void scheduleReadyInsts();
204 /** Schedules a single specific non-speculative instruction. */
205 void scheduleNonSpec(const InstSeqNum &inst);
208 * Commits all instructions up to and including the given sequence number,
209 * for a specific thread.
211 void commit(const InstSeqNum &inst, unsigned tid = 0);
213 /** Wakes all dependents of a completed instruction. */
214 int wakeDependents(DynInstPtr &completed_inst);
216 /** Adds a ready memory instruction to the ready list. */
217 void addReadyMemInst(DynInstPtr &ready_inst);
220 * Reschedules a memory instruction. It will be ready to issue once
221 * replayMemInst() is called.
223 void rescheduleMemInst(DynInstPtr &resched_inst);
225 /** Replays a memory instruction. It must be rescheduled first. */
226 void replayMemInst(DynInstPtr &replay_inst);
228 /** Completes a memory operation. */
229 void completeMemInst(DynInstPtr &completed_inst);
231 /** Indicates an ordering violation between a store and a load. */
232 void violation(DynInstPtr &store, DynInstPtr &faulting_load);
235 * Squashes instructions for a thread. Squashing information is obtained
236 * from the time buffer.
238 void squash(unsigned tid);
240 /** Returns the number of used entries for a thread. */
241 unsigned getCount(unsigned tid) { return count[tid]; };
243 /** Debug function to print all instructions. */
247 /** Does the actual squashing. */
248 void doSquash(unsigned tid);
250 /////////////////////////
252 /////////////////////////
254 /** Pointer to the CPU. */
257 /** Cache interface. */
258 MemInterface *dcacheInterface;
260 /** Pointer to IEW stage. */
263 /** The memory dependence unit, which tracks/predicts memory dependences
264 * between instructions.
266 MemDepUnit memDepUnit[Impl::MaxThreads];
268 /** The queue to the execute stage. Issued instructions will be written
271 TimeBuffer<IssueStruct> *issueToExecuteQueue;
273 /** The backwards time buffer. */
274 TimeBuffer<TimeStruct> *timeBuffer;
276 /** Wire to read information from timebuffer. */
277 typename TimeBuffer<TimeStruct>::wire fromCommit;
279 /** Function unit pool. */
282 //////////////////////////////////////
283 // Instruction lists, ready queues, and ordering
284 //////////////////////////////////////
286 /** List of all the instructions in the IQ (some of which may be issued). */
287 std::list<DynInstPtr> instList[Impl::MaxThreads];
289 /** List of instructions that are ready to be executed. */
290 std::list<DynInstPtr> instsToExecute;
293 * Struct for comparing entries to be added to the priority queue.
294 * This gives reverse ordering to the instructions in terms of
295 * sequence numbers: the instructions with smaller sequence
296 * numbers (and hence are older) will be at the top of the
300 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
302 return lhs->seqNum > rhs->seqNum;
306 typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
309 /** List of ready instructions, per op class. They are separated by op
310 * class to allow for easy mapping to FUs.
312 ReadyInstQueue readyInsts[Num_OpClasses];
314 /** List of non-speculative instructions that will be scheduled
315 * once the IQ gets a signal from commit. While it's redundant to
316 * have the key be a part of the value (the sequence number is stored
317 * inside of DynInst), when these instructions are woken up only
318 * the sequence number will be available. Thus it is most efficient to be
319 * able to search by the sequence number alone.
321 std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
323 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
325 /** Entry for the list age ordering by op class. */
326 struct ListOrderEntry {
328 InstSeqNum oldestInst;
331 /** List that contains the age order of the oldest instruction of each
332 * ready queue. Used to select the oldest instruction available
334 * @todo: Might be better to just move these entries around instead
335 * of creating new ones every time the position changes due to an
336 * instruction issuing. Not sure std::list supports this.
338 std::list<ListOrderEntry> listOrder;
340 typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
342 /** Tracks if each ready queue is on the age order list. */
343 bool queueOnList[Num_OpClasses];
345 /** Iterators of each ready queue. Points to their spot in the age order
348 ListOrderIt readyIt[Num_OpClasses];
350 /** Add an op class to the age order list. */
351 void addToOrderList(OpClass op_class);
354 * Called when the oldest instruction has been removed from a ready queue;
355 * this places that ready queue into the proper spot in the age order list.
357 void moveToYoungerInst(ListOrderIt age_order_it);
359 DependencyGraph<DynInstPtr> dependGraph;
361 //////////////////////////////////////
362 // Various parameters
363 //////////////////////////////////////
365 /** IQ Resource Sharing Policy */
372 /** IQ sharing policy for SMT. */
375 /** Number of Total Threads*/
378 /** Pointer to list of active threads. */
379 std::list<unsigned> *activeThreads;
381 /** Per Thread IQ count */
382 unsigned count[Impl::MaxThreads];
384 /** Max IQ Entries Per Thread */
385 unsigned maxEntries[Impl::MaxThreads];
387 /** Number of free IQ entries left. */
388 unsigned freeEntries;
390 /** The number of entries in the instruction queue. */
393 /** The total number of instructions that can be issued in one cycle. */
396 /** The number of physical registers in the CPU. */
397 unsigned numPhysRegs;
399 /** The number of physical integer registers in the CPU. */
400 unsigned numPhysIntRegs;
402 /** The number of floating point registers in the CPU. */
403 unsigned numPhysFloatRegs;
405 /** Delay between commit stage and the IQ.
406 * @todo: Make there be a distinction between the delays within IEW.
408 unsigned commitToIEWDelay;
410 /** Is the IQ switched out. */
413 /** The sequence number of the squashed instruction. */
414 InstSeqNum squashedSeqNum[Impl::MaxThreads];
416 /** A cache of the recently woken registers. It is 1 if the register
417 * has been woken up recently, and 0 if the register has been added
418 * to the dependency graph and has not yet received its value. It
419 * is basically a secondary scoreboard, and should pretty much mirror
420 * the scoreboard that exists in the rename map.
422 std::vector<bool> regScoreboard;
424 /** Adds an instruction to the dependency graph, as a consumer. */
425 bool addToDependents(DynInstPtr &new_inst);
427 /** Adds an instruction to the dependency graph, as a producer. */
428 void addToProducers(DynInstPtr &new_inst);
430 /** Moves an instruction to the ready queue if it is ready. */
431 void addIfReady(DynInstPtr &inst);
433 /** Debugging function to count how many entries are in the IQ. It does
434 * a linear walk through the instructions, so do not call this function
435 * during normal execution.
439 /** Debugging function to dump all the list sizes, as well as print
440 * out the list of nonspeculative instructions. Should not be used
441 * in any other capacity, but it has no harmful sideaffects.
445 /** Debugging function to dump out all instructions that are in the
450 /** Stat for number of instructions added. */
451 Stats::Scalar<> iqInstsAdded;
452 /** Stat for number of non-speculative instructions added. */
453 Stats::Scalar<> iqNonSpecInstsAdded;
455 Stats::Scalar<> iqInstsIssued;
456 /** Stat for number of integer instructions issued. */
457 Stats::Scalar<> iqIntInstsIssued;
458 /** Stat for number of floating point instructions issued. */
459 Stats::Scalar<> iqFloatInstsIssued;
460 /** Stat for number of branch instructions issued. */
461 Stats::Scalar<> iqBranchInstsIssued;
462 /** Stat for number of memory instructions issued. */
463 Stats::Scalar<> iqMemInstsIssued;
464 /** Stat for number of miscellaneous instructions issued. */
465 Stats::Scalar<> iqMiscInstsIssued;
466 /** Stat for number of squashed instructions that were ready to issue. */
467 Stats::Scalar<> iqSquashedInstsIssued;
468 /** Stat for number of squashed instructions examined when squashing. */
469 Stats::Scalar<> iqSquashedInstsExamined;
470 /** Stat for number of squashed instruction operands examined when
473 Stats::Scalar<> iqSquashedOperandsExamined;
474 /** Stat for number of non-speculative instructions removed due to a squash.
476 Stats::Scalar<> iqSquashedNonSpecRemoved;
478 /** Distribution of number of instructions in the queue. */
479 Stats::VectorDistribution<> queueResDist;
480 /** Distribution of the number of instructions issued. */
481 Stats::Distribution<> numIssuedDist;
482 /** Distribution of the cycles it takes to issue an instruction. */
483 Stats::VectorDistribution<> issueDelayDist;
485 /** Number of times an instruction could not be issued because a
488 Stats::Vector<> statFuBusy;
489 // Stats::Vector<> dist_unissued;
490 /** Stat for total number issued for each instruction type. */
491 Stats::Vector2d<> statIssuedInstType;
493 /** Number of instructions issued per cycle. */
494 Stats::Formula issueRate;
495 // Stats::Formula issue_stores;
496 // Stats::Formula issue_op_rate;
497 /** Number of times the FU was busy. */
498 Stats::Vector<> fuBusy;
499 /** Number of times the FU was busy per instruction issued. */
500 Stats::Formula fuBusyRate;
503 #endif //__CPU_O3_INST_QUEUE_HH__