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47 #include "cpu/o3/fu_pool.hh"
48 #include "cpu/o3/inst_queue.hh"
49 #include "debug/IQ.hh"
50 #include "enums/OpClass.hh"
51 #include "params/DerivO3CPU.hh"
52 #include "sim/core.hh"
54 // clang complains about std::set being overloaded with Packet::set if
55 // we open up the entire namespace std
59 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
60 int fu_idx, InstructionQueue<Impl> *iq_ptr)
61 : Event(Stat_Event_Pri, AutoDelete),
62 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
68 InstructionQueue<Impl>::FUCompletion::process()
70 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
77 InstructionQueue<Impl>::FUCompletion::description() const
79 return "Functional unit completion";
83 InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
84 DerivO3CPUParams *params)
87 fuPool(params->fuPool),
88 numEntries(params->numIQEntries),
89 totalWidth(params->issueWidth),
90 numPhysIntRegs(params->numPhysIntRegs),
91 numPhysFloatRegs(params->numPhysFloatRegs),
92 commitToIEWDelay(params->commitToIEWDelay)
96 numThreads = params->numThreads;
98 // Set the number of physical registers as the number of int + float
99 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
101 //Create an entry for each physical register within the
103 dependGraph.resize(numPhysRegs);
105 // Resize the register scoreboard.
106 regScoreboard.resize(numPhysRegs);
108 //Initialize Mem Dependence Units
109 for (ThreadID tid = 0; tid < numThreads; tid++) {
110 memDepUnit[tid].init(params, tid);
111 memDepUnit[tid].setIQ(this);
116 std::string policy = params->smtIQPolicy;
118 //Convert string to lowercase
119 std::transform(policy.begin(), policy.end(), policy.begin(),
120 (int(*)(int)) tolower);
122 //Figure out resource sharing policy
123 if (policy == "dynamic") {
126 //Set Max Entries to Total ROB Capacity
127 for (ThreadID tid = 0; tid < numThreads; tid++) {
128 maxEntries[tid] = numEntries;
131 } else if (policy == "partitioned") {
132 iqPolicy = Partitioned;
134 //@todo:make work if part_amt doesnt divide evenly.
135 int part_amt = numEntries / numThreads;
137 //Divide ROB up evenly
138 for (ThreadID tid = 0; tid < numThreads; tid++) {
139 maxEntries[tid] = part_amt;
142 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
143 "%i entries per thread.\n",part_amt);
144 } else if (policy == "threshold") {
145 iqPolicy = Threshold;
147 double threshold = (double)params->smtIQThreshold / 100;
149 int thresholdIQ = (int)((double)threshold * numEntries);
151 //Divide up by threshold amount
152 for (ThreadID tid = 0; tid < numThreads; tid++) {
153 maxEntries[tid] = thresholdIQ;
156 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
157 "%i entries per thread.\n",thresholdIQ);
159 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
160 "Partitioned, Threshold}");
164 template <class Impl>
165 InstructionQueue<Impl>::~InstructionQueue()
169 cprintf("Nodes traversed: %i, removed: %i\n",
170 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
174 template <class Impl>
176 InstructionQueue<Impl>::name() const
178 return cpu->name() + ".iq";
181 template <class Impl>
183 InstructionQueue<Impl>::regStats()
185 using namespace Stats;
187 .name(name() + ".iqInstsAdded")
188 .desc("Number of instructions added to the IQ (excludes non-spec)")
189 .prereq(iqInstsAdded);
192 .name(name() + ".iqNonSpecInstsAdded")
193 .desc("Number of non-speculative instructions added to the IQ")
194 .prereq(iqNonSpecInstsAdded);
197 .name(name() + ".iqInstsIssued")
198 .desc("Number of instructions issued")
199 .prereq(iqInstsIssued);
202 .name(name() + ".iqIntInstsIssued")
203 .desc("Number of integer instructions issued")
204 .prereq(iqIntInstsIssued);
207 .name(name() + ".iqFloatInstsIssued")
208 .desc("Number of float instructions issued")
209 .prereq(iqFloatInstsIssued);
212 .name(name() + ".iqBranchInstsIssued")
213 .desc("Number of branch instructions issued")
214 .prereq(iqBranchInstsIssued);
217 .name(name() + ".iqMemInstsIssued")
218 .desc("Number of memory instructions issued")
219 .prereq(iqMemInstsIssued);
222 .name(name() + ".iqMiscInstsIssued")
223 .desc("Number of miscellaneous instructions issued")
224 .prereq(iqMiscInstsIssued);
226 iqSquashedInstsIssued
227 .name(name() + ".iqSquashedInstsIssued")
228 .desc("Number of squashed instructions issued")
229 .prereq(iqSquashedInstsIssued);
231 iqSquashedInstsExamined
232 .name(name() + ".iqSquashedInstsExamined")
233 .desc("Number of squashed instructions iterated over during squash;"
234 " mainly for profiling")
235 .prereq(iqSquashedInstsExamined);
237 iqSquashedOperandsExamined
238 .name(name() + ".iqSquashedOperandsExamined")
239 .desc("Number of squashed operands that are examined and possibly "
240 "removed from graph")
241 .prereq(iqSquashedOperandsExamined);
243 iqSquashedNonSpecRemoved
244 .name(name() + ".iqSquashedNonSpecRemoved")
245 .desc("Number of squashed non-spec instructions that were removed")
246 .prereq(iqSquashedNonSpecRemoved);
249 .init(Num_OpClasses, 0, 99, 2)
250 .name(name() + ".IQ:residence:")
251 .desc("cycles from dispatch to issue")
252 .flags(total | pdf | cdf )
254 for (int i = 0; i < Num_OpClasses; ++i) {
255 queueResDist.subname(i, opClassStrings[i]);
259 .init(0,totalWidth,1)
260 .name(name() + ".issued_per_cycle")
261 .desc("Number of insts issued each cycle")
266 .init(Num_OpClasses+2)
267 .name(name() + ".unissued_cause")
268 .desc("Reason ready instruction not issued")
271 for (int i=0; i < (Num_OpClasses + 2); ++i) {
272 dist_unissued.subname(i, unissued_names[i]);
276 .init(numThreads,Enums::Num_OpClass)
277 .name(name() + ".FU_type")
278 .desc("Type of FU issued")
279 .flags(total | pdf | dist)
281 statIssuedInstType.ysubnames(Enums::OpClassStrings);
284 // How long did instructions for a particular FU type wait prior to issue
288 .init(Num_OpClasses,0,99,2)
290 .desc("cycles from operands ready to issue")
294 for (int i=0; i<Num_OpClasses; ++i) {
295 std::stringstream subname;
296 subname << opClassStrings[i] << "_delay";
297 issueDelayDist.subname(i, subname.str());
301 .name(name() + ".rate")
302 .desc("Inst issue rate")
305 issueRate = iqInstsIssued / cpu->numCycles;
309 .name(name() + ".fu_full")
310 .desc("attempts to use FU when none available")
313 for (int i=0; i < Num_OpClasses; ++i) {
314 statFuBusy.subname(i, Enums::OpClassStrings[i]);
319 .name(name() + ".fu_busy_cnt")
320 .desc("FU busy when requested")
325 .name(name() + ".fu_busy_rate")
326 .desc("FU busy rate (busy events/executed inst)")
329 fuBusyRate = fuBusy / iqInstsIssued;
331 for (ThreadID tid = 0; tid < numThreads; tid++) {
332 // Tell mem dependence unit to reg stats as well.
333 memDepUnit[tid].regStats();
337 .name(name() + ".int_inst_queue_reads")
338 .desc("Number of integer instruction queue reads")
342 .name(name() + ".int_inst_queue_writes")
343 .desc("Number of integer instruction queue writes")
346 intInstQueueWakeupAccesses
347 .name(name() + ".int_inst_queue_wakeup_accesses")
348 .desc("Number of integer instruction queue wakeup accesses")
352 .name(name() + ".fp_inst_queue_reads")
353 .desc("Number of floating instruction queue reads")
357 .name(name() + ".fp_inst_queue_writes")
358 .desc("Number of floating instruction queue writes")
361 fpInstQueueWakeupQccesses
362 .name(name() + ".fp_inst_queue_wakeup_accesses")
363 .desc("Number of floating instruction queue wakeup accesses")
367 .name(name() + ".int_alu_accesses")
368 .desc("Number of integer alu accesses")
372 .name(name() + ".fp_alu_accesses")
373 .desc("Number of floating point alu accesses")
378 template <class Impl>
380 InstructionQueue<Impl>::resetState()
382 //Initialize thread IQ counts
383 for (ThreadID tid = 0; tid <numThreads; tid++) {
385 instList[tid].clear();
388 // Initialize the number of free IQ entries.
389 freeEntries = numEntries;
391 // Note that in actuality, the registers corresponding to the logical
392 // registers start off as ready. However this doesn't matter for the
393 // IQ as the instruction should have been correctly told if those
394 // registers are ready in rename. Thus it can all be initialized as
396 for (int i = 0; i < numPhysRegs; ++i) {
397 regScoreboard[i] = false;
400 for (ThreadID tid = 0; tid < numThreads; ++tid) {
401 squashedSeqNum[tid] = 0;
404 for (int i = 0; i < Num_OpClasses; ++i) {
405 while (!readyInsts[i].empty())
407 queueOnList[i] = false;
408 readyIt[i] = listOrder.end();
410 nonSpecInsts.clear();
412 deferredMemInsts.clear();
415 template <class Impl>
417 InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
419 activeThreads = at_ptr;
422 template <class Impl>
424 InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
426 issueToExecuteQueue = i2e_ptr;
429 template <class Impl>
431 InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
435 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
438 template <class Impl>
440 InstructionQueue<Impl>::drainSanityCheck() const
442 assert(dependGraph.empty());
443 assert(instsToExecute.empty());
444 for (ThreadID tid = 0; tid < numThreads; ++tid)
445 memDepUnit[tid].drainSanityCheck();
448 template <class Impl>
450 InstructionQueue<Impl>::takeOverFrom()
455 template <class Impl>
457 InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
459 if (iqPolicy == Partitioned) {
460 return numEntries / num_threads;
467 template <class Impl>
469 InstructionQueue<Impl>::resetEntries()
471 if (iqPolicy != Dynamic || numThreads > 1) {
472 int active_threads = activeThreads->size();
474 list<ThreadID>::iterator threads = activeThreads->begin();
475 list<ThreadID>::iterator end = activeThreads->end();
477 while (threads != end) {
478 ThreadID tid = *threads++;
480 if (iqPolicy == Partitioned) {
481 maxEntries[tid] = numEntries / active_threads;
482 } else if(iqPolicy == Threshold && active_threads == 1) {
483 maxEntries[tid] = numEntries;
489 template <class Impl>
491 InstructionQueue<Impl>::numFreeEntries()
496 template <class Impl>
498 InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
500 return maxEntries[tid] - count[tid];
503 // Might want to do something more complex if it knows how many instructions
504 // will be issued this cycle.
505 template <class Impl>
507 InstructionQueue<Impl>::isFull()
509 if (freeEntries == 0) {
516 template <class Impl>
518 InstructionQueue<Impl>::isFull(ThreadID tid)
520 if (numFreeEntries(tid) == 0) {
527 template <class Impl>
529 InstructionQueue<Impl>::hasReadyInsts()
531 if (!listOrder.empty()) {
535 for (int i = 0; i < Num_OpClasses; ++i) {
536 if (!readyInsts[i].empty()) {
544 template <class Impl>
546 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
548 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
549 // Make sure the instruction is valid
552 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
553 new_inst->seqNum, new_inst->pcState());
555 assert(freeEntries != 0);
557 instList[new_inst->threadNumber].push_back(new_inst);
563 // Look through its source registers (physical regs), and mark any
565 addToDependents(new_inst);
567 // Have this instruction set itself as the producer of its destination
569 addToProducers(new_inst);
571 if (new_inst->isMemRef()) {
572 memDepUnit[new_inst->threadNumber].insert(new_inst);
574 addIfReady(new_inst);
579 count[new_inst->threadNumber]++;
581 assert(freeEntries == (numEntries - countInsts()));
584 template <class Impl>
586 InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
588 // @todo: Clean up this code; can do it by setting inst as unable
589 // to issue, then calling normal insert on the inst.
590 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
594 nonSpecInsts[new_inst->seqNum] = new_inst;
596 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
598 new_inst->seqNum, new_inst->pcState());
600 assert(freeEntries != 0);
602 instList[new_inst->threadNumber].push_back(new_inst);
608 // Have this instruction set itself as the producer of its destination
610 addToProducers(new_inst);
612 // If it's a memory instruction, add it to the memory dependency
614 if (new_inst->isMemRef()) {
615 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
618 ++iqNonSpecInstsAdded;
620 count[new_inst->threadNumber]++;
622 assert(freeEntries == (numEntries - countInsts()));
625 template <class Impl>
627 InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
629 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
631 insertNonSpec(barr_inst);
634 template <class Impl>
635 typename Impl::DynInstPtr
636 InstructionQueue<Impl>::getInstToExecute()
638 assert(!instsToExecute.empty());
639 DynInstPtr inst = instsToExecute.front();
640 instsToExecute.pop_front();
641 if (inst->isFloating()){
649 template <class Impl>
651 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
653 assert(!readyInsts[op_class].empty());
655 ListOrderEntry queue_entry;
657 queue_entry.queueType = op_class;
659 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
661 ListOrderIt list_it = listOrder.begin();
662 ListOrderIt list_end_it = listOrder.end();
664 while (list_it != list_end_it) {
665 if ((*list_it).oldestInst > queue_entry.oldestInst) {
672 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
673 queueOnList[op_class] = true;
676 template <class Impl>
678 InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
680 // Get iterator of next item on the list
681 // Delete the original iterator
682 // Determine if the next item is either the end of the list or younger
683 // than the new instruction. If so, then add in a new iterator right here.
684 // If not, then move along.
685 ListOrderEntry queue_entry;
686 OpClass op_class = (*list_order_it).queueType;
687 ListOrderIt next_it = list_order_it;
691 queue_entry.queueType = op_class;
692 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
694 while (next_it != listOrder.end() &&
695 (*next_it).oldestInst < queue_entry.oldestInst) {
699 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
702 template <class Impl>
704 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
706 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
707 assert(!cpu->switchedOut());
708 // The CPU could have been sleeping until this op completed (*extremely*
709 // long latency op). Wake it if it was. This may be overkill.
713 fuPool->freeUnitNextCycle(fu_idx);
715 // @todo: Ensure that these FU Completions happen at the beginning
716 // of a cycle, otherwise they could add too many instructions to
718 issueToExecuteQueue->access(-1)->size++;
719 instsToExecute.push_back(inst);
722 // @todo: Figure out a better way to remove the squashed items from the
723 // lists. Checking the top item of each list to see if it's squashed
724 // wastes time and forces jumps.
725 template <class Impl>
727 InstructionQueue<Impl>::scheduleReadyInsts()
729 DPRINTF(IQ, "Attempting to schedule ready instructions from "
732 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
734 DynInstPtr deferred_mem_inst;
735 int total_deferred_mem_issued = 0;
736 while (total_deferred_mem_issued < totalWidth &&
737 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) {
738 issueToExecuteQueue->access(0)->size++;
739 instsToExecute.push_back(deferred_mem_inst);
740 total_deferred_mem_issued++;
743 // Have iterator to head of the list
744 // While I haven't exceeded bandwidth or reached the end of the list,
745 // Try to get a FU that can do what this op needs.
746 // If successful, change the oldestInst to the new top of the list, put
747 // the queue in the proper place in the list.
748 // Increment the iterator.
749 // This will avoid trying to schedule a certain op class if there are no
750 // FUs that handle it.
751 ListOrderIt order_it = listOrder.begin();
752 ListOrderIt order_end_it = listOrder.end();
753 int total_issued = 0;
755 while (total_issued < (totalWidth - total_deferred_mem_issued) &&
756 iewStage->canIssue() &&
757 order_it != order_end_it) {
758 OpClass op_class = (*order_it).queueType;
760 assert(!readyInsts[op_class].empty());
762 DynInstPtr issuing_inst = readyInsts[op_class].top();
764 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
766 assert(issuing_inst->seqNum == (*order_it).oldestInst);
768 if (issuing_inst->isSquashed()) {
769 readyInsts[op_class].pop();
771 if (!readyInsts[op_class].empty()) {
772 moveToYoungerInst(order_it);
774 readyIt[op_class] = listOrder.end();
775 queueOnList[op_class] = false;
778 listOrder.erase(order_it++);
780 ++iqSquashedInstsIssued;
786 Cycles op_latency = Cycles(1);
787 ThreadID tid = issuing_inst->threadNumber;
789 if (op_class != No_OpClass) {
790 idx = fuPool->getUnit(op_class);
791 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
793 op_latency = fuPool->getOpLatency(op_class);
797 // If we have an instruction that doesn't require a FU, or a
798 // valid FU, then schedule for execution.
799 if (idx == -2 || idx != -1) {
800 if (op_latency == Cycles(1)) {
802 instsToExecute.push_back(issuing_inst);
804 // Add the FU onto the list of FU's to be freed next
805 // cycle if we used one.
807 fuPool->freeUnitNextCycle(idx);
809 Cycles issue_latency = fuPool->getIssueLatency(op_class);
810 // Generate completion event for the FU
811 FUCompletion *execution = new FUCompletion(issuing_inst,
814 cpu->schedule(execution,
815 cpu->clockEdge(Cycles(op_latency - 1)));
817 // @todo: Enforce that issue_latency == 1 or op_latency
818 if (issue_latency > Cycles(1)) {
819 // If FU isn't pipelined, then it must be freed
820 // upon the execution completing.
821 execution->setFreeFU();
823 // Add the FU onto the list of FU's to be freed next cycle.
824 fuPool->freeUnitNextCycle(idx);
828 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
830 tid, issuing_inst->pcState(),
831 issuing_inst->seqNum);
833 readyInsts[op_class].pop();
835 if (!readyInsts[op_class].empty()) {
836 moveToYoungerInst(order_it);
838 readyIt[op_class] = listOrder.end();
839 queueOnList[op_class] = false;
842 issuing_inst->setIssued();
846 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
849 if (!issuing_inst->isMemRef()) {
850 // Memory instructions can not be freed from the IQ until they
854 issuing_inst->clearInIQ();
856 memDepUnit[tid].issue(issuing_inst);
859 listOrder.erase(order_it++);
860 statIssuedInstType[tid][op_class]++;
861 iewStage->incrWb(issuing_inst->seqNum);
863 statFuBusy[op_class]++;
869 numIssuedDist.sample(total_issued);
870 iqInstsIssued+= total_issued;
872 // If we issued any instructions, tell the CPU we had activity.
873 // @todo If the way deferred memory instructions are handeled due to
874 // translation changes then the deferredMemInsts condition should be removed
875 // from the code below.
876 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
877 cpu->activityThisCycle();
879 DPRINTF(IQ, "Not able to schedule any instructions.\n");
883 template <class Impl>
885 InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
887 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
888 "to execute.\n", inst);
890 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
892 assert(inst_it != nonSpecInsts.end());
894 ThreadID tid = (*inst_it).second->threadNumber;
896 (*inst_it).second->setAtCommit();
898 (*inst_it).second->setCanIssue();
900 if (!(*inst_it).second->isMemRef()) {
901 addIfReady((*inst_it).second);
903 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
906 (*inst_it).second = NULL;
908 nonSpecInsts.erase(inst_it);
911 template <class Impl>
913 InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
915 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
918 ListIt iq_it = instList[tid].begin();
920 while (iq_it != instList[tid].end() &&
921 (*iq_it)->seqNum <= inst) {
923 instList[tid].pop_front();
926 assert(freeEntries == (numEntries - countInsts()));
929 template <class Impl>
931 InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
935 // The instruction queue here takes care of both floating and int ops
936 if (completed_inst->isFloating()) {
937 fpInstQueueWakeupQccesses++;
939 intInstQueueWakeupAccesses++;
942 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
944 assert(!completed_inst->isSquashed());
946 // Tell the memory dependence unit to wake any dependents on this
947 // instruction if it is a memory instruction. Also complete the memory
948 // instruction at this point since we know it executed without issues.
949 // @todo: Might want to rename "completeMemInst" to something that
950 // indicates that it won't need to be replayed, and call this
951 // earlier. Might not be a big deal.
952 if (completed_inst->isMemRef()) {
953 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
954 completeMemInst(completed_inst);
955 } else if (completed_inst->isMemBarrier() ||
956 completed_inst->isWriteBarrier()) {
957 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
960 for (int dest_reg_idx = 0;
961 dest_reg_idx < completed_inst->numDestRegs();
964 PhysRegIndex dest_reg =
965 completed_inst->renamedDestRegIdx(dest_reg_idx);
967 // Special case of uniq or control registers. They are not
968 // handled by the IQ and thus have no dependency graph entry.
969 // @todo Figure out a cleaner way to handle this.
970 if (dest_reg >= numPhysRegs) {
971 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
976 DPRINTF(IQ, "Waking any dependents on register %i.\n",
979 //Go through the dependency chain, marking the registers as
980 //ready within the waiting instructions.
981 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
984 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
985 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
987 // Might want to give more information to the instruction
988 // so that it knows which of its source registers is
989 // ready. However that would mean that the dependency
990 // graph entries would need to hold the src_reg_idx.
991 dep_inst->markSrcRegReady();
993 addIfReady(dep_inst);
995 dep_inst = dependGraph.pop(dest_reg);
1000 // Reset the head node now that all of its dependents have
1002 assert(dependGraph.empty(dest_reg));
1003 dependGraph.clearInst(dest_reg);
1005 // Mark the scoreboard as having that register ready.
1006 regScoreboard[dest_reg] = true;
1011 template <class Impl>
1013 InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1015 OpClass op_class = ready_inst->opClass();
1017 readyInsts[op_class].push(ready_inst);
1019 // Will need to reorder the list if either a queue is not on the list,
1020 // or it has an older instruction than last time.
1021 if (!queueOnList[op_class]) {
1022 addToOrderList(op_class);
1023 } else if (readyInsts[op_class].top()->seqNum <
1024 (*readyIt[op_class]).oldestInst) {
1025 listOrder.erase(readyIt[op_class]);
1026 addToOrderList(op_class);
1029 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1030 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1031 ready_inst->pcState(), op_class, ready_inst->seqNum);
1034 template <class Impl>
1036 InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1038 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1040 // Reset DTB translation state
1041 resched_inst->translationStarted(false);
1042 resched_inst->translationCompleted(false);
1044 resched_inst->clearCanIssue();
1045 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1048 template <class Impl>
1050 InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1052 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
1055 template <class Impl>
1057 InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1059 ThreadID tid = completed_inst->threadNumber;
1061 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1062 completed_inst->pcState(), completed_inst->seqNum);
1066 completed_inst->memOpDone(true);
1068 memDepUnit[tid].completed(completed_inst);
1072 template <class Impl>
1074 InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1076 deferredMemInsts.push_back(deferred_inst);
1079 template <class Impl>
1080 typename Impl::DynInstPtr
1081 InstructionQueue<Impl>::getDeferredMemInstToExecute()
1083 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1085 if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1086 DynInstPtr ret = *it;
1087 deferredMemInsts.erase(it);
1094 template <class Impl>
1096 InstructionQueue<Impl>::violation(DynInstPtr &store,
1097 DynInstPtr &faulting_load)
1099 intInstQueueWrites++;
1100 memDepUnit[store->threadNumber].violation(store, faulting_load);
1103 template <class Impl>
1105 InstructionQueue<Impl>::squash(ThreadID tid)
1107 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1110 // Read instruction sequence number of last instruction out of the
1112 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1114 // Call doSquash if there are insts in the IQ
1115 if (count[tid] > 0) {
1119 // Also tell the memory dependence unit to squash.
1120 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1123 template <class Impl>
1125 InstructionQueue<Impl>::doSquash(ThreadID tid)
1127 // Start at the tail.
1128 ListIt squash_it = instList[tid].end();
1131 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1132 tid, squashedSeqNum[tid]);
1134 // Squash any instructions younger than the squashed sequence number
1136 while (squash_it != instList[tid].end() &&
1137 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1139 DynInstPtr squashed_inst = (*squash_it);
1140 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1142 // Only handle the instruction if it actually is in the IQ and
1143 // hasn't already been squashed in the IQ.
1144 if (squashed_inst->threadNumber != tid ||
1145 squashed_inst->isSquashedInIQ()) {
1150 if (!squashed_inst->isIssued() ||
1151 (squashed_inst->isMemRef() &&
1152 !squashed_inst->memOpDone())) {
1154 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1155 tid, squashed_inst->seqNum, squashed_inst->pcState());
1157 // Remove the instruction from the dependency list.
1158 if (!squashed_inst->isNonSpeculative() &&
1159 !squashed_inst->isStoreConditional() &&
1160 !squashed_inst->isMemBarrier() &&
1161 !squashed_inst->isWriteBarrier()) {
1163 for (int src_reg_idx = 0;
1164 src_reg_idx < squashed_inst->numSrcRegs();
1167 PhysRegIndex src_reg =
1168 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1170 // Only remove it from the dependency graph if it
1171 // was placed there in the first place.
1173 // Instead of doing a linked list traversal, we
1174 // can just remove these squashed instructions
1175 // either at issue time, or when the register is
1176 // overwritten. The only downside to this is it
1177 // leaves more room for error.
1179 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1180 src_reg < numPhysRegs) {
1181 dependGraph.remove(src_reg, squashed_inst);
1185 ++iqSquashedOperandsExamined;
1187 } else if (!squashed_inst->isStoreConditional() ||
1188 !squashed_inst->isCompleted()) {
1189 NonSpecMapIt ns_inst_it =
1190 nonSpecInsts.find(squashed_inst->seqNum);
1192 if (ns_inst_it == nonSpecInsts.end()) {
1193 assert(squashed_inst->getFault() != NoFault);
1196 (*ns_inst_it).second = NULL;
1198 nonSpecInsts.erase(ns_inst_it);
1200 ++iqSquashedNonSpecRemoved;
1204 // Might want to also clear out the head of the dependency graph.
1206 // Mark it as squashed within the IQ.
1207 squashed_inst->setSquashedInIQ();
1209 // @todo: Remove this hack where several statuses are set so the
1210 // inst will flow through the rest of the pipeline.
1211 squashed_inst->setIssued();
1212 squashed_inst->setCanCommit();
1213 squashed_inst->clearInIQ();
1215 //Update Thread IQ Count
1216 count[squashed_inst->threadNumber]--;
1221 instList[tid].erase(squash_it--);
1222 ++iqSquashedInstsExamined;
1226 template <class Impl>
1228 InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1230 // Loop through the instruction's source registers, adding
1231 // them to the dependency list if they are not ready.
1232 int8_t total_src_regs = new_inst->numSrcRegs();
1233 bool return_val = false;
1235 for (int src_reg_idx = 0;
1236 src_reg_idx < total_src_regs;
1239 // Only add it to the dependency graph if it's not ready.
1240 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1241 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1243 // Check the IQ's scoreboard to make sure the register
1244 // hasn't become ready while the instruction was in flight
1245 // between stages. Only if it really isn't ready should
1246 // it be added to the dependency graph.
1247 if (src_reg >= numPhysRegs) {
1249 } else if (regScoreboard[src_reg] == false) {
1250 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1251 "is being added to the dependency chain.\n",
1252 new_inst->pcState(), src_reg);
1254 dependGraph.insert(src_reg, new_inst);
1256 // Change the return value to indicate that something
1257 // was added to the dependency graph.
1260 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1261 "became ready before it reached the IQ.\n",
1262 new_inst->pcState(), src_reg);
1263 // Mark a register ready within the instruction.
1264 new_inst->markSrcRegReady(src_reg_idx);
1272 template <class Impl>
1274 InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1276 // Nothing really needs to be marked when an instruction becomes
1277 // the producer of a register's value, but for convenience a ptr
1278 // to the producing instruction will be placed in the head node of
1279 // the dependency links.
1280 int8_t total_dest_regs = new_inst->numDestRegs();
1282 for (int dest_reg_idx = 0;
1283 dest_reg_idx < total_dest_regs;
1286 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1288 // Instructions that use the misc regs will have a reg number
1289 // higher than the normal physical registers. In this case these
1290 // registers are not renamed, and there is no need to track
1291 // dependencies as these instructions must be executed at commit.
1292 if (dest_reg >= numPhysRegs) {
1296 if (!dependGraph.empty(dest_reg)) {
1298 panic("Dependency graph %i not empty!", dest_reg);
1301 dependGraph.setInst(dest_reg, new_inst);
1303 // Mark the scoreboard to say it's not yet ready.
1304 regScoreboard[dest_reg] = false;
1308 template <class Impl>
1310 InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1312 // If the instruction now has all of its source registers
1313 // available, then add it to the list of ready instructions.
1314 if (inst->readyToIssue()) {
1316 //Add the instruction to the proper ready list.
1317 if (inst->isMemRef()) {
1319 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1321 // Message to the mem dependence unit that this instruction has
1322 // its registers ready.
1323 memDepUnit[inst->threadNumber].regsReady(inst);
1328 OpClass op_class = inst->opClass();
1330 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1331 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1332 inst->pcState(), op_class, inst->seqNum);
1334 readyInsts[op_class].push(inst);
1336 // Will need to reorder the list if either a queue is not on the list,
1337 // or it has an older instruction than last time.
1338 if (!queueOnList[op_class]) {
1339 addToOrderList(op_class);
1340 } else if (readyInsts[op_class].top()->seqNum <
1341 (*readyIt[op_class]).oldestInst) {
1342 listOrder.erase(readyIt[op_class]);
1343 addToOrderList(op_class);
1348 template <class Impl>
1350 InstructionQueue<Impl>::countInsts()
1353 //ksewell:This works but definitely could use a cleaner write
1354 //with a more intuitive way of counting. Right now it's
1355 //just brute force ....
1356 // Change the #if if you want to use this method.
1357 int total_insts = 0;
1359 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1360 ListIt count_it = instList[tid].begin();
1362 while (count_it != instList[tid].end()) {
1363 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1364 if (!(*count_it)->isIssued()) {
1366 } else if ((*count_it)->isMemRef() &&
1367 !(*count_it)->memOpDone) {
1368 // Loads that have not been marked as executed still count
1369 // towards the total instructions.
1380 return numEntries - freeEntries;
1384 template <class Impl>
1386 InstructionQueue<Impl>::dumpLists()
1388 for (int i = 0; i < Num_OpClasses; ++i) {
1389 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1394 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1396 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1397 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1399 cprintf("Non speculative list: ");
1401 while (non_spec_it != non_spec_end_it) {
1402 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1403 (*non_spec_it).second->seqNum);
1409 ListOrderIt list_order_it = listOrder.begin();
1410 ListOrderIt list_order_end_it = listOrder.end();
1413 cprintf("List order: ");
1415 while (list_order_it != list_order_end_it) {
1416 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1417 (*list_order_it).oldestInst);
1427 template <class Impl>
1429 InstructionQueue<Impl>::dumpInsts()
1431 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1434 ListIt inst_list_it = instList[tid].begin();
1436 while (inst_list_it != instList[tid].end()) {
1437 cprintf("Instruction:%i\n", num);
1438 if (!(*inst_list_it)->isSquashed()) {
1439 if (!(*inst_list_it)->isIssued()) {
1441 cprintf("Count:%i\n", valid_num);
1442 } else if ((*inst_list_it)->isMemRef() &&
1443 !(*inst_list_it)->memOpDone()) {
1444 // Loads that have not been marked as executed
1445 // still count towards the total instructions.
1447 cprintf("Count:%i\n", valid_num);
1451 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1452 "Issued:%i\nSquashed:%i\n",
1453 (*inst_list_it)->pcState(),
1454 (*inst_list_it)->seqNum,
1455 (*inst_list_it)->threadNumber,
1456 (*inst_list_it)->isIssued(),
1457 (*inst_list_it)->isSquashed());
1459 if ((*inst_list_it)->isMemRef()) {
1460 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1470 cprintf("Insts to Execute list:\n");
1474 ListIt inst_list_it = instsToExecute.begin();
1476 while (inst_list_it != instsToExecute.end())
1478 cprintf("Instruction:%i\n",
1480 if (!(*inst_list_it)->isSquashed()) {
1481 if (!(*inst_list_it)->isIssued()) {
1483 cprintf("Count:%i\n", valid_num);
1484 } else if ((*inst_list_it)->isMemRef() &&
1485 !(*inst_list_it)->memOpDone()) {
1486 // Loads that have not been marked as executed
1487 // still count towards the total instructions.
1489 cprintf("Count:%i\n", valid_num);
1493 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1494 "Issued:%i\nSquashed:%i\n",
1495 (*inst_list_it)->pcState(),
1496 (*inst_list_it)->seqNum,
1497 (*inst_list_it)->threadNumber,
1498 (*inst_list_it)->isIssued(),
1499 (*inst_list_it)->isSquashed());
1501 if ((*inst_list_it)->isMemRef()) {
1502 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());