2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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35 #include "sim/core.hh"
37 #include "cpu/o3/fu_pool.hh"
38 #include "cpu/o3/inst_queue.hh"
41 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
43 InstructionQueue<Impl> *iq_ptr)
44 : Event(&mainEventQueue, Stat_Event_Pri),
45 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
47 this->setFlags(Event::AutoDelete);
52 InstructionQueue<Impl>::FUCompletion::process()
54 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
61 InstructionQueue<Impl>::FUCompletion::description()
63 return "Functional unit completion event";
67 InstructionQueue<Impl>::InstructionQueue(Params *params)
68 : fuPool(params->fuPool),
69 numEntries(params->numIQEntries),
70 totalWidth(params->issueWidth),
71 numPhysIntRegs(params->numPhysIntRegs),
72 numPhysFloatRegs(params->numPhysFloatRegs),
73 commitToIEWDelay(params->commitToIEWDelay)
79 numThreads = params->numberOfThreads;
81 // Set the number of physical registers as the number of int + float
82 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
84 //Create an entry for each physical register within the
86 dependGraph.resize(numPhysRegs);
88 // Resize the register scoreboard.
89 regScoreboard.resize(numPhysRegs);
91 //Initialize Mem Dependence Units
92 for (int i = 0; i < numThreads; i++) {
93 memDepUnit[i].init(params,i);
94 memDepUnit[i].setIQ(this);
99 std::string policy = params->smtIQPolicy;
101 //Convert string to lowercase
102 std::transform(policy.begin(), policy.end(), policy.begin(),
103 (int(*)(int)) tolower);
105 //Figure out resource sharing policy
106 if (policy == "dynamic") {
109 //Set Max Entries to Total ROB Capacity
110 for (int i = 0; i < numThreads; i++) {
111 maxEntries[i] = numEntries;
114 } else if (policy == "partitioned") {
115 iqPolicy = Partitioned;
117 //@todo:make work if part_amt doesnt divide evenly.
118 int part_amt = numEntries / numThreads;
120 //Divide ROB up evenly
121 for (int i = 0; i < numThreads; i++) {
122 maxEntries[i] = part_amt;
126 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
127 "%i entries per thread.\n",part_amt);
130 } else if (policy == "threshold") {
131 iqPolicy = Threshold;
133 double threshold = (double)params->smtIQThreshold / 100;
135 int thresholdIQ = (int)((double)threshold * numEntries);
137 //Divide up by threshold amount
138 for (int i = 0; i < numThreads; i++) {
139 maxEntries[i] = thresholdIQ;
143 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
144 "%i entries per thread.\n",thresholdIQ);
147 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
148 "Partitioned, Threshold}");
152 template <class Impl>
153 InstructionQueue<Impl>::~InstructionQueue()
157 cprintf("Nodes traversed: %i, removed: %i\n",
158 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
162 template <class Impl>
164 InstructionQueue<Impl>::name() const
166 return cpu->name() + ".iq";
169 template <class Impl>
171 InstructionQueue<Impl>::regStats()
173 using namespace Stats;
175 .name(name() + ".iqInstsAdded")
176 .desc("Number of instructions added to the IQ (excludes non-spec)")
177 .prereq(iqInstsAdded);
180 .name(name() + ".iqNonSpecInstsAdded")
181 .desc("Number of non-speculative instructions added to the IQ")
182 .prereq(iqNonSpecInstsAdded);
185 .name(name() + ".iqInstsIssued")
186 .desc("Number of instructions issued")
187 .prereq(iqInstsIssued);
190 .name(name() + ".iqIntInstsIssued")
191 .desc("Number of integer instructions issued")
192 .prereq(iqIntInstsIssued);
195 .name(name() + ".iqFloatInstsIssued")
196 .desc("Number of float instructions issued")
197 .prereq(iqFloatInstsIssued);
200 .name(name() + ".iqBranchInstsIssued")
201 .desc("Number of branch instructions issued")
202 .prereq(iqBranchInstsIssued);
205 .name(name() + ".iqMemInstsIssued")
206 .desc("Number of memory instructions issued")
207 .prereq(iqMemInstsIssued);
210 .name(name() + ".iqMiscInstsIssued")
211 .desc("Number of miscellaneous instructions issued")
212 .prereq(iqMiscInstsIssued);
214 iqSquashedInstsIssued
215 .name(name() + ".iqSquashedInstsIssued")
216 .desc("Number of squashed instructions issued")
217 .prereq(iqSquashedInstsIssued);
219 iqSquashedInstsExamined
220 .name(name() + ".iqSquashedInstsExamined")
221 .desc("Number of squashed instructions iterated over during squash;"
222 " mainly for profiling")
223 .prereq(iqSquashedInstsExamined);
225 iqSquashedOperandsExamined
226 .name(name() + ".iqSquashedOperandsExamined")
227 .desc("Number of squashed operands that are examined and possibly "
228 "removed from graph")
229 .prereq(iqSquashedOperandsExamined);
231 iqSquashedNonSpecRemoved
232 .name(name() + ".iqSquashedNonSpecRemoved")
233 .desc("Number of squashed non-spec instructions that were removed")
234 .prereq(iqSquashedNonSpecRemoved);
237 .init(Num_OpClasses, 0, 99, 2)
238 .name(name() + ".IQ:residence:")
239 .desc("cycles from dispatch to issue")
240 .flags(total | pdf | cdf )
242 for (int i = 0; i < Num_OpClasses; ++i) {
243 queueResDist.subname(i, opClassStrings[i]);
247 .init(0,totalWidth,1)
248 .name(name() + ".ISSUE:issued_per_cycle")
249 .desc("Number of insts issued each cycle")
254 .init(Num_OpClasses+2)
255 .name(name() + ".ISSUE:unissued_cause")
256 .desc("Reason ready instruction not issued")
259 for (int i=0; i < (Num_OpClasses + 2); ++i) {
260 dist_unissued.subname(i, unissued_names[i]);
264 .init(numThreads,Num_OpClasses)
265 .name(name() + ".ISSUE:FU_type")
266 .desc("Type of FU issued")
267 .flags(total | pdf | dist)
269 statIssuedInstType.ysubnames(opClassStrings);
272 // How long did instructions for a particular FU type wait prior to issue
276 .init(Num_OpClasses,0,99,2)
277 .name(name() + ".ISSUE:")
278 .desc("cycles from operands ready to issue")
282 for (int i=0; i<Num_OpClasses; ++i) {
283 std::stringstream subname;
284 subname << opClassStrings[i] << "_delay";
285 issueDelayDist.subname(i, subname.str());
289 .name(name() + ".ISSUE:rate")
290 .desc("Inst issue rate")
293 issueRate = iqInstsIssued / cpu->numCycles;
297 .name(name() + ".ISSUE:fu_full")
298 .desc("attempts to use FU when none available")
301 for (int i=0; i < Num_OpClasses; ++i) {
302 statFuBusy.subname(i, opClassStrings[i]);
307 .name(name() + ".ISSUE:fu_busy_cnt")
308 .desc("FU busy when requested")
313 .name(name() + ".ISSUE:fu_busy_rate")
314 .desc("FU busy rate (busy events/executed inst)")
317 fuBusyRate = fuBusy / iqInstsIssued;
319 for ( int i=0; i < numThreads; i++) {
320 // Tell mem dependence unit to reg stats as well.
321 memDepUnit[i].regStats();
325 template <class Impl>
327 InstructionQueue<Impl>::resetState()
329 //Initialize thread IQ counts
330 for (int i = 0; i <numThreads; i++) {
335 // Initialize the number of free IQ entries.
336 freeEntries = numEntries;
338 // Note that in actuality, the registers corresponding to the logical
339 // registers start off as ready. However this doesn't matter for the
340 // IQ as the instruction should have been correctly told if those
341 // registers are ready in rename. Thus it can all be initialized as
343 for (int i = 0; i < numPhysRegs; ++i) {
344 regScoreboard[i] = false;
347 for (int i = 0; i < numThreads; ++i) {
348 squashedSeqNum[i] = 0;
351 for (int i = 0; i < Num_OpClasses; ++i) {
352 while (!readyInsts[i].empty())
354 queueOnList[i] = false;
355 readyIt[i] = listOrder.end();
357 nonSpecInsts.clear();
361 template <class Impl>
363 InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
365 activeThreads = at_ptr;
368 template <class Impl>
370 InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
372 issueToExecuteQueue = i2e_ptr;
375 template <class Impl>
377 InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
381 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
384 template <class Impl>
386 InstructionQueue<Impl>::switchOut()
389 if (!instList[0].empty() || (numEntries != freeEntries) ||
390 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
397 instsToExecute.clear();
399 for (int i = 0; i < numThreads; ++i) {
400 memDepUnit[i].switchOut();
404 template <class Impl>
406 InstructionQueue<Impl>::takeOverFrom()
411 template <class Impl>
413 InstructionQueue<Impl>::entryAmount(int num_threads)
415 if (iqPolicy == Partitioned) {
416 return numEntries / num_threads;
423 template <class Impl>
425 InstructionQueue<Impl>::resetEntries()
427 if (iqPolicy != Dynamic || numThreads > 1) {
428 int active_threads = activeThreads->size();
430 std::list<unsigned>::iterator threads = activeThreads->begin();
431 std::list<unsigned>::iterator end = activeThreads->end();
433 while (threads != end) {
434 unsigned tid = *threads++;
436 if (iqPolicy == Partitioned) {
437 maxEntries[tid] = numEntries / active_threads;
438 } else if(iqPolicy == Threshold && active_threads == 1) {
439 maxEntries[tid] = numEntries;
445 template <class Impl>
447 InstructionQueue<Impl>::numFreeEntries()
452 template <class Impl>
454 InstructionQueue<Impl>::numFreeEntries(unsigned tid)
456 return maxEntries[tid] - count[tid];
459 // Might want to do something more complex if it knows how many instructions
460 // will be issued this cycle.
461 template <class Impl>
463 InstructionQueue<Impl>::isFull()
465 if (freeEntries == 0) {
472 template <class Impl>
474 InstructionQueue<Impl>::isFull(unsigned tid)
476 if (numFreeEntries(tid) == 0) {
483 template <class Impl>
485 InstructionQueue<Impl>::hasReadyInsts()
487 if (!listOrder.empty()) {
491 for (int i = 0; i < Num_OpClasses; ++i) {
492 if (!readyInsts[i].empty()) {
500 template <class Impl>
502 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
504 // Make sure the instruction is valid
507 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
508 new_inst->seqNum, new_inst->readPC());
510 assert(freeEntries != 0);
512 instList[new_inst->threadNumber].push_back(new_inst);
518 // Look through its source registers (physical regs), and mark any
520 addToDependents(new_inst);
522 // Have this instruction set itself as the producer of its destination
524 addToProducers(new_inst);
526 if (new_inst->isMemRef()) {
527 memDepUnit[new_inst->threadNumber].insert(new_inst);
529 addIfReady(new_inst);
534 count[new_inst->threadNumber]++;
536 assert(freeEntries == (numEntries - countInsts()));
539 template <class Impl>
541 InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
543 // @todo: Clean up this code; can do it by setting inst as unable
544 // to issue, then calling normal insert on the inst.
548 nonSpecInsts[new_inst->seqNum] = new_inst;
550 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
552 new_inst->seqNum, new_inst->readPC());
554 assert(freeEntries != 0);
556 instList[new_inst->threadNumber].push_back(new_inst);
562 // Have this instruction set itself as the producer of its destination
564 addToProducers(new_inst);
566 // If it's a memory instruction, add it to the memory dependency
568 if (new_inst->isMemRef()) {
569 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
572 ++iqNonSpecInstsAdded;
574 count[new_inst->threadNumber]++;
576 assert(freeEntries == (numEntries - countInsts()));
579 template <class Impl>
581 InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
583 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
585 insertNonSpec(barr_inst);
588 template <class Impl>
589 typename Impl::DynInstPtr
590 InstructionQueue<Impl>::getInstToExecute()
592 assert(!instsToExecute.empty());
593 DynInstPtr inst = instsToExecute.front();
594 instsToExecute.pop_front();
598 template <class Impl>
600 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
602 assert(!readyInsts[op_class].empty());
604 ListOrderEntry queue_entry;
606 queue_entry.queueType = op_class;
608 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
610 ListOrderIt list_it = listOrder.begin();
611 ListOrderIt list_end_it = listOrder.end();
613 while (list_it != list_end_it) {
614 if ((*list_it).oldestInst > queue_entry.oldestInst) {
621 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
622 queueOnList[op_class] = true;
625 template <class Impl>
627 InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
629 // Get iterator of next item on the list
630 // Delete the original iterator
631 // Determine if the next item is either the end of the list or younger
632 // than the new instruction. If so, then add in a new iterator right here.
633 // If not, then move along.
634 ListOrderEntry queue_entry;
635 OpClass op_class = (*list_order_it).queueType;
636 ListOrderIt next_it = list_order_it;
640 queue_entry.queueType = op_class;
641 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
643 while (next_it != listOrder.end() &&
644 (*next_it).oldestInst < queue_entry.oldestInst) {
648 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
651 template <class Impl>
653 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
655 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
656 // The CPU could have been sleeping until this op completed (*extremely*
657 // long latency op). Wake it if it was. This may be overkill.
658 if (isSwitchedOut()) {
659 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
667 fuPool->freeUnitNextCycle(fu_idx);
669 // @todo: Ensure that these FU Completions happen at the beginning
670 // of a cycle, otherwise they could add too many instructions to
672 issueToExecuteQueue->access(0)->size++;
673 instsToExecute.push_back(inst);
676 // @todo: Figure out a better way to remove the squashed items from the
677 // lists. Checking the top item of each list to see if it's squashed
678 // wastes time and forces jumps.
679 template <class Impl>
681 InstructionQueue<Impl>::scheduleReadyInsts()
683 DPRINTF(IQ, "Attempting to schedule ready instructions from "
686 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
688 // Have iterator to head of the list
689 // While I haven't exceeded bandwidth or reached the end of the list,
690 // Try to get a FU that can do what this op needs.
691 // If successful, change the oldestInst to the new top of the list, put
692 // the queue in the proper place in the list.
693 // Increment the iterator.
694 // This will avoid trying to schedule a certain op class if there are no
695 // FUs that handle it.
696 ListOrderIt order_it = listOrder.begin();
697 ListOrderIt order_end_it = listOrder.end();
698 int total_issued = 0;
700 while (total_issued < totalWidth &&
701 iewStage->canIssue() &&
702 order_it != order_end_it) {
703 OpClass op_class = (*order_it).queueType;
705 assert(!readyInsts[op_class].empty());
707 DynInstPtr issuing_inst = readyInsts[op_class].top();
709 assert(issuing_inst->seqNum == (*order_it).oldestInst);
711 if (issuing_inst->isSquashed()) {
712 readyInsts[op_class].pop();
714 if (!readyInsts[op_class].empty()) {
715 moveToYoungerInst(order_it);
717 readyIt[op_class] = listOrder.end();
718 queueOnList[op_class] = false;
721 listOrder.erase(order_it++);
723 ++iqSquashedInstsIssued;
730 int tid = issuing_inst->threadNumber;
732 if (op_class != No_OpClass) {
733 idx = fuPool->getUnit(op_class);
736 op_latency = fuPool->getOpLatency(op_class);
740 // If we have an instruction that doesn't require a FU, or a
741 // valid FU, then schedule for execution.
742 if (idx == -2 || idx != -1) {
743 if (op_latency == 1) {
745 instsToExecute.push_back(issuing_inst);
747 // Add the FU onto the list of FU's to be freed next
748 // cycle if we used one.
750 fuPool->freeUnitNextCycle(idx);
752 int issue_latency = fuPool->getIssueLatency(op_class);
753 // Generate completion event for the FU
754 FUCompletion *execution = new FUCompletion(issuing_inst,
757 execution->schedule(curTick + cpu->cycles(issue_latency - 1));
759 // @todo: Enforce that issue_latency == 1 or op_latency
760 if (issue_latency > 1) {
761 // If FU isn't pipelined, then it must be freed
762 // upon the execution completing.
763 execution->setFreeFU();
765 // Add the FU onto the list of FU's to be freed next cycle.
766 fuPool->freeUnitNextCycle(idx);
770 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
772 tid, issuing_inst->readPC(),
773 issuing_inst->seqNum);
775 readyInsts[op_class].pop();
777 if (!readyInsts[op_class].empty()) {
778 moveToYoungerInst(order_it);
780 readyIt[op_class] = listOrder.end();
781 queueOnList[op_class] = false;
784 issuing_inst->setIssued();
787 if (!issuing_inst->isMemRef()) {
788 // Memory instructions can not be freed from the IQ until they
792 issuing_inst->clearInIQ();
794 memDepUnit[tid].issue(issuing_inst);
797 listOrder.erase(order_it++);
798 statIssuedInstType[tid][op_class]++;
799 iewStage->incrWb(issuing_inst->seqNum);
801 statFuBusy[op_class]++;
807 numIssuedDist.sample(total_issued);
808 iqInstsIssued+= total_issued;
810 // If we issued any instructions, tell the CPU we had activity.
812 cpu->activityThisCycle();
814 DPRINTF(IQ, "Not able to schedule any instructions.\n");
818 template <class Impl>
820 InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
822 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
823 "to execute.\n", inst);
825 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
827 assert(inst_it != nonSpecInsts.end());
829 unsigned tid = (*inst_it).second->threadNumber;
831 (*inst_it).second->setAtCommit();
833 (*inst_it).second->setCanIssue();
835 if (!(*inst_it).second->isMemRef()) {
836 addIfReady((*inst_it).second);
838 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
841 (*inst_it).second = NULL;
843 nonSpecInsts.erase(inst_it);
846 template <class Impl>
848 InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
850 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
853 ListIt iq_it = instList[tid].begin();
855 while (iq_it != instList[tid].end() &&
856 (*iq_it)->seqNum <= inst) {
858 instList[tid].pop_front();
861 assert(freeEntries == (numEntries - countInsts()));
864 template <class Impl>
866 InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
870 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
872 assert(!completed_inst->isSquashed());
874 // Tell the memory dependence unit to wake any dependents on this
875 // instruction if it is a memory instruction. Also complete the memory
876 // instruction at this point since we know it executed without issues.
877 // @todo: Might want to rename "completeMemInst" to something that
878 // indicates that it won't need to be replayed, and call this
879 // earlier. Might not be a big deal.
880 if (completed_inst->isMemRef()) {
881 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
882 completeMemInst(completed_inst);
883 } else if (completed_inst->isMemBarrier() ||
884 completed_inst->isWriteBarrier()) {
885 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
888 for (int dest_reg_idx = 0;
889 dest_reg_idx < completed_inst->numDestRegs();
892 PhysRegIndex dest_reg =
893 completed_inst->renamedDestRegIdx(dest_reg_idx);
895 // Special case of uniq or control registers. They are not
896 // handled by the IQ and thus have no dependency graph entry.
897 // @todo Figure out a cleaner way to handle this.
898 if (dest_reg >= numPhysRegs) {
902 DPRINTF(IQ, "Waking any dependents on register %i.\n",
905 //Go through the dependency chain, marking the registers as
906 //ready within the waiting instructions.
907 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
910 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
913 // Might want to give more information to the instruction
914 // so that it knows which of its source registers is
915 // ready. However that would mean that the dependency
916 // graph entries would need to hold the src_reg_idx.
917 dep_inst->markSrcRegReady();
919 addIfReady(dep_inst);
921 dep_inst = dependGraph.pop(dest_reg);
926 // Reset the head node now that all of its dependents have
928 assert(dependGraph.empty(dest_reg));
929 dependGraph.clearInst(dest_reg);
931 // Mark the scoreboard as having that register ready.
932 regScoreboard[dest_reg] = true;
937 template <class Impl>
939 InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
941 OpClass op_class = ready_inst->opClass();
943 readyInsts[op_class].push(ready_inst);
945 // Will need to reorder the list if either a queue is not on the list,
946 // or it has an older instruction than last time.
947 if (!queueOnList[op_class]) {
948 addToOrderList(op_class);
949 } else if (readyInsts[op_class].top()->seqNum <
950 (*readyIt[op_class]).oldestInst) {
951 listOrder.erase(readyIt[op_class]);
952 addToOrderList(op_class);
955 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
956 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
957 ready_inst->readPC(), op_class, ready_inst->seqNum);
960 template <class Impl>
962 InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
964 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
965 resched_inst->clearCanIssue();
966 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
969 template <class Impl>
971 InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
973 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
976 template <class Impl>
978 InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
980 int tid = completed_inst->threadNumber;
982 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
983 completed_inst->readPC(), completed_inst->seqNum);
987 completed_inst->memOpDone = true;
989 memDepUnit[tid].completed(completed_inst);
993 template <class Impl>
995 InstructionQueue<Impl>::violation(DynInstPtr &store,
996 DynInstPtr &faulting_load)
998 memDepUnit[store->threadNumber].violation(store, faulting_load);
1001 template <class Impl>
1003 InstructionQueue<Impl>::squash(unsigned tid)
1005 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1008 // Read instruction sequence number of last instruction out of the
1010 #if ISA_HAS_DELAY_SLOT
1011 squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1013 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1016 // Call doSquash if there are insts in the IQ
1017 if (count[tid] > 0) {
1021 // Also tell the memory dependence unit to squash.
1022 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1025 template <class Impl>
1027 InstructionQueue<Impl>::doSquash(unsigned tid)
1029 // Start at the tail.
1030 ListIt squash_it = instList[tid].end();
1033 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1034 tid, squashedSeqNum[tid]);
1036 // Squash any instructions younger than the squashed sequence number
1038 while (squash_it != instList[tid].end() &&
1039 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1041 DynInstPtr squashed_inst = (*squash_it);
1043 // Only handle the instruction if it actually is in the IQ and
1044 // hasn't already been squashed in the IQ.
1045 if (squashed_inst->threadNumber != tid ||
1046 squashed_inst->isSquashedInIQ()) {
1051 if (!squashed_inst->isIssued() ||
1052 (squashed_inst->isMemRef() &&
1053 !squashed_inst->memOpDone)) {
1055 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
1057 tid, squashed_inst->seqNum, squashed_inst->readPC());
1059 // Remove the instruction from the dependency list.
1060 if (!squashed_inst->isNonSpeculative() &&
1061 !squashed_inst->isStoreConditional() &&
1062 !squashed_inst->isMemBarrier() &&
1063 !squashed_inst->isWriteBarrier()) {
1065 for (int src_reg_idx = 0;
1066 src_reg_idx < squashed_inst->numSrcRegs();
1069 PhysRegIndex src_reg =
1070 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1072 // Only remove it from the dependency graph if it
1073 // was placed there in the first place.
1075 // Instead of doing a linked list traversal, we
1076 // can just remove these squashed instructions
1077 // either at issue time, or when the register is
1078 // overwritten. The only downside to this is it
1079 // leaves more room for error.
1081 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1082 src_reg < numPhysRegs) {
1083 dependGraph.remove(src_reg, squashed_inst);
1087 ++iqSquashedOperandsExamined;
1089 } else if (!squashed_inst->isStoreConditional() ||
1090 !squashed_inst->isCompleted()) {
1091 NonSpecMapIt ns_inst_it =
1092 nonSpecInsts.find(squashed_inst->seqNum);
1093 assert(ns_inst_it != nonSpecInsts.end());
1094 if (ns_inst_it == nonSpecInsts.end()) {
1095 assert(squashed_inst->getFault() != NoFault);
1098 (*ns_inst_it).second = NULL;
1100 nonSpecInsts.erase(ns_inst_it);
1102 ++iqSquashedNonSpecRemoved;
1106 // Might want to also clear out the head of the dependency graph.
1108 // Mark it as squashed within the IQ.
1109 squashed_inst->setSquashedInIQ();
1111 // @todo: Remove this hack where several statuses are set so the
1112 // inst will flow through the rest of the pipeline.
1113 squashed_inst->setIssued();
1114 squashed_inst->setCanCommit();
1115 squashed_inst->clearInIQ();
1117 //Update Thread IQ Count
1118 count[squashed_inst->threadNumber]--;
1123 instList[tid].erase(squash_it--);
1124 ++iqSquashedInstsExamined;
1128 template <class Impl>
1130 InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1132 // Loop through the instruction's source registers, adding
1133 // them to the dependency list if they are not ready.
1134 int8_t total_src_regs = new_inst->numSrcRegs();
1135 bool return_val = false;
1137 for (int src_reg_idx = 0;
1138 src_reg_idx < total_src_regs;
1141 // Only add it to the dependency graph if it's not ready.
1142 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1143 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1145 // Check the IQ's scoreboard to make sure the register
1146 // hasn't become ready while the instruction was in flight
1147 // between stages. Only if it really isn't ready should
1148 // it be added to the dependency graph.
1149 if (src_reg >= numPhysRegs) {
1151 } else if (regScoreboard[src_reg] == false) {
1152 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1153 "is being added to the dependency chain.\n",
1154 new_inst->readPC(), src_reg);
1156 dependGraph.insert(src_reg, new_inst);
1158 // Change the return value to indicate that something
1159 // was added to the dependency graph.
1162 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1163 "became ready before it reached the IQ.\n",
1164 new_inst->readPC(), src_reg);
1165 // Mark a register ready within the instruction.
1166 new_inst->markSrcRegReady(src_reg_idx);
1174 template <class Impl>
1176 InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1178 // Nothing really needs to be marked when an instruction becomes
1179 // the producer of a register's value, but for convenience a ptr
1180 // to the producing instruction will be placed in the head node of
1181 // the dependency links.
1182 int8_t total_dest_regs = new_inst->numDestRegs();
1184 for (int dest_reg_idx = 0;
1185 dest_reg_idx < total_dest_regs;
1188 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1190 // Instructions that use the misc regs will have a reg number
1191 // higher than the normal physical registers. In this case these
1192 // registers are not renamed, and there is no need to track
1193 // dependencies as these instructions must be executed at commit.
1194 if (dest_reg >= numPhysRegs) {
1198 if (!dependGraph.empty(dest_reg)) {
1200 panic("Dependency graph %i not empty!", dest_reg);
1203 dependGraph.setInst(dest_reg, new_inst);
1205 // Mark the scoreboard to say it's not yet ready.
1206 regScoreboard[dest_reg] = false;
1210 template <class Impl>
1212 InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1214 // If the instruction now has all of its source registers
1215 // available, then add it to the list of ready instructions.
1216 if (inst->readyToIssue()) {
1218 //Add the instruction to the proper ready list.
1219 if (inst->isMemRef()) {
1221 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1223 // Message to the mem dependence unit that this instruction has
1224 // its registers ready.
1225 memDepUnit[inst->threadNumber].regsReady(inst);
1230 OpClass op_class = inst->opClass();
1232 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1233 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1234 inst->readPC(), op_class, inst->seqNum);
1236 readyInsts[op_class].push(inst);
1238 // Will need to reorder the list if either a queue is not on the list,
1239 // or it has an older instruction than last time.
1240 if (!queueOnList[op_class]) {
1241 addToOrderList(op_class);
1242 } else if (readyInsts[op_class].top()->seqNum <
1243 (*readyIt[op_class]).oldestInst) {
1244 listOrder.erase(readyIt[op_class]);
1245 addToOrderList(op_class);
1250 template <class Impl>
1252 InstructionQueue<Impl>::countInsts()
1255 //ksewell:This works but definitely could use a cleaner write
1256 //with a more intuitive way of counting. Right now it's
1257 //just brute force ....
1258 // Change the #if if you want to use this method.
1259 int total_insts = 0;
1261 for (int i = 0; i < numThreads; ++i) {
1262 ListIt count_it = instList[i].begin();
1264 while (count_it != instList[i].end()) {
1265 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1266 if (!(*count_it)->isIssued()) {
1268 } else if ((*count_it)->isMemRef() &&
1269 !(*count_it)->memOpDone) {
1270 // Loads that have not been marked as executed still count
1271 // towards the total instructions.
1282 return numEntries - freeEntries;
1286 template <class Impl>
1288 InstructionQueue<Impl>::dumpLists()
1290 for (int i = 0; i < Num_OpClasses; ++i) {
1291 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1296 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1298 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1299 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1301 cprintf("Non speculative list: ");
1303 while (non_spec_it != non_spec_end_it) {
1304 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1305 (*non_spec_it).second->seqNum);
1311 ListOrderIt list_order_it = listOrder.begin();
1312 ListOrderIt list_order_end_it = listOrder.end();
1315 cprintf("List order: ");
1317 while (list_order_it != list_order_end_it) {
1318 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1319 (*list_order_it).oldestInst);
1329 template <class Impl>
1331 InstructionQueue<Impl>::dumpInsts()
1333 for (int i = 0; i < numThreads; ++i) {
1336 ListIt inst_list_it = instList[i].begin();
1338 while (inst_list_it != instList[i].end())
1340 cprintf("Instruction:%i\n",
1342 if (!(*inst_list_it)->isSquashed()) {
1343 if (!(*inst_list_it)->isIssued()) {
1345 cprintf("Count:%i\n", valid_num);
1346 } else if ((*inst_list_it)->isMemRef() &&
1347 !(*inst_list_it)->memOpDone) {
1348 // Loads that have not been marked as executed
1349 // still count towards the total instructions.
1351 cprintf("Count:%i\n", valid_num);
1355 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1356 "Issued:%i\nSquashed:%i\n",
1357 (*inst_list_it)->readPC(),
1358 (*inst_list_it)->seqNum,
1359 (*inst_list_it)->threadNumber,
1360 (*inst_list_it)->isIssued(),
1361 (*inst_list_it)->isSquashed());
1363 if ((*inst_list_it)->isMemRef()) {
1364 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1374 cprintf("Insts to Execute list:\n");
1378 ListIt inst_list_it = instsToExecute.begin();
1380 while (inst_list_it != instsToExecute.end())
1382 cprintf("Instruction:%i\n",
1384 if (!(*inst_list_it)->isSquashed()) {
1385 if (!(*inst_list_it)->isIssued()) {
1387 cprintf("Count:%i\n", valid_num);
1388 } else if ((*inst_list_it)->isMemRef() &&
1389 !(*inst_list_it)->memOpDone) {
1390 // Loads that have not been marked as executed
1391 // still count towards the total instructions.
1393 cprintf("Count:%i\n", valid_num);
1397 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1398 "Issued:%i\nSquashed:%i\n",
1399 (*inst_list_it)->readPC(),
1400 (*inst_list_it)->seqNum,
1401 (*inst_list_it)->threadNumber,
1402 (*inst_list_it)->isIssued(),
1403 (*inst_list_it)->isSquashed());
1405 if ((*inst_list_it)->isMemRef()) {
1406 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);