2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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35 #include "sim/root.hh"
37 #include "cpu/o3/fu_pool.hh"
38 #include "cpu/o3/inst_queue.hh"
41 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
43 InstructionQueue<Impl> *iq_ptr)
44 : Event(&mainEventQueue, Stat_Event_Pri),
45 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
47 this->setFlags(Event::AutoDelete);
52 InstructionQueue<Impl>::FUCompletion::process()
54 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
61 InstructionQueue<Impl>::FUCompletion::description()
63 return "Functional unit completion event";
67 InstructionQueue<Impl>::InstructionQueue(Params *params)
68 : fuPool(params->fuPool),
69 numEntries(params->numIQEntries),
70 totalWidth(params->issueWidth),
71 numPhysIntRegs(params->numPhysIntRegs),
72 numPhysFloatRegs(params->numPhysFloatRegs),
73 commitToIEWDelay(params->commitToIEWDelay)
79 numThreads = params->numberOfThreads;
81 // Set the number of physical registers as the number of int + float
82 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
84 DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
86 //Create an entry for each physical register within the
88 dependGraph.resize(numPhysRegs);
90 // Resize the register scoreboard.
91 regScoreboard.resize(numPhysRegs);
93 //Initialize Mem Dependence Units
94 for (int i = 0; i < numThreads; i++) {
95 memDepUnit[i].init(params,i);
96 memDepUnit[i].setIQ(this);
101 std::string policy = params->smtIQPolicy;
103 //Convert string to lowercase
104 std::transform(policy.begin(), policy.end(), policy.begin(),
105 (int(*)(int)) tolower);
107 //Figure out resource sharing policy
108 if (policy == "dynamic") {
111 //Set Max Entries to Total ROB Capacity
112 for (int i = 0; i < numThreads; i++) {
113 maxEntries[i] = numEntries;
116 } else if (policy == "partitioned") {
117 iqPolicy = Partitioned;
119 //@todo:make work if part_amt doesnt divide evenly.
120 int part_amt = numEntries / numThreads;
122 //Divide ROB up evenly
123 for (int i = 0; i < numThreads; i++) {
124 maxEntries[i] = part_amt;
127 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
128 "%i entries per thread.\n",part_amt);
130 } else if (policy == "threshold") {
131 iqPolicy = Threshold;
133 double threshold = (double)params->smtIQThreshold / 100;
135 int thresholdIQ = (int)((double)threshold * numEntries);
137 //Divide up by threshold amount
138 for (int i = 0; i < numThreads; i++) {
139 maxEntries[i] = thresholdIQ;
142 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
143 "%i entries per thread.\n",thresholdIQ);
145 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
146 "Partitioned, Threshold}");
150 template <class Impl>
151 InstructionQueue<Impl>::~InstructionQueue()
155 cprintf("Nodes traversed: %i, removed: %i\n",
156 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
160 template <class Impl>
162 InstructionQueue<Impl>::name() const
164 return cpu->name() + ".iq";
167 template <class Impl>
169 InstructionQueue<Impl>::regStats()
171 using namespace Stats;
173 .name(name() + ".iqInstsAdded")
174 .desc("Number of instructions added to the IQ (excludes non-spec)")
175 .prereq(iqInstsAdded);
178 .name(name() + ".iqNonSpecInstsAdded")
179 .desc("Number of non-speculative instructions added to the IQ")
180 .prereq(iqNonSpecInstsAdded);
183 .name(name() + ".iqInstsIssued")
184 .desc("Number of instructions issued")
185 .prereq(iqInstsIssued);
188 .name(name() + ".iqIntInstsIssued")
189 .desc("Number of integer instructions issued")
190 .prereq(iqIntInstsIssued);
193 .name(name() + ".iqFloatInstsIssued")
194 .desc("Number of float instructions issued")
195 .prereq(iqFloatInstsIssued);
198 .name(name() + ".iqBranchInstsIssued")
199 .desc("Number of branch instructions issued")
200 .prereq(iqBranchInstsIssued);
203 .name(name() + ".iqMemInstsIssued")
204 .desc("Number of memory instructions issued")
205 .prereq(iqMemInstsIssued);
208 .name(name() + ".iqMiscInstsIssued")
209 .desc("Number of miscellaneous instructions issued")
210 .prereq(iqMiscInstsIssued);
212 iqSquashedInstsIssued
213 .name(name() + ".iqSquashedInstsIssued")
214 .desc("Number of squashed instructions issued")
215 .prereq(iqSquashedInstsIssued);
217 iqSquashedInstsExamined
218 .name(name() + ".iqSquashedInstsExamined")
219 .desc("Number of squashed instructions iterated over during squash;"
220 " mainly for profiling")
221 .prereq(iqSquashedInstsExamined);
223 iqSquashedOperandsExamined
224 .name(name() + ".iqSquashedOperandsExamined")
225 .desc("Number of squashed operands that are examined and possibly "
226 "removed from graph")
227 .prereq(iqSquashedOperandsExamined);
229 iqSquashedNonSpecRemoved
230 .name(name() + ".iqSquashedNonSpecRemoved")
231 .desc("Number of squashed non-spec instructions that were removed")
232 .prereq(iqSquashedNonSpecRemoved);
235 .init(Num_OpClasses, 0, 99, 2)
236 .name(name() + ".IQ:residence:")
237 .desc("cycles from dispatch to issue")
238 .flags(total | pdf | cdf )
240 for (int i = 0; i < Num_OpClasses; ++i) {
241 queueResDist.subname(i, opClassStrings[i]);
245 .init(0,totalWidth,1)
246 .name(name() + ".ISSUE:issued_per_cycle")
247 .desc("Number of insts issued each cycle")
252 .init(Num_OpClasses+2)
253 .name(name() + ".ISSUE:unissued_cause")
254 .desc("Reason ready instruction not issued")
257 for (int i=0; i < (Num_OpClasses + 2); ++i) {
258 dist_unissued.subname(i, unissued_names[i]);
262 .init(numThreads,Num_OpClasses)
263 .name(name() + ".ISSUE:FU_type")
264 .desc("Type of FU issued")
265 .flags(total | pdf | dist)
267 statIssuedInstType.ysubnames(opClassStrings);
270 // How long did instructions for a particular FU type wait prior to issue
274 .init(Num_OpClasses,0,99,2)
275 .name(name() + ".ISSUE:")
276 .desc("cycles from operands ready to issue")
280 for (int i=0; i<Num_OpClasses; ++i) {
281 std::stringstream subname;
282 subname << opClassStrings[i] << "_delay";
283 issueDelayDist.subname(i, subname.str());
287 .name(name() + ".ISSUE:rate")
288 .desc("Inst issue rate")
291 issueRate = iqInstsIssued / cpu->numCycles;
295 .name(name() + ".ISSUE:fu_full")
296 .desc("attempts to use FU when none available")
299 for (int i=0; i < Num_OpClasses; ++i) {
300 statFuBusy.subname(i, opClassStrings[i]);
305 .name(name() + ".ISSUE:fu_busy_cnt")
306 .desc("FU busy when requested")
311 .name(name() + ".ISSUE:fu_busy_rate")
312 .desc("FU busy rate (busy events/executed inst)")
315 fuBusyRate = fuBusy / iqInstsIssued;
317 for ( int i=0; i < numThreads; i++) {
318 // Tell mem dependence unit to reg stats as well.
319 memDepUnit[i].regStats();
323 template <class Impl>
325 InstructionQueue<Impl>::resetState()
327 //Initialize thread IQ counts
328 for (int i = 0; i <numThreads; i++) {
333 // Initialize the number of free IQ entries.
334 freeEntries = numEntries;
336 // Note that in actuality, the registers corresponding to the logical
337 // registers start off as ready. However this doesn't matter for the
338 // IQ as the instruction should have been correctly told if those
339 // registers are ready in rename. Thus it can all be initialized as
341 for (int i = 0; i < numPhysRegs; ++i) {
342 regScoreboard[i] = false;
345 for (int i = 0; i < numThreads; ++i) {
346 squashedSeqNum[i] = 0;
349 for (int i = 0; i < Num_OpClasses; ++i) {
350 while (!readyInsts[i].empty())
352 queueOnList[i] = false;
353 readyIt[i] = listOrder.end();
355 nonSpecInsts.clear();
359 template <class Impl>
361 InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
363 DPRINTF(IQ, "Setting active threads list pointer.\n");
364 activeThreads = at_ptr;
367 template <class Impl>
369 InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
371 DPRINTF(IQ, "Set the issue to execute queue.\n");
372 issueToExecuteQueue = i2e_ptr;
375 template <class Impl>
377 InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
379 DPRINTF(IQ, "Set the time buffer.\n");
382 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
385 template <class Impl>
387 InstructionQueue<Impl>::switchOut()
390 if (!instList[0].empty() || (numEntries != freeEntries) ||
391 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
398 instsToExecute.clear();
400 for (int i = 0; i < numThreads; ++i) {
401 memDepUnit[i].switchOut();
405 template <class Impl>
407 InstructionQueue<Impl>::takeOverFrom()
412 template <class Impl>
414 InstructionQueue<Impl>::entryAmount(int num_threads)
416 if (iqPolicy == Partitioned) {
417 return numEntries / num_threads;
424 template <class Impl>
426 InstructionQueue<Impl>::resetEntries()
428 if (iqPolicy != Dynamic || numThreads > 1) {
429 int active_threads = (*activeThreads).size();
431 std::list<unsigned>::iterator threads = (*activeThreads).begin();
432 std::list<unsigned>::iterator list_end = (*activeThreads).end();
434 while (threads != list_end) {
435 if (iqPolicy == Partitioned) {
436 maxEntries[*threads++] = numEntries / active_threads;
437 } else if(iqPolicy == Threshold && active_threads == 1) {
438 maxEntries[*threads++] = numEntries;
444 template <class Impl>
446 InstructionQueue<Impl>::numFreeEntries()
451 template <class Impl>
453 InstructionQueue<Impl>::numFreeEntries(unsigned tid)
455 return maxEntries[tid] - count[tid];
458 // Might want to do something more complex if it knows how many instructions
459 // will be issued this cycle.
460 template <class Impl>
462 InstructionQueue<Impl>::isFull()
464 if (freeEntries == 0) {
471 template <class Impl>
473 InstructionQueue<Impl>::isFull(unsigned tid)
475 if (numFreeEntries(tid) == 0) {
482 template <class Impl>
484 InstructionQueue<Impl>::hasReadyInsts()
486 if (!listOrder.empty()) {
490 for (int i = 0; i < Num_OpClasses; ++i) {
491 if (!readyInsts[i].empty()) {
499 template <class Impl>
501 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
503 // Make sure the instruction is valid
506 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
507 new_inst->seqNum, new_inst->readPC());
509 assert(freeEntries != 0);
511 instList[new_inst->threadNumber].push_back(new_inst);
517 // Look through its source registers (physical regs), and mark any
519 addToDependents(new_inst);
521 // Have this instruction set itself as the producer of its destination
523 addToProducers(new_inst);
525 if (new_inst->isMemRef()) {
526 memDepUnit[new_inst->threadNumber].insert(new_inst);
528 addIfReady(new_inst);
533 count[new_inst->threadNumber]++;
535 assert(freeEntries == (numEntries - countInsts()));
538 template <class Impl>
540 InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
542 // @todo: Clean up this code; can do it by setting inst as unable
543 // to issue, then calling normal insert on the inst.
547 nonSpecInsts[new_inst->seqNum] = new_inst;
549 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
551 new_inst->seqNum, new_inst->readPC());
553 assert(freeEntries != 0);
555 instList[new_inst->threadNumber].push_back(new_inst);
561 // Have this instruction set itself as the producer of its destination
563 addToProducers(new_inst);
565 // If it's a memory instruction, add it to the memory dependency
567 if (new_inst->isMemRef()) {
568 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
571 ++iqNonSpecInstsAdded;
573 count[new_inst->threadNumber]++;
575 assert(freeEntries == (numEntries - countInsts()));
578 template <class Impl>
580 InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
582 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
584 insertNonSpec(barr_inst);
587 template <class Impl>
588 typename Impl::DynInstPtr
589 InstructionQueue<Impl>::getInstToExecute()
591 assert(!instsToExecute.empty());
592 DynInstPtr inst = instsToExecute.front();
593 instsToExecute.pop_front();
597 template <class Impl>
599 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
601 assert(!readyInsts[op_class].empty());
603 ListOrderEntry queue_entry;
605 queue_entry.queueType = op_class;
607 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
609 ListOrderIt list_it = listOrder.begin();
610 ListOrderIt list_end_it = listOrder.end();
612 while (list_it != list_end_it) {
613 if ((*list_it).oldestInst > queue_entry.oldestInst) {
620 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
621 queueOnList[op_class] = true;
624 template <class Impl>
626 InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
628 // Get iterator of next item on the list
629 // Delete the original iterator
630 // Determine if the next item is either the end of the list or younger
631 // than the new instruction. If so, then add in a new iterator right here.
632 // If not, then move along.
633 ListOrderEntry queue_entry;
634 OpClass op_class = (*list_order_it).queueType;
635 ListOrderIt next_it = list_order_it;
639 queue_entry.queueType = op_class;
640 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
642 while (next_it != listOrder.end() &&
643 (*next_it).oldestInst < queue_entry.oldestInst) {
647 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
650 template <class Impl>
652 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
654 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
655 // The CPU could have been sleeping until this op completed (*extremely*
656 // long latency op). Wake it if it was. This may be overkill.
657 if (isSwitchedOut()) {
658 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
666 fuPool->freeUnitNextCycle(fu_idx);
668 // @todo: Ensure that these FU Completions happen at the beginning
669 // of a cycle, otherwise they could add too many instructions to
671 issueToExecuteQueue->access(0)->size++;
672 instsToExecute.push_back(inst);
675 // @todo: Figure out a better way to remove the squashed items from the
676 // lists. Checking the top item of each list to see if it's squashed
677 // wastes time and forces jumps.
678 template <class Impl>
680 InstructionQueue<Impl>::scheduleReadyInsts()
682 DPRINTF(IQ, "Attempting to schedule ready instructions from "
685 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
687 // Have iterator to head of the list
688 // While I haven't exceeded bandwidth or reached the end of the list,
689 // Try to get a FU that can do what this op needs.
690 // If successful, change the oldestInst to the new top of the list, put
691 // the queue in the proper place in the list.
692 // Increment the iterator.
693 // This will avoid trying to schedule a certain op class if there are no
694 // FUs that handle it.
695 ListOrderIt order_it = listOrder.begin();
696 ListOrderIt order_end_it = listOrder.end();
697 int total_issued = 0;
699 while (total_issued < totalWidth &&
700 iewStage->canIssue() &&
701 order_it != order_end_it) {
702 OpClass op_class = (*order_it).queueType;
704 assert(!readyInsts[op_class].empty());
706 DynInstPtr issuing_inst = readyInsts[op_class].top();
708 assert(issuing_inst->seqNum == (*order_it).oldestInst);
710 if (issuing_inst->isSquashed()) {
711 readyInsts[op_class].pop();
713 if (!readyInsts[op_class].empty()) {
714 moveToYoungerInst(order_it);
716 readyIt[op_class] = listOrder.end();
717 queueOnList[op_class] = false;
720 listOrder.erase(order_it++);
722 ++iqSquashedInstsIssued;
729 int tid = issuing_inst->threadNumber;
731 if (op_class != No_OpClass) {
732 idx = fuPool->getUnit(op_class);
735 op_latency = fuPool->getOpLatency(op_class);
739 // If we have an instruction that doesn't require a FU, or a
740 // valid FU, then schedule for execution.
741 if (idx == -2 || idx != -1) {
742 if (op_latency == 1) {
744 instsToExecute.push_back(issuing_inst);
746 // Add the FU onto the list of FU's to be freed next
747 // cycle if we used one.
749 fuPool->freeUnitNextCycle(idx);
751 int issue_latency = fuPool->getIssueLatency(op_class);
752 // Generate completion event for the FU
753 FUCompletion *execution = new FUCompletion(issuing_inst,
756 execution->schedule(curTick + cpu->cycles(issue_latency - 1));
758 // @todo: Enforce that issue_latency == 1 or op_latency
759 if (issue_latency > 1) {
760 // If FU isn't pipelined, then it must be freed
761 // upon the execution completing.
762 execution->setFreeFU();
764 // Add the FU onto the list of FU's to be freed next cycle.
765 fuPool->freeUnitNextCycle(idx);
769 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
771 tid, issuing_inst->readPC(),
772 issuing_inst->seqNum);
774 readyInsts[op_class].pop();
776 if (!readyInsts[op_class].empty()) {
777 moveToYoungerInst(order_it);
779 readyIt[op_class] = listOrder.end();
780 queueOnList[op_class] = false;
783 issuing_inst->setIssued();
786 if (!issuing_inst->isMemRef()) {
787 // Memory instructions can not be freed from the IQ until they
791 issuing_inst->clearInIQ();
793 memDepUnit[tid].issue(issuing_inst);
796 listOrder.erase(order_it++);
797 statIssuedInstType[tid][op_class]++;
798 iewStage->incrWb(issuing_inst->seqNum);
800 statFuBusy[op_class]++;
806 numIssuedDist.sample(total_issued);
807 iqInstsIssued+= total_issued;
809 // If we issued any instructions, tell the CPU we had activity.
811 cpu->activityThisCycle();
813 DPRINTF(IQ, "Not able to schedule any instructions.\n");
817 template <class Impl>
819 InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
821 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
822 "to execute.\n", inst);
824 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
826 assert(inst_it != nonSpecInsts.end());
828 unsigned tid = (*inst_it).second->threadNumber;
830 (*inst_it).second->setCanIssue();
832 if (!(*inst_it).second->isMemRef()) {
833 addIfReady((*inst_it).second);
835 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
838 (*inst_it).second = NULL;
840 nonSpecInsts.erase(inst_it);
843 template <class Impl>
845 InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
847 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
850 ListIt iq_it = instList[tid].begin();
852 while (iq_it != instList[tid].end() &&
853 (*iq_it)->seqNum <= inst) {
855 instList[tid].pop_front();
858 assert(freeEntries == (numEntries - countInsts()));
861 template <class Impl>
863 InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
867 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
869 assert(!completed_inst->isSquashed());
871 // Tell the memory dependence unit to wake any dependents on this
872 // instruction if it is a memory instruction. Also complete the memory
873 // instruction at this point since we know it executed without issues.
874 // @todo: Might want to rename "completeMemInst" to something that
875 // indicates that it won't need to be replayed, and call this
876 // earlier. Might not be a big deal.
877 if (completed_inst->isMemRef()) {
878 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
879 completeMemInst(completed_inst);
880 } else if (completed_inst->isMemBarrier() ||
881 completed_inst->isWriteBarrier()) {
882 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
885 for (int dest_reg_idx = 0;
886 dest_reg_idx < completed_inst->numDestRegs();
889 PhysRegIndex dest_reg =
890 completed_inst->renamedDestRegIdx(dest_reg_idx);
892 // Special case of uniq or control registers. They are not
893 // handled by the IQ and thus have no dependency graph entry.
894 // @todo Figure out a cleaner way to handle this.
895 if (dest_reg >= numPhysRegs) {
899 DPRINTF(IQ, "Waking any dependents on register %i.\n",
902 //Go through the dependency chain, marking the registers as
903 //ready within the waiting instructions.
904 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
907 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
910 // Might want to give more information to the instruction
911 // so that it knows which of its source registers is
912 // ready. However that would mean that the dependency
913 // graph entries would need to hold the src_reg_idx.
914 dep_inst->markSrcRegReady();
916 addIfReady(dep_inst);
918 dep_inst = dependGraph.pop(dest_reg);
923 // Reset the head node now that all of its dependents have
925 assert(dependGraph.empty(dest_reg));
926 dependGraph.clearInst(dest_reg);
928 // Mark the scoreboard as having that register ready.
929 regScoreboard[dest_reg] = true;
934 template <class Impl>
936 InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
938 OpClass op_class = ready_inst->opClass();
940 readyInsts[op_class].push(ready_inst);
942 // Will need to reorder the list if either a queue is not on the list,
943 // or it has an older instruction than last time.
944 if (!queueOnList[op_class]) {
945 addToOrderList(op_class);
946 } else if (readyInsts[op_class].top()->seqNum <
947 (*readyIt[op_class]).oldestInst) {
948 listOrder.erase(readyIt[op_class]);
949 addToOrderList(op_class);
952 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
953 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
954 ready_inst->readPC(), op_class, ready_inst->seqNum);
957 template <class Impl>
959 InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
961 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
964 template <class Impl>
966 InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
968 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
971 template <class Impl>
973 InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
975 int tid = completed_inst->threadNumber;
977 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
978 completed_inst->readPC(), completed_inst->seqNum);
982 completed_inst->memOpDone = true;
984 memDepUnit[tid].completed(completed_inst);
989 template <class Impl>
991 InstructionQueue<Impl>::violation(DynInstPtr &store,
992 DynInstPtr &faulting_load)
994 memDepUnit[store->threadNumber].violation(store, faulting_load);
997 template <class Impl>
999 InstructionQueue<Impl>::squash(unsigned tid)
1001 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1004 // Read instruction sequence number of last instruction out of the
1006 #if ISA_HAS_DELAY_SLOT
1007 squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1009 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1012 // Call doSquash if there are insts in the IQ
1013 if (count[tid] > 0) {
1017 // Also tell the memory dependence unit to squash.
1018 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1021 template <class Impl>
1023 InstructionQueue<Impl>::doSquash(unsigned tid)
1025 // Start at the tail.
1026 ListIt squash_it = instList[tid].end();
1029 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1030 tid, squashedSeqNum[tid]);
1032 // Squash any instructions younger than the squashed sequence number
1034 while (squash_it != instList[tid].end() &&
1035 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1037 DynInstPtr squashed_inst = (*squash_it);
1039 // Only handle the instruction if it actually is in the IQ and
1040 // hasn't already been squashed in the IQ.
1041 if (squashed_inst->threadNumber != tid ||
1042 squashed_inst->isSquashedInIQ()) {
1047 if (!squashed_inst->isIssued() ||
1048 (squashed_inst->isMemRef() &&
1049 !squashed_inst->memOpDone)) {
1051 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
1053 tid, squashed_inst->seqNum, squashed_inst->readPC());
1055 // Remove the instruction from the dependency list.
1056 if (!squashed_inst->isNonSpeculative() &&
1057 !squashed_inst->isStoreConditional() &&
1058 !squashed_inst->isMemBarrier() &&
1059 !squashed_inst->isWriteBarrier()) {
1061 for (int src_reg_idx = 0;
1062 src_reg_idx < squashed_inst->numSrcRegs();
1065 PhysRegIndex src_reg =
1066 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1068 // Only remove it from the dependency graph if it
1069 // was placed there in the first place.
1071 // Instead of doing a linked list traversal, we
1072 // can just remove these squashed instructions
1073 // either at issue time, or when the register is
1074 // overwritten. The only downside to this is it
1075 // leaves more room for error.
1077 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1078 src_reg < numPhysRegs) {
1079 dependGraph.remove(src_reg, squashed_inst);
1083 ++iqSquashedOperandsExamined;
1085 } else if (!squashed_inst->isStoreConditional() || !squashed_inst->isCompleted()) {
1086 NonSpecMapIt ns_inst_it =
1087 nonSpecInsts.find(squashed_inst->seqNum);
1088 assert(ns_inst_it != nonSpecInsts.end());
1090 (*ns_inst_it).second = NULL;
1092 nonSpecInsts.erase(ns_inst_it);
1094 ++iqSquashedNonSpecRemoved;
1097 // Might want to also clear out the head of the dependency graph.
1099 // Mark it as squashed within the IQ.
1100 squashed_inst->setSquashedInIQ();
1102 // @todo: Remove this hack where several statuses are set so the
1103 // inst will flow through the rest of the pipeline.
1104 squashed_inst->setIssued();
1105 squashed_inst->setCanCommit();
1106 squashed_inst->clearInIQ();
1108 //Update Thread IQ Count
1109 count[squashed_inst->threadNumber]--;
1114 instList[tid].erase(squash_it--);
1115 ++iqSquashedInstsExamined;
1119 template <class Impl>
1121 InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1123 // Loop through the instruction's source registers, adding
1124 // them to the dependency list if they are not ready.
1125 int8_t total_src_regs = new_inst->numSrcRegs();
1126 bool return_val = false;
1128 for (int src_reg_idx = 0;
1129 src_reg_idx < total_src_regs;
1132 // Only add it to the dependency graph if it's not ready.
1133 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1134 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1136 // Check the IQ's scoreboard to make sure the register
1137 // hasn't become ready while the instruction was in flight
1138 // between stages. Only if it really isn't ready should
1139 // it be added to the dependency graph.
1140 if (src_reg >= numPhysRegs) {
1142 } else if (regScoreboard[src_reg] == false) {
1143 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1144 "is being added to the dependency chain.\n",
1145 new_inst->readPC(), src_reg);
1147 dependGraph.insert(src_reg, new_inst);
1149 // Change the return value to indicate that something
1150 // was added to the dependency graph.
1153 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1154 "became ready before it reached the IQ.\n",
1155 new_inst->readPC(), src_reg);
1156 // Mark a register ready within the instruction.
1157 new_inst->markSrcRegReady(src_reg_idx);
1165 template <class Impl>
1167 InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1169 // Nothing really needs to be marked when an instruction becomes
1170 // the producer of a register's value, but for convenience a ptr
1171 // to the producing instruction will be placed in the head node of
1172 // the dependency links.
1173 int8_t total_dest_regs = new_inst->numDestRegs();
1175 for (int dest_reg_idx = 0;
1176 dest_reg_idx < total_dest_regs;
1179 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1181 // Instructions that use the misc regs will have a reg number
1182 // higher than the normal physical registers. In this case these
1183 // registers are not renamed, and there is no need to track
1184 // dependencies as these instructions must be executed at commit.
1185 if (dest_reg >= numPhysRegs) {
1189 if (!dependGraph.empty(dest_reg)) {
1191 panic("Dependency graph %i not empty!", dest_reg);
1194 dependGraph.setInst(dest_reg, new_inst);
1196 // Mark the scoreboard to say it's not yet ready.
1197 regScoreboard[dest_reg] = false;
1201 template <class Impl>
1203 InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1205 // If the instruction now has all of its source registers
1206 // available, then add it to the list of ready instructions.
1207 if (inst->readyToIssue()) {
1209 //Add the instruction to the proper ready list.
1210 if (inst->isMemRef()) {
1212 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1214 // Message to the mem dependence unit that this instruction has
1215 // its registers ready.
1216 memDepUnit[inst->threadNumber].regsReady(inst);
1221 OpClass op_class = inst->opClass();
1223 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1224 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1225 inst->readPC(), op_class, inst->seqNum);
1227 readyInsts[op_class].push(inst);
1229 // Will need to reorder the list if either a queue is not on the list,
1230 // or it has an older instruction than last time.
1231 if (!queueOnList[op_class]) {
1232 addToOrderList(op_class);
1233 } else if (readyInsts[op_class].top()->seqNum <
1234 (*readyIt[op_class]).oldestInst) {
1235 listOrder.erase(readyIt[op_class]);
1236 addToOrderList(op_class);
1241 template <class Impl>
1243 InstructionQueue<Impl>::countInsts()
1246 //ksewell:This works but definitely could use a cleaner write
1247 //with a more intuitive way of counting. Right now it's
1248 //just brute force ....
1249 // Change the #if if you want to use this method.
1250 int total_insts = 0;
1252 for (int i = 0; i < numThreads; ++i) {
1253 ListIt count_it = instList[i].begin();
1255 while (count_it != instList[i].end()) {
1256 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1257 if (!(*count_it)->isIssued()) {
1259 } else if ((*count_it)->isMemRef() &&
1260 !(*count_it)->memOpDone) {
1261 // Loads that have not been marked as executed still count
1262 // towards the total instructions.
1273 return numEntries - freeEntries;
1277 template <class Impl>
1279 InstructionQueue<Impl>::dumpLists()
1281 for (int i = 0; i < Num_OpClasses; ++i) {
1282 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1287 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1289 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1290 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1292 cprintf("Non speculative list: ");
1294 while (non_spec_it != non_spec_end_it) {
1295 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1296 (*non_spec_it).second->seqNum);
1302 ListOrderIt list_order_it = listOrder.begin();
1303 ListOrderIt list_order_end_it = listOrder.end();
1306 cprintf("List order: ");
1308 while (list_order_it != list_order_end_it) {
1309 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1310 (*list_order_it).oldestInst);
1320 template <class Impl>
1322 InstructionQueue<Impl>::dumpInsts()
1324 for (int i = 0; i < numThreads; ++i) {
1327 ListIt inst_list_it = instList[i].begin();
1329 while (inst_list_it != instList[i].end())
1331 cprintf("Instruction:%i\n",
1333 if (!(*inst_list_it)->isSquashed()) {
1334 if (!(*inst_list_it)->isIssued()) {
1336 cprintf("Count:%i\n", valid_num);
1337 } else if ((*inst_list_it)->isMemRef() &&
1338 !(*inst_list_it)->memOpDone) {
1339 // Loads that have not been marked as executed
1340 // still count towards the total instructions.
1342 cprintf("Count:%i\n", valid_num);
1346 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1347 "Issued:%i\nSquashed:%i\n",
1348 (*inst_list_it)->readPC(),
1349 (*inst_list_it)->seqNum,
1350 (*inst_list_it)->threadNumber,
1351 (*inst_list_it)->isIssued(),
1352 (*inst_list_it)->isSquashed());
1354 if ((*inst_list_it)->isMemRef()) {
1355 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1365 cprintf("Insts to Execute list:\n");
1369 ListIt inst_list_it = instsToExecute.begin();
1371 while (inst_list_it != instsToExecute.end())
1373 cprintf("Instruction:%i\n",
1375 if (!(*inst_list_it)->isSquashed()) {
1376 if (!(*inst_list_it)->isIssued()) {
1378 cprintf("Count:%i\n", valid_num);
1379 } else if ((*inst_list_it)->isMemRef() &&
1380 !(*inst_list_it)->memOpDone) {
1381 // Loads that have not been marked as executed
1382 // still count towards the total instructions.
1384 cprintf("Count:%i\n", valid_num);
1388 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1389 "Issued:%i\nSquashed:%i\n",
1390 (*inst_list_it)->readPC(),
1391 (*inst_list_it)->seqNum,
1392 (*inst_list_it)->threadNumber,
1393 (*inst_list_it)->isIssued(),
1394 (*inst_list_it)->isSquashed());
1396 if ((*inst_list_it)->isMemRef()) {
1397 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);