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5 * The license below extends only to copyright in the software and shall
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47 #include "cpu/o3/fu_pool.hh"
48 #include "cpu/o3/inst_queue.hh"
49 #include "debug/IQ.hh"
50 #include "enums/OpClass.hh"
51 #include "params/DerivO3CPU.hh"
52 #include "sim/core.hh"
54 // clang complains about std::set being overloaded with Packet::set if
55 // we open up the entire namespace std
59 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
60 int fu_idx, InstructionQueue<Impl> *iq_ptr)
61 : Event(Stat_Event_Pri, AutoDelete),
62 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
68 InstructionQueue<Impl>::FUCompletion::process()
70 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
77 InstructionQueue<Impl>::FUCompletion::description() const
79 return "Functional unit completion";
83 InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
84 DerivO3CPUParams *params)
87 fuPool(params->fuPool),
88 numEntries(params->numIQEntries),
89 totalWidth(params->issueWidth),
90 numPhysIntRegs(params->numPhysIntRegs),
91 numPhysFloatRegs(params->numPhysFloatRegs),
92 commitToIEWDelay(params->commitToIEWDelay)
98 numThreads = params->numThreads;
100 // Set the number of physical registers as the number of int + float
101 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
103 //Create an entry for each physical register within the
105 dependGraph.resize(numPhysRegs);
107 // Resize the register scoreboard.
108 regScoreboard.resize(numPhysRegs);
110 //Initialize Mem Dependence Units
111 for (ThreadID tid = 0; tid < numThreads; tid++) {
112 memDepUnit[tid].init(params, tid);
113 memDepUnit[tid].setIQ(this);
118 std::string policy = params->smtIQPolicy;
120 //Convert string to lowercase
121 std::transform(policy.begin(), policy.end(), policy.begin(),
122 (int(*)(int)) tolower);
124 //Figure out resource sharing policy
125 if (policy == "dynamic") {
128 //Set Max Entries to Total ROB Capacity
129 for (ThreadID tid = 0; tid < numThreads; tid++) {
130 maxEntries[tid] = numEntries;
133 } else if (policy == "partitioned") {
134 iqPolicy = Partitioned;
136 //@todo:make work if part_amt doesnt divide evenly.
137 int part_amt = numEntries / numThreads;
139 //Divide ROB up evenly
140 for (ThreadID tid = 0; tid < numThreads; tid++) {
141 maxEntries[tid] = part_amt;
144 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
145 "%i entries per thread.\n",part_amt);
146 } else if (policy == "threshold") {
147 iqPolicy = Threshold;
149 double threshold = (double)params->smtIQThreshold / 100;
151 int thresholdIQ = (int)((double)threshold * numEntries);
153 //Divide up by threshold amount
154 for (ThreadID tid = 0; tid < numThreads; tid++) {
155 maxEntries[tid] = thresholdIQ;
158 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
159 "%i entries per thread.\n",thresholdIQ);
161 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
162 "Partitioned, Threshold}");
166 template <class Impl>
167 InstructionQueue<Impl>::~InstructionQueue()
171 cprintf("Nodes traversed: %i, removed: %i\n",
172 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
176 template <class Impl>
178 InstructionQueue<Impl>::name() const
180 return cpu->name() + ".iq";
183 template <class Impl>
185 InstructionQueue<Impl>::regStats()
187 using namespace Stats;
189 .name(name() + ".iqInstsAdded")
190 .desc("Number of instructions added to the IQ (excludes non-spec)")
191 .prereq(iqInstsAdded);
194 .name(name() + ".iqNonSpecInstsAdded")
195 .desc("Number of non-speculative instructions added to the IQ")
196 .prereq(iqNonSpecInstsAdded);
199 .name(name() + ".iqInstsIssued")
200 .desc("Number of instructions issued")
201 .prereq(iqInstsIssued);
204 .name(name() + ".iqIntInstsIssued")
205 .desc("Number of integer instructions issued")
206 .prereq(iqIntInstsIssued);
209 .name(name() + ".iqFloatInstsIssued")
210 .desc("Number of float instructions issued")
211 .prereq(iqFloatInstsIssued);
214 .name(name() + ".iqBranchInstsIssued")
215 .desc("Number of branch instructions issued")
216 .prereq(iqBranchInstsIssued);
219 .name(name() + ".iqMemInstsIssued")
220 .desc("Number of memory instructions issued")
221 .prereq(iqMemInstsIssued);
224 .name(name() + ".iqMiscInstsIssued")
225 .desc("Number of miscellaneous instructions issued")
226 .prereq(iqMiscInstsIssued);
228 iqSquashedInstsIssued
229 .name(name() + ".iqSquashedInstsIssued")
230 .desc("Number of squashed instructions issued")
231 .prereq(iqSquashedInstsIssued);
233 iqSquashedInstsExamined
234 .name(name() + ".iqSquashedInstsExamined")
235 .desc("Number of squashed instructions iterated over during squash;"
236 " mainly for profiling")
237 .prereq(iqSquashedInstsExamined);
239 iqSquashedOperandsExamined
240 .name(name() + ".iqSquashedOperandsExamined")
241 .desc("Number of squashed operands that are examined and possibly "
242 "removed from graph")
243 .prereq(iqSquashedOperandsExamined);
245 iqSquashedNonSpecRemoved
246 .name(name() + ".iqSquashedNonSpecRemoved")
247 .desc("Number of squashed non-spec instructions that were removed")
248 .prereq(iqSquashedNonSpecRemoved);
251 .init(Num_OpClasses, 0, 99, 2)
252 .name(name() + ".IQ:residence:")
253 .desc("cycles from dispatch to issue")
254 .flags(total | pdf | cdf )
256 for (int i = 0; i < Num_OpClasses; ++i) {
257 queueResDist.subname(i, opClassStrings[i]);
261 .init(0,totalWidth,1)
262 .name(name() + ".issued_per_cycle")
263 .desc("Number of insts issued each cycle")
268 .init(Num_OpClasses+2)
269 .name(name() + ".unissued_cause")
270 .desc("Reason ready instruction not issued")
273 for (int i=0; i < (Num_OpClasses + 2); ++i) {
274 dist_unissued.subname(i, unissued_names[i]);
278 .init(numThreads,Enums::Num_OpClass)
279 .name(name() + ".FU_type")
280 .desc("Type of FU issued")
281 .flags(total | pdf | dist)
283 statIssuedInstType.ysubnames(Enums::OpClassStrings);
286 // How long did instructions for a particular FU type wait prior to issue
290 .init(Num_OpClasses,0,99,2)
292 .desc("cycles from operands ready to issue")
296 for (int i=0; i<Num_OpClasses; ++i) {
297 std::stringstream subname;
298 subname << opClassStrings[i] << "_delay";
299 issueDelayDist.subname(i, subname.str());
303 .name(name() + ".rate")
304 .desc("Inst issue rate")
307 issueRate = iqInstsIssued / cpu->numCycles;
311 .name(name() + ".fu_full")
312 .desc("attempts to use FU when none available")
315 for (int i=0; i < Num_OpClasses; ++i) {
316 statFuBusy.subname(i, Enums::OpClassStrings[i]);
321 .name(name() + ".fu_busy_cnt")
322 .desc("FU busy when requested")
327 .name(name() + ".fu_busy_rate")
328 .desc("FU busy rate (busy events/executed inst)")
331 fuBusyRate = fuBusy / iqInstsIssued;
333 for (ThreadID tid = 0; tid < numThreads; tid++) {
334 // Tell mem dependence unit to reg stats as well.
335 memDepUnit[tid].regStats();
339 .name(name() + ".int_inst_queue_reads")
340 .desc("Number of integer instruction queue reads")
344 .name(name() + ".int_inst_queue_writes")
345 .desc("Number of integer instruction queue writes")
348 intInstQueueWakeupAccesses
349 .name(name() + ".int_inst_queue_wakeup_accesses")
350 .desc("Number of integer instruction queue wakeup accesses")
354 .name(name() + ".fp_inst_queue_reads")
355 .desc("Number of floating instruction queue reads")
359 .name(name() + ".fp_inst_queue_writes")
360 .desc("Number of floating instruction queue writes")
363 fpInstQueueWakeupQccesses
364 .name(name() + ".fp_inst_queue_wakeup_accesses")
365 .desc("Number of floating instruction queue wakeup accesses")
369 .name(name() + ".int_alu_accesses")
370 .desc("Number of integer alu accesses")
374 .name(name() + ".fp_alu_accesses")
375 .desc("Number of floating point alu accesses")
380 template <class Impl>
382 InstructionQueue<Impl>::resetState()
384 //Initialize thread IQ counts
385 for (ThreadID tid = 0; tid <numThreads; tid++) {
387 instList[tid].clear();
390 // Initialize the number of free IQ entries.
391 freeEntries = numEntries;
393 // Note that in actuality, the registers corresponding to the logical
394 // registers start off as ready. However this doesn't matter for the
395 // IQ as the instruction should have been correctly told if those
396 // registers are ready in rename. Thus it can all be initialized as
398 for (int i = 0; i < numPhysRegs; ++i) {
399 regScoreboard[i] = false;
402 for (ThreadID tid = 0; tid < numThreads; ++tid) {
403 squashedSeqNum[tid] = 0;
406 for (int i = 0; i < Num_OpClasses; ++i) {
407 while (!readyInsts[i].empty())
409 queueOnList[i] = false;
410 readyIt[i] = listOrder.end();
412 nonSpecInsts.clear();
414 deferredMemInsts.clear();
417 template <class Impl>
419 InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
421 activeThreads = at_ptr;
424 template <class Impl>
426 InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
428 issueToExecuteQueue = i2e_ptr;
431 template <class Impl>
433 InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
437 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
440 template <class Impl>
442 InstructionQueue<Impl>::switchOut()
445 if (!instList[0].empty() || (numEntries != freeEntries) ||
446 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
453 instsToExecute.clear();
455 for (ThreadID tid = 0; tid < numThreads; ++tid) {
456 memDepUnit[tid].switchOut();
460 template <class Impl>
462 InstructionQueue<Impl>::takeOverFrom()
467 template <class Impl>
469 InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
471 if (iqPolicy == Partitioned) {
472 return numEntries / num_threads;
479 template <class Impl>
481 InstructionQueue<Impl>::resetEntries()
483 if (iqPolicy != Dynamic || numThreads > 1) {
484 int active_threads = activeThreads->size();
486 list<ThreadID>::iterator threads = activeThreads->begin();
487 list<ThreadID>::iterator end = activeThreads->end();
489 while (threads != end) {
490 ThreadID tid = *threads++;
492 if (iqPolicy == Partitioned) {
493 maxEntries[tid] = numEntries / active_threads;
494 } else if(iqPolicy == Threshold && active_threads == 1) {
495 maxEntries[tid] = numEntries;
501 template <class Impl>
503 InstructionQueue<Impl>::numFreeEntries()
508 template <class Impl>
510 InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
512 return maxEntries[tid] - count[tid];
515 // Might want to do something more complex if it knows how many instructions
516 // will be issued this cycle.
517 template <class Impl>
519 InstructionQueue<Impl>::isFull()
521 if (freeEntries == 0) {
528 template <class Impl>
530 InstructionQueue<Impl>::isFull(ThreadID tid)
532 if (numFreeEntries(tid) == 0) {
539 template <class Impl>
541 InstructionQueue<Impl>::hasReadyInsts()
543 if (!listOrder.empty()) {
547 for (int i = 0; i < Num_OpClasses; ++i) {
548 if (!readyInsts[i].empty()) {
556 template <class Impl>
558 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
560 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
561 // Make sure the instruction is valid
564 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
565 new_inst->seqNum, new_inst->pcState());
567 assert(freeEntries != 0);
569 instList[new_inst->threadNumber].push_back(new_inst);
575 // Look through its source registers (physical regs), and mark any
577 addToDependents(new_inst);
579 // Have this instruction set itself as the producer of its destination
581 addToProducers(new_inst);
583 if (new_inst->isMemRef()) {
584 memDepUnit[new_inst->threadNumber].insert(new_inst);
586 addIfReady(new_inst);
591 count[new_inst->threadNumber]++;
593 assert(freeEntries == (numEntries - countInsts()));
596 template <class Impl>
598 InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
600 // @todo: Clean up this code; can do it by setting inst as unable
601 // to issue, then calling normal insert on the inst.
602 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
606 nonSpecInsts[new_inst->seqNum] = new_inst;
608 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
610 new_inst->seqNum, new_inst->pcState());
612 assert(freeEntries != 0);
614 instList[new_inst->threadNumber].push_back(new_inst);
620 // Have this instruction set itself as the producer of its destination
622 addToProducers(new_inst);
624 // If it's a memory instruction, add it to the memory dependency
626 if (new_inst->isMemRef()) {
627 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
630 ++iqNonSpecInstsAdded;
632 count[new_inst->threadNumber]++;
634 assert(freeEntries == (numEntries - countInsts()));
637 template <class Impl>
639 InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
641 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
643 insertNonSpec(barr_inst);
646 template <class Impl>
647 typename Impl::DynInstPtr
648 InstructionQueue<Impl>::getInstToExecute()
650 assert(!instsToExecute.empty());
651 DynInstPtr inst = instsToExecute.front();
652 instsToExecute.pop_front();
653 if (inst->isFloating()){
661 template <class Impl>
663 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
665 assert(!readyInsts[op_class].empty());
667 ListOrderEntry queue_entry;
669 queue_entry.queueType = op_class;
671 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
673 ListOrderIt list_it = listOrder.begin();
674 ListOrderIt list_end_it = listOrder.end();
676 while (list_it != list_end_it) {
677 if ((*list_it).oldestInst > queue_entry.oldestInst) {
684 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
685 queueOnList[op_class] = true;
688 template <class Impl>
690 InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
692 // Get iterator of next item on the list
693 // Delete the original iterator
694 // Determine if the next item is either the end of the list or younger
695 // than the new instruction. If so, then add in a new iterator right here.
696 // If not, then move along.
697 ListOrderEntry queue_entry;
698 OpClass op_class = (*list_order_it).queueType;
699 ListOrderIt next_it = list_order_it;
703 queue_entry.queueType = op_class;
704 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
706 while (next_it != listOrder.end() &&
707 (*next_it).oldestInst < queue_entry.oldestInst) {
711 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
714 template <class Impl>
716 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
718 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
719 // The CPU could have been sleeping until this op completed (*extremely*
720 // long latency op). Wake it if it was. This may be overkill.
721 if (isSwitchedOut()) {
722 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
730 fuPool->freeUnitNextCycle(fu_idx);
732 // @todo: Ensure that these FU Completions happen at the beginning
733 // of a cycle, otherwise they could add too many instructions to
735 issueToExecuteQueue->access(-1)->size++;
736 instsToExecute.push_back(inst);
739 // @todo: Figure out a better way to remove the squashed items from the
740 // lists. Checking the top item of each list to see if it's squashed
741 // wastes time and forces jumps.
742 template <class Impl>
744 InstructionQueue<Impl>::scheduleReadyInsts()
746 DPRINTF(IQ, "Attempting to schedule ready instructions from "
749 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
751 DynInstPtr deferred_mem_inst;
752 int total_deferred_mem_issued = 0;
753 while (total_deferred_mem_issued < totalWidth &&
754 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) {
755 issueToExecuteQueue->access(0)->size++;
756 instsToExecute.push_back(deferred_mem_inst);
757 total_deferred_mem_issued++;
760 // Have iterator to head of the list
761 // While I haven't exceeded bandwidth or reached the end of the list,
762 // Try to get a FU that can do what this op needs.
763 // If successful, change the oldestInst to the new top of the list, put
764 // the queue in the proper place in the list.
765 // Increment the iterator.
766 // This will avoid trying to schedule a certain op class if there are no
767 // FUs that handle it.
768 ListOrderIt order_it = listOrder.begin();
769 ListOrderIt order_end_it = listOrder.end();
770 int total_issued = 0;
772 while (total_issued < (totalWidth - total_deferred_mem_issued) &&
773 iewStage->canIssue() &&
774 order_it != order_end_it) {
775 OpClass op_class = (*order_it).queueType;
777 assert(!readyInsts[op_class].empty());
779 DynInstPtr issuing_inst = readyInsts[op_class].top();
781 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
783 assert(issuing_inst->seqNum == (*order_it).oldestInst);
785 if (issuing_inst->isSquashed()) {
786 readyInsts[op_class].pop();
788 if (!readyInsts[op_class].empty()) {
789 moveToYoungerInst(order_it);
791 readyIt[op_class] = listOrder.end();
792 queueOnList[op_class] = false;
795 listOrder.erase(order_it++);
797 ++iqSquashedInstsIssued;
803 Cycles op_latency = Cycles(1);
804 ThreadID tid = issuing_inst->threadNumber;
806 if (op_class != No_OpClass) {
807 idx = fuPool->getUnit(op_class);
808 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
810 op_latency = fuPool->getOpLatency(op_class);
814 // If we have an instruction that doesn't require a FU, or a
815 // valid FU, then schedule for execution.
816 if (idx == -2 || idx != -1) {
817 if (op_latency == Cycles(1)) {
819 instsToExecute.push_back(issuing_inst);
821 // Add the FU onto the list of FU's to be freed next
822 // cycle if we used one.
824 fuPool->freeUnitNextCycle(idx);
826 Cycles issue_latency = fuPool->getIssueLatency(op_class);
827 // Generate completion event for the FU
828 FUCompletion *execution = new FUCompletion(issuing_inst,
831 cpu->schedule(execution,
832 cpu->clockEdge(Cycles(op_latency - 1)));
834 // @todo: Enforce that issue_latency == 1 or op_latency
835 if (issue_latency > Cycles(1)) {
836 // If FU isn't pipelined, then it must be freed
837 // upon the execution completing.
838 execution->setFreeFU();
840 // Add the FU onto the list of FU's to be freed next cycle.
841 fuPool->freeUnitNextCycle(idx);
845 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
847 tid, issuing_inst->pcState(),
848 issuing_inst->seqNum);
850 readyInsts[op_class].pop();
852 if (!readyInsts[op_class].empty()) {
853 moveToYoungerInst(order_it);
855 readyIt[op_class] = listOrder.end();
856 queueOnList[op_class] = false;
859 issuing_inst->setIssued();
863 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
866 if (!issuing_inst->isMemRef()) {
867 // Memory instructions can not be freed from the IQ until they
871 issuing_inst->clearInIQ();
873 memDepUnit[tid].issue(issuing_inst);
876 listOrder.erase(order_it++);
877 statIssuedInstType[tid][op_class]++;
878 iewStage->incrWb(issuing_inst->seqNum);
880 statFuBusy[op_class]++;
886 numIssuedDist.sample(total_issued);
887 iqInstsIssued+= total_issued;
889 // If we issued any instructions, tell the CPU we had activity.
890 // @todo If the way deferred memory instructions are handeled due to
891 // translation changes then the deferredMemInsts condition should be removed
892 // from the code below.
893 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
894 cpu->activityThisCycle();
896 DPRINTF(IQ, "Not able to schedule any instructions.\n");
900 template <class Impl>
902 InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
904 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
905 "to execute.\n", inst);
907 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
909 assert(inst_it != nonSpecInsts.end());
911 ThreadID tid = (*inst_it).second->threadNumber;
913 (*inst_it).second->setAtCommit();
915 (*inst_it).second->setCanIssue();
917 if (!(*inst_it).second->isMemRef()) {
918 addIfReady((*inst_it).second);
920 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
923 (*inst_it).second = NULL;
925 nonSpecInsts.erase(inst_it);
928 template <class Impl>
930 InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
932 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
935 ListIt iq_it = instList[tid].begin();
937 while (iq_it != instList[tid].end() &&
938 (*iq_it)->seqNum <= inst) {
940 instList[tid].pop_front();
943 assert(freeEntries == (numEntries - countInsts()));
946 template <class Impl>
948 InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
952 // The instruction queue here takes care of both floating and int ops
953 if (completed_inst->isFloating()) {
954 fpInstQueueWakeupQccesses++;
956 intInstQueueWakeupAccesses++;
959 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
961 assert(!completed_inst->isSquashed());
963 // Tell the memory dependence unit to wake any dependents on this
964 // instruction if it is a memory instruction. Also complete the memory
965 // instruction at this point since we know it executed without issues.
966 // @todo: Might want to rename "completeMemInst" to something that
967 // indicates that it won't need to be replayed, and call this
968 // earlier. Might not be a big deal.
969 if (completed_inst->isMemRef()) {
970 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
971 completeMemInst(completed_inst);
972 } else if (completed_inst->isMemBarrier() ||
973 completed_inst->isWriteBarrier()) {
974 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
977 for (int dest_reg_idx = 0;
978 dest_reg_idx < completed_inst->numDestRegs();
981 PhysRegIndex dest_reg =
982 completed_inst->renamedDestRegIdx(dest_reg_idx);
984 // Special case of uniq or control registers. They are not
985 // handled by the IQ and thus have no dependency graph entry.
986 // @todo Figure out a cleaner way to handle this.
987 if (dest_reg >= numPhysRegs) {
988 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
993 DPRINTF(IQ, "Waking any dependents on register %i.\n",
996 //Go through the dependency chain, marking the registers as
997 //ready within the waiting instructions.
998 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
1001 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1002 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1004 // Might want to give more information to the instruction
1005 // so that it knows which of its source registers is
1006 // ready. However that would mean that the dependency
1007 // graph entries would need to hold the src_reg_idx.
1008 dep_inst->markSrcRegReady();
1010 addIfReady(dep_inst);
1012 dep_inst = dependGraph.pop(dest_reg);
1017 // Reset the head node now that all of its dependents have
1019 assert(dependGraph.empty(dest_reg));
1020 dependGraph.clearInst(dest_reg);
1022 // Mark the scoreboard as having that register ready.
1023 regScoreboard[dest_reg] = true;
1028 template <class Impl>
1030 InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1032 OpClass op_class = ready_inst->opClass();
1034 readyInsts[op_class].push(ready_inst);
1036 // Will need to reorder the list if either a queue is not on the list,
1037 // or it has an older instruction than last time.
1038 if (!queueOnList[op_class]) {
1039 addToOrderList(op_class);
1040 } else if (readyInsts[op_class].top()->seqNum <
1041 (*readyIt[op_class]).oldestInst) {
1042 listOrder.erase(readyIt[op_class]);
1043 addToOrderList(op_class);
1046 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1047 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1048 ready_inst->pcState(), op_class, ready_inst->seqNum);
1051 template <class Impl>
1053 InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1055 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1057 // Reset DTB translation state
1058 resched_inst->translationStarted(false);
1059 resched_inst->translationCompleted(false);
1061 resched_inst->clearCanIssue();
1062 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1065 template <class Impl>
1067 InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1069 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
1072 template <class Impl>
1074 InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1076 ThreadID tid = completed_inst->threadNumber;
1078 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1079 completed_inst->pcState(), completed_inst->seqNum);
1083 completed_inst->memOpDone(true);
1085 memDepUnit[tid].completed(completed_inst);
1089 template <class Impl>
1091 InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1093 deferredMemInsts.push_back(deferred_inst);
1096 template <class Impl>
1097 typename Impl::DynInstPtr
1098 InstructionQueue<Impl>::getDeferredMemInstToExecute()
1100 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1102 if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1103 DynInstPtr ret = *it;
1104 deferredMemInsts.erase(it);
1111 template <class Impl>
1113 InstructionQueue<Impl>::violation(DynInstPtr &store,
1114 DynInstPtr &faulting_load)
1116 intInstQueueWrites++;
1117 memDepUnit[store->threadNumber].violation(store, faulting_load);
1120 template <class Impl>
1122 InstructionQueue<Impl>::squash(ThreadID tid)
1124 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1127 // Read instruction sequence number of last instruction out of the
1129 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1131 // Call doSquash if there are insts in the IQ
1132 if (count[tid] > 0) {
1136 // Also tell the memory dependence unit to squash.
1137 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1140 template <class Impl>
1142 InstructionQueue<Impl>::doSquash(ThreadID tid)
1144 // Start at the tail.
1145 ListIt squash_it = instList[tid].end();
1148 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1149 tid, squashedSeqNum[tid]);
1151 // Squash any instructions younger than the squashed sequence number
1153 while (squash_it != instList[tid].end() &&
1154 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1156 DynInstPtr squashed_inst = (*squash_it);
1157 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1159 // Only handle the instruction if it actually is in the IQ and
1160 // hasn't already been squashed in the IQ.
1161 if (squashed_inst->threadNumber != tid ||
1162 squashed_inst->isSquashedInIQ()) {
1167 if (!squashed_inst->isIssued() ||
1168 (squashed_inst->isMemRef() &&
1169 !squashed_inst->memOpDone())) {
1171 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1172 tid, squashed_inst->seqNum, squashed_inst->pcState());
1174 // Remove the instruction from the dependency list.
1175 if (!squashed_inst->isNonSpeculative() &&
1176 !squashed_inst->isStoreConditional() &&
1177 !squashed_inst->isMemBarrier() &&
1178 !squashed_inst->isWriteBarrier()) {
1180 for (int src_reg_idx = 0;
1181 src_reg_idx < squashed_inst->numSrcRegs();
1184 PhysRegIndex src_reg =
1185 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1187 // Only remove it from the dependency graph if it
1188 // was placed there in the first place.
1190 // Instead of doing a linked list traversal, we
1191 // can just remove these squashed instructions
1192 // either at issue time, or when the register is
1193 // overwritten. The only downside to this is it
1194 // leaves more room for error.
1196 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1197 src_reg < numPhysRegs) {
1198 dependGraph.remove(src_reg, squashed_inst);
1202 ++iqSquashedOperandsExamined;
1204 } else if (!squashed_inst->isStoreConditional() ||
1205 !squashed_inst->isCompleted()) {
1206 NonSpecMapIt ns_inst_it =
1207 nonSpecInsts.find(squashed_inst->seqNum);
1209 if (ns_inst_it == nonSpecInsts.end()) {
1210 assert(squashed_inst->getFault() != NoFault);
1213 (*ns_inst_it).second = NULL;
1215 nonSpecInsts.erase(ns_inst_it);
1217 ++iqSquashedNonSpecRemoved;
1221 // Might want to also clear out the head of the dependency graph.
1223 // Mark it as squashed within the IQ.
1224 squashed_inst->setSquashedInIQ();
1226 // @todo: Remove this hack where several statuses are set so the
1227 // inst will flow through the rest of the pipeline.
1228 squashed_inst->setIssued();
1229 squashed_inst->setCanCommit();
1230 squashed_inst->clearInIQ();
1232 //Update Thread IQ Count
1233 count[squashed_inst->threadNumber]--;
1238 instList[tid].erase(squash_it--);
1239 ++iqSquashedInstsExamined;
1243 template <class Impl>
1245 InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1247 // Loop through the instruction's source registers, adding
1248 // them to the dependency list if they are not ready.
1249 int8_t total_src_regs = new_inst->numSrcRegs();
1250 bool return_val = false;
1252 for (int src_reg_idx = 0;
1253 src_reg_idx < total_src_regs;
1256 // Only add it to the dependency graph if it's not ready.
1257 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1258 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1260 // Check the IQ's scoreboard to make sure the register
1261 // hasn't become ready while the instruction was in flight
1262 // between stages. Only if it really isn't ready should
1263 // it be added to the dependency graph.
1264 if (src_reg >= numPhysRegs) {
1266 } else if (regScoreboard[src_reg] == false) {
1267 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1268 "is being added to the dependency chain.\n",
1269 new_inst->pcState(), src_reg);
1271 dependGraph.insert(src_reg, new_inst);
1273 // Change the return value to indicate that something
1274 // was added to the dependency graph.
1277 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1278 "became ready before it reached the IQ.\n",
1279 new_inst->pcState(), src_reg);
1280 // Mark a register ready within the instruction.
1281 new_inst->markSrcRegReady(src_reg_idx);
1289 template <class Impl>
1291 InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1293 // Nothing really needs to be marked when an instruction becomes
1294 // the producer of a register's value, but for convenience a ptr
1295 // to the producing instruction will be placed in the head node of
1296 // the dependency links.
1297 int8_t total_dest_regs = new_inst->numDestRegs();
1299 for (int dest_reg_idx = 0;
1300 dest_reg_idx < total_dest_regs;
1303 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1305 // Instructions that use the misc regs will have a reg number
1306 // higher than the normal physical registers. In this case these
1307 // registers are not renamed, and there is no need to track
1308 // dependencies as these instructions must be executed at commit.
1309 if (dest_reg >= numPhysRegs) {
1313 if (!dependGraph.empty(dest_reg)) {
1315 panic("Dependency graph %i not empty!", dest_reg);
1318 dependGraph.setInst(dest_reg, new_inst);
1320 // Mark the scoreboard to say it's not yet ready.
1321 regScoreboard[dest_reg] = false;
1325 template <class Impl>
1327 InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1329 // If the instruction now has all of its source registers
1330 // available, then add it to the list of ready instructions.
1331 if (inst->readyToIssue()) {
1333 //Add the instruction to the proper ready list.
1334 if (inst->isMemRef()) {
1336 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1338 // Message to the mem dependence unit that this instruction has
1339 // its registers ready.
1340 memDepUnit[inst->threadNumber].regsReady(inst);
1345 OpClass op_class = inst->opClass();
1347 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1348 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1349 inst->pcState(), op_class, inst->seqNum);
1351 readyInsts[op_class].push(inst);
1353 // Will need to reorder the list if either a queue is not on the list,
1354 // or it has an older instruction than last time.
1355 if (!queueOnList[op_class]) {
1356 addToOrderList(op_class);
1357 } else if (readyInsts[op_class].top()->seqNum <
1358 (*readyIt[op_class]).oldestInst) {
1359 listOrder.erase(readyIt[op_class]);
1360 addToOrderList(op_class);
1365 template <class Impl>
1367 InstructionQueue<Impl>::countInsts()
1370 //ksewell:This works but definitely could use a cleaner write
1371 //with a more intuitive way of counting. Right now it's
1372 //just brute force ....
1373 // Change the #if if you want to use this method.
1374 int total_insts = 0;
1376 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1377 ListIt count_it = instList[tid].begin();
1379 while (count_it != instList[tid].end()) {
1380 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1381 if (!(*count_it)->isIssued()) {
1383 } else if ((*count_it)->isMemRef() &&
1384 !(*count_it)->memOpDone) {
1385 // Loads that have not been marked as executed still count
1386 // towards the total instructions.
1397 return numEntries - freeEntries;
1401 template <class Impl>
1403 InstructionQueue<Impl>::dumpLists()
1405 for (int i = 0; i < Num_OpClasses; ++i) {
1406 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1411 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1413 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1414 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1416 cprintf("Non speculative list: ");
1418 while (non_spec_it != non_spec_end_it) {
1419 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1420 (*non_spec_it).second->seqNum);
1426 ListOrderIt list_order_it = listOrder.begin();
1427 ListOrderIt list_order_end_it = listOrder.end();
1430 cprintf("List order: ");
1432 while (list_order_it != list_order_end_it) {
1433 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1434 (*list_order_it).oldestInst);
1444 template <class Impl>
1446 InstructionQueue<Impl>::dumpInsts()
1448 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1451 ListIt inst_list_it = instList[tid].begin();
1453 while (inst_list_it != instList[tid].end()) {
1454 cprintf("Instruction:%i\n", num);
1455 if (!(*inst_list_it)->isSquashed()) {
1456 if (!(*inst_list_it)->isIssued()) {
1458 cprintf("Count:%i\n", valid_num);
1459 } else if ((*inst_list_it)->isMemRef() &&
1460 !(*inst_list_it)->memOpDone()) {
1461 // Loads that have not been marked as executed
1462 // still count towards the total instructions.
1464 cprintf("Count:%i\n", valid_num);
1468 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1469 "Issued:%i\nSquashed:%i\n",
1470 (*inst_list_it)->pcState(),
1471 (*inst_list_it)->seqNum,
1472 (*inst_list_it)->threadNumber,
1473 (*inst_list_it)->isIssued(),
1474 (*inst_list_it)->isSquashed());
1476 if ((*inst_list_it)->isMemRef()) {
1477 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1487 cprintf("Insts to Execute list:\n");
1491 ListIt inst_list_it = instsToExecute.begin();
1493 while (inst_list_it != instsToExecute.end())
1495 cprintf("Instruction:%i\n",
1497 if (!(*inst_list_it)->isSquashed()) {
1498 if (!(*inst_list_it)->isIssued()) {
1500 cprintf("Count:%i\n", valid_num);
1501 } else if ((*inst_list_it)->isMemRef() &&
1502 !(*inst_list_it)->memOpDone()) {
1503 // Loads that have not been marked as executed
1504 // still count towards the total instructions.
1506 cprintf("Count:%i\n", valid_num);
1510 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1511 "Issued:%i\nSquashed:%i\n",
1512 (*inst_list_it)->pcState(),
1513 (*inst_list_it)->seqNum,
1514 (*inst_list_it)->threadNumber,
1515 (*inst_list_it)->isIssued(),
1516 (*inst_list_it)->isSquashed());
1518 if ((*inst_list_it)->isMemRef()) {
1519 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());