src/cpu/o3/inst_queue_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include <limits>
  45 #include <vector>
  46
  47 #include "cpu/o3/fu_pool.hh"
  48 #include "cpu/o3/inst_queue.hh"
  49 #include "debug/IQ.hh"
  50 #include "enums/OpClass.hh"
  51 #include "params/DerivO3CPU.hh"
  52 #include "sim/core.hh"
  53
  54 // clang complains about std::set being overloaded with Packet::set if
  55 // we open up the entire namespace std
  56 using std::list;
  57
  58 template <class Impl>
  59 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
  60     int fu_idx, InstructionQueue<Impl> *iq_ptr)
  61     : Event(Stat_Event_Pri, AutoDelete),
  62       inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
  63 {
  64 }
  65
  66 template <class Impl>
  67 void
  68 InstructionQueue<Impl>::FUCompletion::process()
  69 {
  70     iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
  71     inst = NULL;
  72 }
  73
  74
  75 template <class Impl>
  76 const char *
  77 InstructionQueue<Impl>::FUCompletion::description() const
  78 {
  79     return "Functional unit completion";
  80 }
  81
  82 template <class Impl>
  83 InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
  84                                          DerivO3CPUParams *params)
  85     : cpu(cpu_ptr),
  86       iewStage(iew_ptr),
  87       fuPool(params->fuPool),
  88       numEntries(params->numIQEntries),
  89       totalWidth(params->issueWidth),
  90       numPhysIntRegs(params->numPhysIntRegs),
  91       numPhysFloatRegs(params->numPhysFloatRegs),
  92       commitToIEWDelay(params->commitToIEWDelay)
  93 {
  94     assert(fuPool);
  95
  96     switchedOut = false;
  97
  98     numThreads = params->numThreads;
  99
 100     // Set the number of physical registers as the number of int + float
 101     numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
 102
 103     //Create an entry for each physical register within the
 104     //dependency graph.
 105     dependGraph.resize(numPhysRegs);
 106
 107     // Resize the register scoreboard.
 108     regScoreboard.resize(numPhysRegs);
 109
 110     //Initialize Mem Dependence Units
 111     for (ThreadID tid = 0; tid < numThreads; tid++) {
 112         memDepUnit[tid].init(params, tid);
 113         memDepUnit[tid].setIQ(this);
 114     }
 115
 116     resetState();
 117
 118     std::string policy = params->smtIQPolicy;
 119
 120     //Convert string to lowercase
 121     std::transform(policy.begin(), policy.end(), policy.begin(),
 122                    (int(*)(int)) tolower);
 123
 124     //Figure out resource sharing policy
 125     if (policy == "dynamic") {
 126         iqPolicy = Dynamic;
 127
 128         //Set Max Entries to Total ROB Capacity
 129         for (ThreadID tid = 0; tid < numThreads; tid++) {
 130             maxEntries[tid] = numEntries;
 131         }
 132
 133     } else if (policy == "partitioned") {
 134         iqPolicy = Partitioned;
 135
 136         //@todo:make work if part_amt doesnt divide evenly.
 137         int part_amt = numEntries / numThreads;
 138
 139         //Divide ROB up evenly
 140         for (ThreadID tid = 0; tid < numThreads; tid++) {
 141             maxEntries[tid] = part_amt;
 142         }
 143
 144         DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
 145                 "%i entries per thread.\n",part_amt);
 146     } else if (policy == "threshold") {
 147         iqPolicy = Threshold;
 148
 149         double threshold =  (double)params->smtIQThreshold / 100;
 150
 151         int thresholdIQ = (int)((double)threshold * numEntries);
 152
 153         //Divide up by threshold amount
 154         for (ThreadID tid = 0; tid < numThreads; tid++) {
 155             maxEntries[tid] = thresholdIQ;
 156         }
 157
 158         DPRINTF(IQ, "IQ sharing policy set to Threshold:"
 159                 "%i entries per thread.\n",thresholdIQ);
 160    } else {
 161        assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
 162               "Partitioned, Threshold}");
 163    }
 164 }
 165
 166 template <class Impl>
 167 InstructionQueue<Impl>::~InstructionQueue()
 168 {
 169     dependGraph.reset();
 170 #ifdef DEBUG
 171     cprintf("Nodes traversed: %i, removed: %i\n",
 172             dependGraph.nodesTraversed, dependGraph.nodesRemoved);
 173 #endif
 174 }
 175
 176 template <class Impl>
 177 std::string
 178 InstructionQueue<Impl>::name() const
 179 {
 180     return cpu->name() + ".iq";
 181 }
 182
 183 template <class Impl>
 184 void
 185 InstructionQueue<Impl>::regStats()
 186 {
 187     using namespace Stats;
 188     iqInstsAdded
 189         .name(name() + ".iqInstsAdded")
 190         .desc("Number of instructions added to the IQ (excludes non-spec)")
 191         .prereq(iqInstsAdded);
 192
 193     iqNonSpecInstsAdded
 194         .name(name() + ".iqNonSpecInstsAdded")
 195         .desc("Number of non-speculative instructions added to the IQ")
 196         .prereq(iqNonSpecInstsAdded);
 197
 198     iqInstsIssued
 199         .name(name() + ".iqInstsIssued")
 200         .desc("Number of instructions issued")
 201         .prereq(iqInstsIssued);
 202
 203     iqIntInstsIssued
 204         .name(name() + ".iqIntInstsIssued")
 205         .desc("Number of integer instructions issued")
 206         .prereq(iqIntInstsIssued);
 207
 208     iqFloatInstsIssued
 209         .name(name() + ".iqFloatInstsIssued")
 210         .desc("Number of float instructions issued")
 211         .prereq(iqFloatInstsIssued);
 212
 213     iqBranchInstsIssued
 214         .name(name() + ".iqBranchInstsIssued")
 215         .desc("Number of branch instructions issued")
 216         .prereq(iqBranchInstsIssued);
 217
 218     iqMemInstsIssued
 219         .name(name() + ".iqMemInstsIssued")
 220         .desc("Number of memory instructions issued")
 221         .prereq(iqMemInstsIssued);
 222
 223     iqMiscInstsIssued
 224         .name(name() + ".iqMiscInstsIssued")
 225         .desc("Number of miscellaneous instructions issued")
 226         .prereq(iqMiscInstsIssued);
 227
 228     iqSquashedInstsIssued
 229         .name(name() + ".iqSquashedInstsIssued")
 230         .desc("Number of squashed instructions issued")
 231         .prereq(iqSquashedInstsIssued);
 232
 233     iqSquashedInstsExamined
 234         .name(name() + ".iqSquashedInstsExamined")
 235         .desc("Number of squashed instructions iterated over during squash;"
 236               " mainly for profiling")
 237         .prereq(iqSquashedInstsExamined);
 238
 239     iqSquashedOperandsExamined
 240         .name(name() + ".iqSquashedOperandsExamined")
 241         .desc("Number of squashed operands that are examined and possibly "
 242               "removed from graph")
 243         .prereq(iqSquashedOperandsExamined);
 244
 245     iqSquashedNonSpecRemoved
 246         .name(name() + ".iqSquashedNonSpecRemoved")
 247         .desc("Number of squashed non-spec instructions that were removed")
 248         .prereq(iqSquashedNonSpecRemoved);
 249 /*
 250     queueResDist
 251         .init(Num_OpClasses, 0, 99, 2)
 252         .name(name() + ".IQ:residence:")
 253         .desc("cycles from dispatch to issue")
 254         .flags(total | pdf | cdf )
 255         ;
 256     for (int i = 0; i < Num_OpClasses; ++i) {
 257         queueResDist.subname(i, opClassStrings[i]);
 258     }
 259 */
 260     numIssuedDist
 261         .init(0,totalWidth,1)
 262         .name(name() + ".issued_per_cycle")
 263         .desc("Number of insts issued each cycle")
 264         .flags(pdf)
 265         ;
 266 /*
 267     dist_unissued
 268         .init(Num_OpClasses+2)
 269         .name(name() + ".unissued_cause")
 270         .desc("Reason ready instruction not issued")
 271         .flags(pdf | dist)
 272         ;
 273     for (int i=0; i < (Num_OpClasses + 2); ++i) {
 274         dist_unissued.subname(i, unissued_names[i]);
 275     }
 276 */
 277     statIssuedInstType
 278         .init(numThreads,Enums::Num_OpClass)
 279         .name(name() + ".FU_type")
 280         .desc("Type of FU issued")
 281         .flags(total | pdf | dist)
 282         ;
 283     statIssuedInstType.ysubnames(Enums::OpClassStrings);
 284
 285     //
 286     //  How long did instructions for a particular FU type wait prior to issue
 287     //
 288 /*
 289     issueDelayDist
 290         .init(Num_OpClasses,0,99,2)
 291         .name(name() + ".")
 292         .desc("cycles from operands ready to issue")
 293         .flags(pdf | cdf)
 294         ;
 295
 296     for (int i=0; i<Num_OpClasses; ++i) {
 297         std::stringstream subname;
 298         subname << opClassStrings[i] << "_delay";
 299         issueDelayDist.subname(i, subname.str());
 300     }
 301 */
 302     issueRate
 303         .name(name() + ".rate")
 304         .desc("Inst issue rate")
 305         .flags(total)
 306         ;
 307     issueRate = iqInstsIssued / cpu->numCycles;
 308
 309     statFuBusy
 310         .init(Num_OpClasses)
 311         .name(name() + ".fu_full")
 312         .desc("attempts to use FU when none available")
 313         .flags(pdf | dist)
 314         ;
 315     for (int i=0; i < Num_OpClasses; ++i) {
 316         statFuBusy.subname(i, Enums::OpClassStrings[i]);
 317     }
 318
 319     fuBusy
 320         .init(numThreads)
 321         .name(name() + ".fu_busy_cnt")
 322         .desc("FU busy when requested")
 323         .flags(total)
 324         ;
 325
 326     fuBusyRate
 327         .name(name() + ".fu_busy_rate")
 328         .desc("FU busy rate (busy events/executed inst)")
 329         .flags(total)
 330         ;
 331     fuBusyRate = fuBusy / iqInstsIssued;
 332
 333     for (ThreadID tid = 0; tid < numThreads; tid++) {
 334         // Tell mem dependence unit to reg stats as well.
 335         memDepUnit[tid].regStats();
 336     }
 337
 338     intInstQueueReads
 339         .name(name() + ".int_inst_queue_reads")
 340         .desc("Number of integer instruction queue reads")
 341         .flags(total);
 342
 343     intInstQueueWrites
 344         .name(name() + ".int_inst_queue_writes")
 345         .desc("Number of integer instruction queue writes")
 346         .flags(total);
 347
 348     intInstQueueWakeupAccesses
 349         .name(name() + ".int_inst_queue_wakeup_accesses")
 350         .desc("Number of integer instruction queue wakeup accesses")
 351         .flags(total);
 352
 353     fpInstQueueReads
 354         .name(name() + ".fp_inst_queue_reads")
 355         .desc("Number of floating instruction queue reads")
 356         .flags(total);
 357
 358     fpInstQueueWrites
 359         .name(name() + ".fp_inst_queue_writes")
 360         .desc("Number of floating instruction queue writes")
 361         .flags(total);
 362
 363     fpInstQueueWakeupQccesses
 364         .name(name() + ".fp_inst_queue_wakeup_accesses")
 365         .desc("Number of floating instruction queue wakeup accesses")
 366         .flags(total);
 367
 368     intAluAccesses
 369         .name(name() + ".int_alu_accesses")
 370         .desc("Number of integer alu accesses")
 371         .flags(total);
 372
 373     fpAluAccesses
 374         .name(name() + ".fp_alu_accesses")
 375         .desc("Number of floating point alu accesses")
 376         .flags(total);
 377
 378 }
 379
 380 template <class Impl>
 381 void
 382 InstructionQueue<Impl>::resetState()
 383 {
 384     //Initialize thread IQ counts
 385     for (ThreadID tid = 0; tid <numThreads; tid++) {
 386         count[tid] = 0;
 387         instList[tid].clear();
 388     }
 389
 390     // Initialize the number of free IQ entries.
 391     freeEntries = numEntries;
 392
 393     // Note that in actuality, the registers corresponding to the logical
 394     // registers start off as ready.  However this doesn't matter for the
 395     // IQ as the instruction should have been correctly told if those
 396     // registers are ready in rename.  Thus it can all be initialized as
 397     // unready.
 398     for (int i = 0; i < numPhysRegs; ++i) {
 399         regScoreboard[i] = false;
 400     }
 401
 402     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 403         squashedSeqNum[tid] = 0;
 404     }
 405
 406     for (int i = 0; i < Num_OpClasses; ++i) {
 407         while (!readyInsts[i].empty())
 408             readyInsts[i].pop();
 409         queueOnList[i] = false;
 410         readyIt[i] = listOrder.end();
 411     }
 412     nonSpecInsts.clear();
 413     listOrder.clear();
 414     deferredMemInsts.clear();
 415 }
 416
 417 template <class Impl>
 418 void
 419 InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 420 {
 421     activeThreads = at_ptr;
 422 }
 423
 424 template <class Impl>
 425 void
 426 InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
 427 {
 428       issueToExecuteQueue = i2e_ptr;
 429 }
 430
 431 template <class Impl>
 432 void
 433 InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 434 {
 435     timeBuffer = tb_ptr;
 436
 437     fromCommit = timeBuffer->getWire(-commitToIEWDelay);
 438 }
 439
 440 template <class Impl>
 441 void
 442 InstructionQueue<Impl>::switchOut()
 443 {
 444 /*
 445     if (!instList[0].empty() || (numEntries != freeEntries) ||
 446         !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
 447         dumpInsts();
 448 //        assert(0);
 449     }
 450 */
 451     resetState();
 452     dependGraph.reset();
 453     instsToExecute.clear();
 454     switchedOut = true;
 455     for (ThreadID tid = 0; tid < numThreads; ++tid) {
 456         memDepUnit[tid].switchOut();
 457     }
 458 }
 459
 460 template <class Impl>
 461 void
 462 InstructionQueue<Impl>::takeOverFrom()
 463 {
 464     switchedOut = false;
 465 }
 466
 467 template <class Impl>
 468 int
 469 InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
 470 {
 471     if (iqPolicy == Partitioned) {
 472         return numEntries / num_threads;
 473     } else {
 474         return 0;
 475     }
 476 }
 477
 478
 479 template <class Impl>
 480 void
 481 InstructionQueue<Impl>::resetEntries()
 482 {
 483     if (iqPolicy != Dynamic || numThreads > 1) {
 484         int active_threads = activeThreads->size();
 485
 486         list<ThreadID>::iterator threads = activeThreads->begin();
 487         list<ThreadID>::iterator end = activeThreads->end();
 488
 489         while (threads != end) {
 490             ThreadID tid = *threads++;
 491
 492             if (iqPolicy == Partitioned) {
 493                 maxEntries[tid] = numEntries / active_threads;
 494             } else if(iqPolicy == Threshold && active_threads == 1) {
 495                 maxEntries[tid] = numEntries;
 496             }
 497         }
 498     }
 499 }
 500
 501 template <class Impl>
 502 unsigned
 503 InstructionQueue<Impl>::numFreeEntries()
 504 {
 505     return freeEntries;
 506 }
 507
 508 template <class Impl>
 509 unsigned
 510 InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
 511 {
 512     return maxEntries[tid] - count[tid];
 513 }
 514
 515 // Might want to do something more complex if it knows how many instructions
 516 // will be issued this cycle.
 517 template <class Impl>
 518 bool
 519 InstructionQueue<Impl>::isFull()
 520 {
 521     if (freeEntries == 0) {
 522         return(true);
 523     } else {
 524         return(false);
 525     }
 526 }
 527
 528 template <class Impl>
 529 bool
 530 InstructionQueue<Impl>::isFull(ThreadID tid)
 531 {
 532     if (numFreeEntries(tid) == 0) {
 533         return(true);
 534     } else {
 535         return(false);
 536     }
 537 }
 538
 539 template <class Impl>
 540 bool
 541 InstructionQueue<Impl>::hasReadyInsts()
 542 {
 543     if (!listOrder.empty()) {
 544         return true;
 545     }
 546
 547     for (int i = 0; i < Num_OpClasses; ++i) {
 548         if (!readyInsts[i].empty()) {
 549             return true;
 550         }
 551     }
 552
 553     return false;
 554 }
 555
 556 template <class Impl>
 557 void
 558 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
 559 {
 560     new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
 561     // Make sure the instruction is valid
 562     assert(new_inst);
 563
 564     DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
 565             new_inst->seqNum, new_inst->pcState());
 566
 567     assert(freeEntries != 0);
 568
 569     instList[new_inst->threadNumber].push_back(new_inst);
 570
 571     --freeEntries;
 572
 573     new_inst->setInIQ();
 574
 575     // Look through its source registers (physical regs), and mark any
 576     // dependencies.
 577     addToDependents(new_inst);
 578
 579     // Have this instruction set itself as the producer of its destination
 580     // register(s).
 581     addToProducers(new_inst);
 582
 583     if (new_inst->isMemRef()) {
 584         memDepUnit[new_inst->threadNumber].insert(new_inst);
 585     } else {
 586         addIfReady(new_inst);
 587     }
 588
 589     ++iqInstsAdded;
 590
 591     count[new_inst->threadNumber]++;
 592
 593     assert(freeEntries == (numEntries - countInsts()));
 594 }
 595
 596 template <class Impl>
 597 void
 598 InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
 599 {
 600     // @todo: Clean up this code; can do it by setting inst as unable
 601     // to issue, then calling normal insert on the inst.
 602     new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
 603
 604     assert(new_inst);
 605
 606     nonSpecInsts[new_inst->seqNum] = new_inst;
 607
 608     DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
 609             "to the IQ.\n",
 610             new_inst->seqNum, new_inst->pcState());
 611
 612     assert(freeEntries != 0);
 613
 614     instList[new_inst->threadNumber].push_back(new_inst);
 615
 616     --freeEntries;
 617
 618     new_inst->setInIQ();
 619
 620     // Have this instruction set itself as the producer of its destination
 621     // register(s).
 622     addToProducers(new_inst);
 623
 624     // If it's a memory instruction, add it to the memory dependency
 625     // unit.
 626     if (new_inst->isMemRef()) {
 627         memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
 628     }
 629
 630     ++iqNonSpecInstsAdded;
 631
 632     count[new_inst->threadNumber]++;
 633
 634     assert(freeEntries == (numEntries - countInsts()));
 635 }
 636
 637 template <class Impl>
 638 void
 639 InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
 640 {
 641     memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
 642
 643     insertNonSpec(barr_inst);
 644 }
 645
 646 template <class Impl>
 647 typename Impl::DynInstPtr
 648 InstructionQueue<Impl>::getInstToExecute()
 649 {
 650     assert(!instsToExecute.empty());
 651     DynInstPtr inst = instsToExecute.front();
 652     instsToExecute.pop_front();
 653     if (inst->isFloating()){
 654         fpInstQueueReads++;
 655     } else {
 656         intInstQueueReads++;
 657     }
 658     return inst;
 659 }
 660
 661 template <class Impl>
 662 void
 663 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
 664 {
 665     assert(!readyInsts[op_class].empty());
 666
 667     ListOrderEntry queue_entry;
 668
 669     queue_entry.queueType = op_class;
 670
 671     queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
 672
 673     ListOrderIt list_it = listOrder.begin();
 674     ListOrderIt list_end_it = listOrder.end();
 675
 676     while (list_it != list_end_it) {
 677         if ((*list_it).oldestInst > queue_entry.oldestInst) {
 678             break;
 679         }
 680
 681         list_it++;
 682     }
 683
 684     readyIt[op_class] = listOrder.insert(list_it, queue_entry);
 685     queueOnList[op_class] = true;
 686 }
 687
 688 template <class Impl>
 689 void
 690 InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
 691 {
 692     // Get iterator of next item on the list
 693     // Delete the original iterator
 694     // Determine if the next item is either the end of the list or younger
 695     // than the new instruction.  If so, then add in a new iterator right here.
 696     // If not, then move along.
 697     ListOrderEntry queue_entry;
 698     OpClass op_class = (*list_order_it).queueType;
 699     ListOrderIt next_it = list_order_it;
 700
 701     ++next_it;
 702
 703     queue_entry.queueType = op_class;
 704     queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
 705
 706     while (next_it != listOrder.end() &&
 707            (*next_it).oldestInst < queue_entry.oldestInst) {
 708         ++next_it;
 709     }
 710
 711     readyIt[op_class] = listOrder.insert(next_it, queue_entry);
 712 }
 713
 714 template <class Impl>
 715 void
 716 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
 717 {
 718     DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
 719     // The CPU could have been sleeping until this op completed (*extremely*
 720     // long latency op).  Wake it if it was.  This may be overkill.
 721     if (isSwitchedOut()) {
 722         DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
 723                 inst->seqNum);
 724         return;
 725     }
 726
 727     iewStage->wakeCPU();
 728
 729     if (fu_idx > -1)
 730         fuPool->freeUnitNextCycle(fu_idx);
 731
 732     // @todo: Ensure that these FU Completions happen at the beginning
 733     // of a cycle, otherwise they could add too many instructions to
 734     // the queue.
 735     issueToExecuteQueue->access(-1)->size++;
 736     instsToExecute.push_back(inst);
 737 }
 738
 739 // @todo: Figure out a better way to remove the squashed items from the
 740 // lists.  Checking the top item of each list to see if it's squashed
 741 // wastes time and forces jumps.
 742 template <class Impl>
 743 void
 744 InstructionQueue<Impl>::scheduleReadyInsts()
 745 {
 746     DPRINTF(IQ, "Attempting to schedule ready instructions from "
 747             "the IQ.\n");
 748
 749     IssueStruct *i2e_info = issueToExecuteQueue->access(0);
 750
 751     DynInstPtr deferred_mem_inst;
 752     int total_deferred_mem_issued = 0;
 753     while (total_deferred_mem_issued < totalWidth &&
 754            (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) {
 755         issueToExecuteQueue->access(0)->size++;
 756         instsToExecute.push_back(deferred_mem_inst);
 757         total_deferred_mem_issued++;
 758     }
 759
 760     // Have iterator to head of the list
 761     // While I haven't exceeded bandwidth or reached the end of the list,
 762     // Try to get a FU that can do what this op needs.
 763     // If successful, change the oldestInst to the new top of the list, put
 764     // the queue in the proper place in the list.
 765     // Increment the iterator.
 766     // This will avoid trying to schedule a certain op class if there are no
 767     // FUs that handle it.
 768     ListOrderIt order_it = listOrder.begin();
 769     ListOrderIt order_end_it = listOrder.end();
 770     int total_issued = 0;
 771
 772     while (total_issued < (totalWidth - total_deferred_mem_issued) &&
 773            iewStage->canIssue() &&
 774            order_it != order_end_it) {
 775         OpClass op_class = (*order_it).queueType;
 776
 777         assert(!readyInsts[op_class].empty());
 778
 779         DynInstPtr issuing_inst = readyInsts[op_class].top();
 780
 781         issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
 782
 783         assert(issuing_inst->seqNum == (*order_it).oldestInst);
 784
 785         if (issuing_inst->isSquashed()) {
 786             readyInsts[op_class].pop();
 787
 788             if (!readyInsts[op_class].empty()) {
 789                 moveToYoungerInst(order_it);
 790             } else {
 791                 readyIt[op_class] = listOrder.end();
 792                 queueOnList[op_class] = false;
 793             }
 794
 795             listOrder.erase(order_it++);
 796
 797             ++iqSquashedInstsIssued;
 798
 799             continue;
 800         }
 801
 802         int idx = -2;
 803         int op_latency = 1;
 804         ThreadID tid = issuing_inst->threadNumber;
 805
 806         if (op_class != No_OpClass) {
 807             idx = fuPool->getUnit(op_class);
 808             issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
 809             if (idx > -1) {
 810                 op_latency = fuPool->getOpLatency(op_class);
 811             }
 812         }
 813
 814         // If we have an instruction that doesn't require a FU, or a
 815         // valid FU, then schedule for execution.
 816         if (idx == -2 || idx != -1) {
 817             if (op_latency == 1) {
 818                 i2e_info->size++;
 819                 instsToExecute.push_back(issuing_inst);
 820
 821                 // Add the FU onto the list of FU's to be freed next
 822                 // cycle if we used one.
 823                 if (idx >= 0)
 824                     fuPool->freeUnitNextCycle(idx);
 825             } else {
 826                 int issue_latency = fuPool->getIssueLatency(op_class);
 827                 // Generate completion event for the FU
 828                 FUCompletion *execution = new FUCompletion(issuing_inst,
 829                                                            idx, this);
 830
 831                 cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1));
 832
 833                 // @todo: Enforce that issue_latency == 1 or op_latency
 834                 if (issue_latency > 1) {
 835                     // If FU isn't pipelined, then it must be freed
 836                     // upon the execution completing.
 837                     execution->setFreeFU();
 838                 } else {
 839                     // Add the FU onto the list of FU's to be freed next cycle.
 840                     fuPool->freeUnitNextCycle(idx);
 841                 }
 842             }
 843
 844             DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
 845                     "[sn:%lli]\n",
 846                     tid, issuing_inst->pcState(),
 847                     issuing_inst->seqNum);
 848
 849             readyInsts[op_class].pop();
 850
 851             if (!readyInsts[op_class].empty()) {
 852                 moveToYoungerInst(order_it);
 853             } else {
 854                 readyIt[op_class] = listOrder.end();
 855                 queueOnList[op_class] = false;
 856             }
 857
 858             issuing_inst->setIssued();
 859             ++total_issued;
 860
 861 #if TRACING_ON
 862             issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
 863 #endif
 864
 865             if (!issuing_inst->isMemRef()) {
 866                 // Memory instructions can not be freed from the IQ until they
 867                 // complete.
 868                 ++freeEntries;
 869                 count[tid]--;
 870                 issuing_inst->clearInIQ();
 871             } else {
 872                 memDepUnit[tid].issue(issuing_inst);
 873             }
 874
 875             listOrder.erase(order_it++);
 876             statIssuedInstType[tid][op_class]++;
 877             iewStage->incrWb(issuing_inst->seqNum);
 878         } else {
 879             statFuBusy[op_class]++;
 880             fuBusy[tid]++;
 881             ++order_it;
 882         }
 883     }
 884
 885     numIssuedDist.sample(total_issued);
 886     iqInstsIssued+= total_issued;
 887
 888     // If we issued any instructions, tell the CPU we had activity.
 889     // @todo If the way deferred memory instructions are handeled due to
 890     // translation changes then the deferredMemInsts condition should be removed
 891     // from the code below.
 892     if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
 893         cpu->activityThisCycle();
 894     } else {
 895         DPRINTF(IQ, "Not able to schedule any instructions.\n");
 896     }
 897 }
 898
 899 template <class Impl>
 900 void
 901 InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
 902 {
 903     DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
 904             "to execute.\n", inst);
 905
 906     NonSpecMapIt inst_it = nonSpecInsts.find(inst);
 907
 908     assert(inst_it != nonSpecInsts.end());
 909
 910     ThreadID tid = (*inst_it).second->threadNumber;
 911
 912     (*inst_it).second->setAtCommit();
 913
 914     (*inst_it).second->setCanIssue();
 915
 916     if (!(*inst_it).second->isMemRef()) {
 917         addIfReady((*inst_it).second);
 918     } else {
 919         memDepUnit[tid].nonSpecInstReady((*inst_it).second);
 920     }
 921
 922     (*inst_it).second = NULL;
 923
 924     nonSpecInsts.erase(inst_it);
 925 }
 926
 927 template <class Impl>
 928 void
 929 InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
 930 {
 931     DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
 932             tid,inst);
 933
 934     ListIt iq_it = instList[tid].begin();
 935
 936     while (iq_it != instList[tid].end() &&
 937            (*iq_it)->seqNum <= inst) {
 938         ++iq_it;
 939         instList[tid].pop_front();
 940     }
 941
 942     assert(freeEntries == (numEntries - countInsts()));
 943 }
 944
 945 template <class Impl>
 946 int
 947 InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
 948 {
 949     int dependents = 0;
 950
 951     // The instruction queue here takes care of both floating and int ops
 952     if (completed_inst->isFloating()) {
 953         fpInstQueueWakeupQccesses++;
 954     } else {
 955         intInstQueueWakeupAccesses++;
 956     }
 957
 958     DPRINTF(IQ, "Waking dependents of completed instruction.\n");
 959
 960     assert(!completed_inst->isSquashed());
 961
 962     // Tell the memory dependence unit to wake any dependents on this
 963     // instruction if it is a memory instruction.  Also complete the memory
 964     // instruction at this point since we know it executed without issues.
 965     // @todo: Might want to rename "completeMemInst" to something that
 966     // indicates that it won't need to be replayed, and call this
 967     // earlier.  Might not be a big deal.
 968     if (completed_inst->isMemRef()) {
 969         memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
 970         completeMemInst(completed_inst);
 971     } else if (completed_inst->isMemBarrier() ||
 972                completed_inst->isWriteBarrier()) {
 973         memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
 974     }
 975
 976     for (int dest_reg_idx = 0;
 977          dest_reg_idx < completed_inst->numDestRegs();
 978          dest_reg_idx++)
 979     {
 980         PhysRegIndex dest_reg =
 981             completed_inst->renamedDestRegIdx(dest_reg_idx);
 982
 983         // Special case of uniq or control registers.  They are not
 984         // handled by the IQ and thus have no dependency graph entry.
 985         // @todo Figure out a cleaner way to handle this.
 986         if (dest_reg >= numPhysRegs) {
 987             DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
 988                     numPhysRegs);
 989             continue;
 990         }
 991
 992         DPRINTF(IQ, "Waking any dependents on register %i.\n",
 993                 (int) dest_reg);
 994
 995         //Go through the dependency chain, marking the registers as
 996         //ready within the waiting instructions.
 997         DynInstPtr dep_inst = dependGraph.pop(dest_reg);
 998
 999         while (dep_inst) {
1000             DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1001                     "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1002
1003             // Might want to give more information to the instruction
1004             // so that it knows which of its source registers is
1005             // ready.  However that would mean that the dependency
1006             // graph entries would need to hold the src_reg_idx.
1007             dep_inst->markSrcRegReady();
1008
1009             addIfReady(dep_inst);
1010
1011             dep_inst = dependGraph.pop(dest_reg);
1012
1013             ++dependents;
1014         }
1015
1016         // Reset the head node now that all of its dependents have
1017         // been woken up.
1018         assert(dependGraph.empty(dest_reg));
1019         dependGraph.clearInst(dest_reg);
1020
1021         // Mark the scoreboard as having that register ready.
1022         regScoreboard[dest_reg] = true;
1023     }
1024     return dependents;
1025 }
1026
1027 template <class Impl>
1028 void
1029 InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1030 {
1031     OpClass op_class = ready_inst->opClass();
1032
1033     readyInsts[op_class].push(ready_inst);
1034
1035     // Will need to reorder the list if either a queue is not on the list,
1036     // or it has an older instruction than last time.
1037     if (!queueOnList[op_class]) {
1038         addToOrderList(op_class);
1039     } else if (readyInsts[op_class].top()->seqNum  <
1040                (*readyIt[op_class]).oldestInst) {
1041         listOrder.erase(readyIt[op_class]);
1042         addToOrderList(op_class);
1043     }
1044
1045     DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1046             "the ready list, PC %s opclass:%i [sn:%lli].\n",
1047             ready_inst->pcState(), op_class, ready_inst->seqNum);
1048 }
1049
1050 template <class Impl>
1051 void
1052 InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1053 {
1054     DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1055
1056     // Reset DTB translation state
1057     resched_inst->translationStarted(false);
1058     resched_inst->translationCompleted(false);
1059
1060     resched_inst->clearCanIssue();
1061     memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1062 }
1063
1064 template <class Impl>
1065 void
1066 InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1067 {
1068     memDepUnit[replay_inst->threadNumber].replay(replay_inst);
1069 }
1070
1071 template <class Impl>
1072 void
1073 InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1074 {
1075     ThreadID tid = completed_inst->threadNumber;
1076
1077     DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1078             completed_inst->pcState(), completed_inst->seqNum);
1079
1080     ++freeEntries;
1081
1082     completed_inst->memOpDone(true);
1083
1084     memDepUnit[tid].completed(completed_inst);
1085     count[tid]--;
1086 }
1087
1088 template <class Impl>
1089 void
1090 InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1091 {
1092     deferredMemInsts.push_back(deferred_inst);
1093 }
1094
1095 template <class Impl>
1096 typename Impl::DynInstPtr
1097 InstructionQueue<Impl>::getDeferredMemInstToExecute()
1098 {
1099     for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1100          ++it) {
1101         if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1102             DynInstPtr ret = *it;
1103             deferredMemInsts.erase(it);
1104             return ret;
1105         }
1106     }
1107     return NULL;
1108 }
1109
1110 template <class Impl>
1111 void
1112 InstructionQueue<Impl>::violation(DynInstPtr &store,
1113                                   DynInstPtr &faulting_load)
1114 {
1115     intInstQueueWrites++;
1116     memDepUnit[store->threadNumber].violation(store, faulting_load);
1117 }
1118
1119 template <class Impl>
1120 void
1121 InstructionQueue<Impl>::squash(ThreadID tid)
1122 {
1123     DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1124             "the IQ.\n", tid);
1125
1126     // Read instruction sequence number of last instruction out of the
1127     // time buffer.
1128     squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1129
1130     // Call doSquash if there are insts in the IQ
1131     if (count[tid] > 0) {
1132         doSquash(tid);
1133     }
1134
1135     // Also tell the memory dependence unit to squash.
1136     memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1137 }
1138
1139 template <class Impl>
1140 void
1141 InstructionQueue<Impl>::doSquash(ThreadID tid)
1142 {
1143     // Start at the tail.
1144     ListIt squash_it = instList[tid].end();
1145     --squash_it;
1146
1147     DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1148             tid, squashedSeqNum[tid]);
1149
1150     // Squash any instructions younger than the squashed sequence number
1151     // given.
1152     while (squash_it != instList[tid].end() &&
1153            (*squash_it)->seqNum > squashedSeqNum[tid]) {
1154
1155         DynInstPtr squashed_inst = (*squash_it);
1156         squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1157
1158         // Only handle the instruction if it actually is in the IQ and
1159         // hasn't already been squashed in the IQ.
1160         if (squashed_inst->threadNumber != tid ||
1161             squashed_inst->isSquashedInIQ()) {
1162             --squash_it;
1163             continue;
1164         }
1165
1166         if (!squashed_inst->isIssued() ||
1167             (squashed_inst->isMemRef() &&
1168              !squashed_inst->memOpDone())) {
1169
1170             DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1171                     tid, squashed_inst->seqNum, squashed_inst->pcState());
1172
1173             // Remove the instruction from the dependency list.
1174             if (!squashed_inst->isNonSpeculative() &&
1175                 !squashed_inst->isStoreConditional() &&
1176                 !squashed_inst->isMemBarrier() &&
1177                 !squashed_inst->isWriteBarrier()) {
1178
1179                 for (int src_reg_idx = 0;
1180                      src_reg_idx < squashed_inst->numSrcRegs();
1181                      src_reg_idx++)
1182                 {
1183                     PhysRegIndex src_reg =
1184                         squashed_inst->renamedSrcRegIdx(src_reg_idx);
1185
1186                     // Only remove it from the dependency graph if it
1187                     // was placed there in the first place.
1188
1189                     // Instead of doing a linked list traversal, we
1190                     // can just remove these squashed instructions
1191                     // either at issue time, or when the register is
1192                     // overwritten.  The only downside to this is it
1193                     // leaves more room for error.
1194
1195                     if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1196                         src_reg < numPhysRegs) {
1197                         dependGraph.remove(src_reg, squashed_inst);
1198                     }
1199
1200
1201                     ++iqSquashedOperandsExamined;
1202                 }
1203             } else if (!squashed_inst->isStoreConditional() ||
1204                        !squashed_inst->isCompleted()) {
1205                 NonSpecMapIt ns_inst_it =
1206                     nonSpecInsts.find(squashed_inst->seqNum);
1207
1208                 if (ns_inst_it == nonSpecInsts.end()) {
1209                     assert(squashed_inst->getFault() != NoFault);
1210                 } else {
1211
1212                     (*ns_inst_it).second = NULL;
1213
1214                     nonSpecInsts.erase(ns_inst_it);
1215
1216                     ++iqSquashedNonSpecRemoved;
1217                 }
1218             }
1219
1220             // Might want to also clear out the head of the dependency graph.
1221
1222             // Mark it as squashed within the IQ.
1223             squashed_inst->setSquashedInIQ();
1224
1225             // @todo: Remove this hack where several statuses are set so the
1226             // inst will flow through the rest of the pipeline.
1227             squashed_inst->setIssued();
1228             squashed_inst->setCanCommit();
1229             squashed_inst->clearInIQ();
1230
1231             //Update Thread IQ Count
1232             count[squashed_inst->threadNumber]--;
1233
1234             ++freeEntries;
1235         }
1236
1237         instList[tid].erase(squash_it--);
1238         ++iqSquashedInstsExamined;
1239     }
1240 }
1241
1242 template <class Impl>
1243 bool
1244 InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1245 {
1246     // Loop through the instruction's source registers, adding
1247     // them to the dependency list if they are not ready.
1248     int8_t total_src_regs = new_inst->numSrcRegs();
1249     bool return_val = false;
1250
1251     for (int src_reg_idx = 0;
1252          src_reg_idx < total_src_regs;
1253          src_reg_idx++)
1254     {
1255         // Only add it to the dependency graph if it's not ready.
1256         if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1257             PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1258
1259             // Check the IQ's scoreboard to make sure the register
1260             // hasn't become ready while the instruction was in flight
1261             // between stages.  Only if it really isn't ready should
1262             // it be added to the dependency graph.
1263             if (src_reg >= numPhysRegs) {
1264                 continue;
1265             } else if (regScoreboard[src_reg] == false) {
1266                 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1267                         "is being added to the dependency chain.\n",
1268                         new_inst->pcState(), src_reg);
1269
1270                 dependGraph.insert(src_reg, new_inst);
1271
1272                 // Change the return value to indicate that something
1273                 // was added to the dependency graph.
1274                 return_val = true;
1275             } else {
1276                 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1277                         "became ready before it reached the IQ.\n",
1278                         new_inst->pcState(), src_reg);
1279                 // Mark a register ready within the instruction.
1280                 new_inst->markSrcRegReady(src_reg_idx);
1281             }
1282         }
1283     }
1284
1285     return return_val;
1286 }
1287
1288 template <class Impl>
1289 void
1290 InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1291 {
1292     // Nothing really needs to be marked when an instruction becomes
1293     // the producer of a register's value, but for convenience a ptr
1294     // to the producing instruction will be placed in the head node of
1295     // the dependency links.
1296     int8_t total_dest_regs = new_inst->numDestRegs();
1297
1298     for (int dest_reg_idx = 0;
1299          dest_reg_idx < total_dest_regs;
1300          dest_reg_idx++)
1301     {
1302         PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1303
1304         // Instructions that use the misc regs will have a reg number
1305         // higher than the normal physical registers.  In this case these
1306         // registers are not renamed, and there is no need to track
1307         // dependencies as these instructions must be executed at commit.
1308         if (dest_reg >= numPhysRegs) {
1309             continue;
1310         }
1311
1312         if (!dependGraph.empty(dest_reg)) {
1313             dependGraph.dump();
1314             panic("Dependency graph %i not empty!", dest_reg);
1315         }
1316
1317         dependGraph.setInst(dest_reg, new_inst);
1318
1319         // Mark the scoreboard to say it's not yet ready.
1320         regScoreboard[dest_reg] = false;
1321     }
1322 }
1323
1324 template <class Impl>
1325 void
1326 InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1327 {
1328     // If the instruction now has all of its source registers
1329     // available, then add it to the list of ready instructions.
1330     if (inst->readyToIssue()) {
1331
1332         //Add the instruction to the proper ready list.
1333         if (inst->isMemRef()) {
1334
1335             DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1336
1337             // Message to the mem dependence unit that this instruction has
1338             // its registers ready.
1339             memDepUnit[inst->threadNumber].regsReady(inst);
1340
1341             return;
1342         }
1343
1344         OpClass op_class = inst->opClass();
1345
1346         DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1347                 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1348                 inst->pcState(), op_class, inst->seqNum);
1349
1350         readyInsts[op_class].push(inst);
1351
1352         // Will need to reorder the list if either a queue is not on the list,
1353         // or it has an older instruction than last time.
1354         if (!queueOnList[op_class]) {
1355             addToOrderList(op_class);
1356         } else if (readyInsts[op_class].top()->seqNum  <
1357                    (*readyIt[op_class]).oldestInst) {
1358             listOrder.erase(readyIt[op_class]);
1359             addToOrderList(op_class);
1360         }
1361     }
1362 }
1363
1364 template <class Impl>
1365 int
1366 InstructionQueue<Impl>::countInsts()
1367 {
1368 #if 0
1369     //ksewell:This works but definitely could use a cleaner write
1370     //with a more intuitive way of counting. Right now it's
1371     //just brute force ....
1372     // Change the #if if you want to use this method.
1373     int total_insts = 0;
1374
1375     for (ThreadID tid = 0; tid < numThreads; ++tid) {
1376         ListIt count_it = instList[tid].begin();
1377
1378         while (count_it != instList[tid].end()) {
1379             if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1380                 if (!(*count_it)->isIssued()) {
1381                     ++total_insts;
1382                 } else if ((*count_it)->isMemRef() &&
1383                            !(*count_it)->memOpDone) {
1384                     // Loads that have not been marked as executed still count
1385                     // towards the total instructions.
1386                     ++total_insts;
1387                 }
1388             }
1389
1390             ++count_it;
1391         }
1392     }
1393
1394     return total_insts;
1395 #else
1396     return numEntries - freeEntries;
1397 #endif
1398 }
1399
1400 template <class Impl>
1401 void
1402 InstructionQueue<Impl>::dumpLists()
1403 {
1404     for (int i = 0; i < Num_OpClasses; ++i) {
1405         cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1406
1407         cprintf("\n");
1408     }
1409
1410     cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1411
1412     NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1413     NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1414
1415     cprintf("Non speculative list: ");
1416
1417     while (non_spec_it != non_spec_end_it) {
1418         cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1419                 (*non_spec_it).second->seqNum);
1420         ++non_spec_it;
1421     }
1422
1423     cprintf("\n");
1424
1425     ListOrderIt list_order_it = listOrder.begin();
1426     ListOrderIt list_order_end_it = listOrder.end();
1427     int i = 1;
1428
1429     cprintf("List order: ");
1430
1431     while (list_order_it != list_order_end_it) {
1432         cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1433                 (*list_order_it).oldestInst);
1434
1435         ++list_order_it;
1436         ++i;
1437     }
1438
1439     cprintf("\n");
1440 }
1441
1442
1443 template <class Impl>
1444 void
1445 InstructionQueue<Impl>::dumpInsts()
1446 {
1447     for (ThreadID tid = 0; tid < numThreads; ++tid) {
1448         int num = 0;
1449         int valid_num = 0;
1450         ListIt inst_list_it = instList[tid].begin();
1451
1452         while (inst_list_it != instList[tid].end()) {
1453             cprintf("Instruction:%i\n", num);
1454             if (!(*inst_list_it)->isSquashed()) {
1455                 if (!(*inst_list_it)->isIssued()) {
1456                     ++valid_num;
1457                     cprintf("Count:%i\n", valid_num);
1458                 } else if ((*inst_list_it)->isMemRef() &&
1459                            !(*inst_list_it)->memOpDone()) {
1460                     // Loads that have not been marked as executed
1461                     // still count towards the total instructions.
1462                     ++valid_num;
1463                     cprintf("Count:%i\n", valid_num);
1464                 }
1465             }
1466
1467             cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1468                     "Issued:%i\nSquashed:%i\n",
1469                     (*inst_list_it)->pcState(),
1470                     (*inst_list_it)->seqNum,
1471                     (*inst_list_it)->threadNumber,
1472                     (*inst_list_it)->isIssued(),
1473                     (*inst_list_it)->isSquashed());
1474
1475             if ((*inst_list_it)->isMemRef()) {
1476                 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1477             }
1478
1479             cprintf("\n");
1480
1481             inst_list_it++;
1482             ++num;
1483         }
1484     }
1485
1486     cprintf("Insts to Execute list:\n");
1487
1488     int num = 0;
1489     int valid_num = 0;
1490     ListIt inst_list_it = instsToExecute.begin();
1491
1492     while (inst_list_it != instsToExecute.end())
1493     {
1494         cprintf("Instruction:%i\n",
1495                 num);
1496         if (!(*inst_list_it)->isSquashed()) {
1497             if (!(*inst_list_it)->isIssued()) {
1498                 ++valid_num;
1499                 cprintf("Count:%i\n", valid_num);
1500             } else if ((*inst_list_it)->isMemRef() &&
1501                        !(*inst_list_it)->memOpDone()) {
1502                 // Loads that have not been marked as executed
1503                 // still count towards the total instructions.
1504                 ++valid_num;
1505                 cprintf("Count:%i\n", valid_num);
1506             }
1507         }
1508
1509         cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1510                 "Issued:%i\nSquashed:%i\n",
1511                 (*inst_list_it)->pcState(),
1512                 (*inst_list_it)->seqNum,
1513                 (*inst_list_it)->threadNumber,
1514                 (*inst_list_it)->isIssued(),
1515                 (*inst_list_it)->isSquashed());
1516
1517         if ((*inst_list_it)->isMemRef()) {
1518             cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1519         }
1520
1521         cprintf("\n");
1522
1523         inst_list_it++;
1524         ++num;
1525     }
1526 }