2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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35 #include "sim/root.hh"
37 #include "cpu/o3/fu_pool.hh"
38 #include "cpu/o3/inst_queue.hh"
43 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
45 InstructionQueue<Impl> *iq_ptr)
46 : Event(&mainEventQueue, Stat_Event_Pri),
47 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
49 this->setFlags(Event::AutoDelete);
54 InstructionQueue<Impl>::FUCompletion::process()
56 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
63 InstructionQueue<Impl>::FUCompletion::description()
65 return "Functional unit completion event";
69 InstructionQueue<Impl>::InstructionQueue(Params *params)
70 : fuPool(params->fuPool),
71 numEntries(params->numIQEntries),
72 totalWidth(params->issueWidth),
73 numPhysIntRegs(params->numPhysIntRegs),
74 numPhysFloatRegs(params->numPhysFloatRegs),
75 commitToIEWDelay(params->commitToIEWDelay)
81 numThreads = params->numberOfThreads;
83 // Set the number of physical registers as the number of int + float
84 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
86 DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
88 //Create an entry for each physical register within the
90 dependGraph.resize(numPhysRegs);
92 // Resize the register scoreboard.
93 regScoreboard.resize(numPhysRegs);
95 //Initialize Mem Dependence Units
96 for (int i = 0; i < numThreads; i++) {
97 memDepUnit[i].init(params,i);
98 memDepUnit[i].setIQ(this);
103 string policy = params->smtIQPolicy;
105 //Convert string to lowercase
106 std::transform(policy.begin(), policy.end(), policy.begin(),
107 (int(*)(int)) tolower);
109 //Figure out resource sharing policy
110 if (policy == "dynamic") {
113 //Set Max Entries to Total ROB Capacity
114 for (int i = 0; i < numThreads; i++) {
115 maxEntries[i] = numEntries;
118 } else if (policy == "partitioned") {
119 iqPolicy = Partitioned;
121 //@todo:make work if part_amt doesnt divide evenly.
122 int part_amt = numEntries / numThreads;
124 //Divide ROB up evenly
125 for (int i = 0; i < numThreads; i++) {
126 maxEntries[i] = part_amt;
129 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
130 "%i entries per thread.\n",part_amt);
132 } else if (policy == "threshold") {
133 iqPolicy = Threshold;
135 double threshold = (double)params->smtIQThreshold / 100;
137 int thresholdIQ = (int)((double)threshold * numEntries);
139 //Divide up by threshold amount
140 for (int i = 0; i < numThreads; i++) {
141 maxEntries[i] = thresholdIQ;
144 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
145 "%i entries per thread.\n",thresholdIQ);
147 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
148 "Partitioned, Threshold}");
152 template <class Impl>
153 InstructionQueue<Impl>::~InstructionQueue()
157 cprintf("Nodes traversed: %i, removed: %i\n",
158 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
162 template <class Impl>
164 InstructionQueue<Impl>::name() const
166 return cpu->name() + ".iq";
169 template <class Impl>
171 InstructionQueue<Impl>::regStats()
173 using namespace Stats;
175 .name(name() + ".iqInstsAdded")
176 .desc("Number of instructions added to the IQ (excludes non-spec)")
177 .prereq(iqInstsAdded);
180 .name(name() + ".iqNonSpecInstsAdded")
181 .desc("Number of non-speculative instructions added to the IQ")
182 .prereq(iqNonSpecInstsAdded);
185 .name(name() + ".iqInstsIssued")
186 .desc("Number of instructions issued")
187 .prereq(iqInstsIssued);
190 .name(name() + ".iqIntInstsIssued")
191 .desc("Number of integer instructions issued")
192 .prereq(iqIntInstsIssued);
195 .name(name() + ".iqFloatInstsIssued")
196 .desc("Number of float instructions issued")
197 .prereq(iqFloatInstsIssued);
200 .name(name() + ".iqBranchInstsIssued")
201 .desc("Number of branch instructions issued")
202 .prereq(iqBranchInstsIssued);
205 .name(name() + ".iqMemInstsIssued")
206 .desc("Number of memory instructions issued")
207 .prereq(iqMemInstsIssued);
210 .name(name() + ".iqMiscInstsIssued")
211 .desc("Number of miscellaneous instructions issued")
212 .prereq(iqMiscInstsIssued);
214 iqSquashedInstsIssued
215 .name(name() + ".iqSquashedInstsIssued")
216 .desc("Number of squashed instructions issued")
217 .prereq(iqSquashedInstsIssued);
219 iqSquashedInstsExamined
220 .name(name() + ".iqSquashedInstsExamined")
221 .desc("Number of squashed instructions iterated over during squash;"
222 " mainly for profiling")
223 .prereq(iqSquashedInstsExamined);
225 iqSquashedOperandsExamined
226 .name(name() + ".iqSquashedOperandsExamined")
227 .desc("Number of squashed operands that are examined and possibly "
228 "removed from graph")
229 .prereq(iqSquashedOperandsExamined);
231 iqSquashedNonSpecRemoved
232 .name(name() + ".iqSquashedNonSpecRemoved")
233 .desc("Number of squashed non-spec instructions that were removed")
234 .prereq(iqSquashedNonSpecRemoved);
237 .init(Num_OpClasses, 0, 99, 2)
238 .name(name() + ".IQ:residence:")
239 .desc("cycles from dispatch to issue")
240 .flags(total | pdf | cdf )
242 for (int i = 0; i < Num_OpClasses; ++i) {
243 queueResDist.subname(i, opClassStrings[i]);
246 .init(0,totalWidth,1)
247 .name(name() + ".ISSUE:issued_per_cycle")
248 .desc("Number of insts issued each cycle")
253 .init(Num_OpClasses+2)
254 .name(name() + ".ISSUE:unissued_cause")
255 .desc("Reason ready instruction not issued")
258 for (int i=0; i < (Num_OpClasses + 2); ++i) {
259 dist_unissued.subname(i, unissued_names[i]);
263 .init(numThreads,Num_OpClasses)
264 .name(name() + ".ISSUE:FU_type")
265 .desc("Type of FU issued")
266 .flags(total | pdf | dist)
268 statIssuedInstType.ysubnames(opClassStrings);
271 // How long did instructions for a particular FU type wait prior to issue
275 .init(Num_OpClasses,0,99,2)
276 .name(name() + ".ISSUE:")
277 .desc("cycles from operands ready to issue")
281 for (int i=0; i<Num_OpClasses; ++i) {
282 stringstream subname;
283 subname << opClassStrings[i] << "_delay";
284 issueDelayDist.subname(i, subname.str());
288 .name(name() + ".ISSUE:rate")
289 .desc("Inst issue rate")
292 issueRate = iqInstsIssued / cpu->numCycles;
296 .name(name() + ".ISSUE:fu_full")
297 .desc("attempts to use FU when none available")
300 for (int i=0; i < Num_OpClasses; ++i) {
301 statFuBusy.subname(i, opClassStrings[i]);
306 .name(name() + ".ISSUE:fu_busy_cnt")
307 .desc("FU busy when requested")
312 .name(name() + ".ISSUE:fu_busy_rate")
313 .desc("FU busy rate (busy events/executed inst)")
316 fuBusyRate = fuBusy / iqInstsIssued;
318 for ( int i=0; i < numThreads; i++) {
319 // Tell mem dependence unit to reg stats as well.
320 memDepUnit[i].regStats();
324 template <class Impl>
326 InstructionQueue<Impl>::resetState()
328 //Initialize thread IQ counts
329 for (int i = 0; i <numThreads; i++) {
334 // Initialize the number of free IQ entries.
335 freeEntries = numEntries;
337 // Note that in actuality, the registers corresponding to the logical
338 // registers start off as ready. However this doesn't matter for the
339 // IQ as the instruction should have been correctly told if those
340 // registers are ready in rename. Thus it can all be initialized as
342 for (int i = 0; i < numPhysRegs; ++i) {
343 regScoreboard[i] = false;
346 for (int i = 0; i < numThreads; ++i) {
347 squashedSeqNum[i] = 0;
350 for (int i = 0; i < Num_OpClasses; ++i) {
351 while (!readyInsts[i].empty())
353 queueOnList[i] = false;
354 readyIt[i] = listOrder.end();
356 nonSpecInsts.clear();
360 template <class Impl>
362 InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
364 DPRINTF(IQ, "Setting active threads list pointer.\n");
365 activeThreads = at_ptr;
368 template <class Impl>
370 InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
372 DPRINTF(IQ, "Set the issue to execute queue.\n");
373 issueToExecuteQueue = i2e_ptr;
376 template <class Impl>
378 InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
380 DPRINTF(IQ, "Set the time buffer.\n");
383 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
386 template <class Impl>
388 InstructionQueue<Impl>::switchOut()
393 for (int i = 0; i < numThreads; ++i) {
394 memDepUnit[i].switchOut();
398 template <class Impl>
400 InstructionQueue<Impl>::takeOverFrom()
405 template <class Impl>
407 InstructionQueue<Impl>::entryAmount(int num_threads)
409 if (iqPolicy == Partitioned) {
410 return numEntries / num_threads;
417 template <class Impl>
419 InstructionQueue<Impl>::resetEntries()
421 if (iqPolicy != Dynamic || numThreads > 1) {
422 int active_threads = (*activeThreads).size();
424 list<unsigned>::iterator threads = (*activeThreads).begin();
425 list<unsigned>::iterator list_end = (*activeThreads).end();
427 while (threads != list_end) {
428 if (iqPolicy == Partitioned) {
429 maxEntries[*threads++] = numEntries / active_threads;
430 } else if(iqPolicy == Threshold && active_threads == 1) {
431 maxEntries[*threads++] = numEntries;
437 template <class Impl>
439 InstructionQueue<Impl>::numFreeEntries()
444 template <class Impl>
446 InstructionQueue<Impl>::numFreeEntries(unsigned tid)
448 return maxEntries[tid] - count[tid];
451 // Might want to do something more complex if it knows how many instructions
452 // will be issued this cycle.
453 template <class Impl>
455 InstructionQueue<Impl>::isFull()
457 if (freeEntries == 0) {
464 template <class Impl>
466 InstructionQueue<Impl>::isFull(unsigned tid)
468 if (numFreeEntries(tid) == 0) {
475 template <class Impl>
477 InstructionQueue<Impl>::hasReadyInsts()
479 if (!listOrder.empty()) {
483 for (int i = 0; i < Num_OpClasses; ++i) {
484 if (!readyInsts[i].empty()) {
492 template <class Impl>
494 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
496 // Make sure the instruction is valid
499 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
500 new_inst->seqNum, new_inst->readPC());
502 assert(freeEntries != 0);
504 instList[new_inst->threadNumber].push_back(new_inst);
510 // Look through its source registers (physical regs), and mark any
512 addToDependents(new_inst);
514 // Have this instruction set itself as the producer of its destination
516 addToProducers(new_inst);
518 if (new_inst->isMemRef()) {
519 memDepUnit[new_inst->threadNumber].insert(new_inst);
521 addIfReady(new_inst);
526 count[new_inst->threadNumber]++;
528 assert(freeEntries == (numEntries - countInsts()));
531 template <class Impl>
533 InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
535 // @todo: Clean up this code; can do it by setting inst as unable
536 // to issue, then calling normal insert on the inst.
540 nonSpecInsts[new_inst->seqNum] = new_inst;
542 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
544 new_inst->seqNum, new_inst->readPC());
546 assert(freeEntries != 0);
548 instList[new_inst->threadNumber].push_back(new_inst);
554 // Have this instruction set itself as the producer of its destination
556 addToProducers(new_inst);
558 // If it's a memory instruction, add it to the memory dependency
560 if (new_inst->isMemRef()) {
561 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
564 ++iqNonSpecInstsAdded;
566 count[new_inst->threadNumber]++;
568 assert(freeEntries == (numEntries - countInsts()));
571 template <class Impl>
573 InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
575 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
577 insertNonSpec(barr_inst);
580 template <class Impl>
581 typename Impl::DynInstPtr
582 InstructionQueue<Impl>::getInstToExecute()
584 assert(!instsToExecute.empty());
585 DynInstPtr inst = instsToExecute.front();
586 instsToExecute.pop_front();
590 template <class Impl>
592 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
594 assert(!readyInsts[op_class].empty());
596 ListOrderEntry queue_entry;
598 queue_entry.queueType = op_class;
600 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
602 ListOrderIt list_it = listOrder.begin();
603 ListOrderIt list_end_it = listOrder.end();
605 while (list_it != list_end_it) {
606 if ((*list_it).oldestInst > queue_entry.oldestInst) {
613 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
614 queueOnList[op_class] = true;
617 template <class Impl>
619 InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
621 // Get iterator of next item on the list
622 // Delete the original iterator
623 // Determine if the next item is either the end of the list or younger
624 // than the new instruction. If so, then add in a new iterator right here.
625 // If not, then move along.
626 ListOrderEntry queue_entry;
627 OpClass op_class = (*list_order_it).queueType;
628 ListOrderIt next_it = list_order_it;
632 queue_entry.queueType = op_class;
633 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
635 while (next_it != listOrder.end() &&
636 (*next_it).oldestInst < queue_entry.oldestInst) {
640 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
643 template <class Impl>
645 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
647 // The CPU could have been sleeping until this op completed (*extremely*
648 // long latency op). Wake it if it was. This may be overkill.
649 if (isSwitchedOut()) {
656 fuPool->freeUnitNextCycle(fu_idx);
658 // @todo: Ensure that these FU Completions happen at the beginning
659 // of a cycle, otherwise they could add too many instructions to
661 issueToExecuteQueue->access(0)->size++;
662 instsToExecute.push_back(inst);
665 // @todo: Figure out a better way to remove the squashed items from the
666 // lists. Checking the top item of each list to see if it's squashed
667 // wastes time and forces jumps.
668 template <class Impl>
670 InstructionQueue<Impl>::scheduleReadyInsts()
672 DPRINTF(IQ, "Attempting to schedule ready instructions from "
675 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
677 // Have iterator to head of the list
678 // While I haven't exceeded bandwidth or reached the end of the list,
679 // Try to get a FU that can do what this op needs.
680 // If successful, change the oldestInst to the new top of the list, put
681 // the queue in the proper place in the list.
682 // Increment the iterator.
683 // This will avoid trying to schedule a certain op class if there are no
684 // FUs that handle it.
685 ListOrderIt order_it = listOrder.begin();
686 ListOrderIt order_end_it = listOrder.end();
687 int total_issued = 0;
689 while (total_issued < totalWidth &&
690 iewStage->canIssue() &&
691 order_it != order_end_it) {
692 OpClass op_class = (*order_it).queueType;
694 assert(!readyInsts[op_class].empty());
696 DynInstPtr issuing_inst = readyInsts[op_class].top();
698 assert(issuing_inst->seqNum == (*order_it).oldestInst);
700 if (issuing_inst->isSquashed()) {
701 readyInsts[op_class].pop();
703 if (!readyInsts[op_class].empty()) {
704 moveToYoungerInst(order_it);
706 readyIt[op_class] = listOrder.end();
707 queueOnList[op_class] = false;
710 listOrder.erase(order_it++);
712 ++iqSquashedInstsIssued;
719 int tid = issuing_inst->threadNumber;
721 if (op_class != No_OpClass) {
722 idx = fuPool->getUnit(op_class);
725 op_latency = fuPool->getOpLatency(op_class);
729 // If we have an instruction that doesn't require a FU, or a
730 // valid FU, then schedule for execution.
731 if (idx == -2 || idx != -1) {
732 if (op_latency == 1) {
734 instsToExecute.push_back(issuing_inst);
736 // Add the FU onto the list of FU's to be freed next
737 // cycle if we used one.
739 fuPool->freeUnitNextCycle(idx);
741 int issue_latency = fuPool->getIssueLatency(op_class);
742 // Generate completion event for the FU
743 FUCompletion *execution = new FUCompletion(issuing_inst,
746 execution->schedule(curTick + cpu->cycles(issue_latency - 1));
748 // @todo: Enforce that issue_latency == 1 or op_latency
749 if (issue_latency > 1) {
750 // If FU isn't pipelined, then it must be freed
751 // upon the execution completing.
752 execution->setFreeFU();
754 // Add the FU onto the list of FU's to be freed next cycle.
755 fuPool->freeUnitNextCycle(idx);
759 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
761 tid, issuing_inst->readPC(),
762 issuing_inst->seqNum);
764 readyInsts[op_class].pop();
766 if (!readyInsts[op_class].empty()) {
767 moveToYoungerInst(order_it);
769 readyIt[op_class] = listOrder.end();
770 queueOnList[op_class] = false;
773 issuing_inst->setIssued();
776 if (!issuing_inst->isMemRef()) {
777 // Memory instructions can not be freed from the IQ until they
781 issuing_inst->clearInIQ();
783 memDepUnit[tid].issue(issuing_inst);
786 listOrder.erase(order_it++);
787 statIssuedInstType[tid][op_class]++;
788 iewStage->incrWb(issuing_inst->seqNum);
790 statFuBusy[op_class]++;
796 numIssuedDist.sample(total_issued);
797 iqInstsIssued+= total_issued;
799 // If we issued any instructions, tell the CPU we had activity.
801 cpu->activityThisCycle();
803 DPRINTF(IQ, "Not able to schedule any instructions.\n");
807 template <class Impl>
809 InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
811 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
812 "to execute.\n", inst);
814 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
816 assert(inst_it != nonSpecInsts.end());
818 unsigned tid = (*inst_it).second->threadNumber;
820 (*inst_it).second->setCanIssue();
822 if (!(*inst_it).second->isMemRef()) {
823 addIfReady((*inst_it).second);
825 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
828 (*inst_it).second = NULL;
830 nonSpecInsts.erase(inst_it);
833 template <class Impl>
835 InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
837 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
840 ListIt iq_it = instList[tid].begin();
842 while (iq_it != instList[tid].end() &&
843 (*iq_it)->seqNum <= inst) {
845 instList[tid].pop_front();
848 assert(freeEntries == (numEntries - countInsts()));
851 template <class Impl>
853 InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
857 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
859 assert(!completed_inst->isSquashed());
861 // Tell the memory dependence unit to wake any dependents on this
862 // instruction if it is a memory instruction. Also complete the memory
863 // instruction at this point since we know it executed without issues.
864 // @todo: Might want to rename "completeMemInst" to something that
865 // indicates that it won't need to be replayed, and call this
866 // earlier. Might not be a big deal.
867 if (completed_inst->isMemRef()) {
868 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
869 completeMemInst(completed_inst);
870 } else if (completed_inst->isMemBarrier() ||
871 completed_inst->isWriteBarrier()) {
872 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
875 for (int dest_reg_idx = 0;
876 dest_reg_idx < completed_inst->numDestRegs();
879 PhysRegIndex dest_reg =
880 completed_inst->renamedDestRegIdx(dest_reg_idx);
882 // Special case of uniq or control registers. They are not
883 // handled by the IQ and thus have no dependency graph entry.
884 // @todo Figure out a cleaner way to handle this.
885 if (dest_reg >= numPhysRegs) {
889 DPRINTF(IQ, "Waking any dependents on register %i.\n",
892 //Go through the dependency chain, marking the registers as
893 //ready within the waiting instructions.
894 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
897 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
900 // Might want to give more information to the instruction
901 // so that it knows which of its source registers is
902 // ready. However that would mean that the dependency
903 // graph entries would need to hold the src_reg_idx.
904 dep_inst->markSrcRegReady();
906 addIfReady(dep_inst);
908 dep_inst = dependGraph.pop(dest_reg);
913 // Reset the head node now that all of its dependents have
915 assert(dependGraph.empty(dest_reg));
916 dependGraph.clearInst(dest_reg);
918 // Mark the scoreboard as having that register ready.
919 regScoreboard[dest_reg] = true;
924 template <class Impl>
926 InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
928 OpClass op_class = ready_inst->opClass();
930 readyInsts[op_class].push(ready_inst);
932 // Will need to reorder the list if either a queue is not on the list,
933 // or it has an older instruction than last time.
934 if (!queueOnList[op_class]) {
935 addToOrderList(op_class);
936 } else if (readyInsts[op_class].top()->seqNum <
937 (*readyIt[op_class]).oldestInst) {
938 listOrder.erase(readyIt[op_class]);
939 addToOrderList(op_class);
942 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
943 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
944 ready_inst->readPC(), op_class, ready_inst->seqNum);
947 template <class Impl>
949 InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
951 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
954 template <class Impl>
956 InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
958 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
961 template <class Impl>
963 InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
965 int tid = completed_inst->threadNumber;
967 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
968 completed_inst->readPC(), completed_inst->seqNum);
972 completed_inst->memOpDone = true;
974 memDepUnit[tid].completed(completed_inst);
979 template <class Impl>
981 InstructionQueue<Impl>::violation(DynInstPtr &store,
982 DynInstPtr &faulting_load)
984 memDepUnit[store->threadNumber].violation(store, faulting_load);
987 template <class Impl>
989 InstructionQueue<Impl>::squash(unsigned tid)
991 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
994 // Read instruction sequence number of last instruction out of the
996 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
998 // Call doSquash if there are insts in the IQ
999 if (count[tid] > 0) {
1003 // Also tell the memory dependence unit to squash.
1004 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1007 template <class Impl>
1009 InstructionQueue<Impl>::doSquash(unsigned tid)
1011 // Start at the tail.
1012 ListIt squash_it = instList[tid].end();
1015 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1016 tid, squashedSeqNum[tid]);
1018 // Squash any instructions younger than the squashed sequence number
1020 while (squash_it != instList[tid].end() &&
1021 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1023 DynInstPtr squashed_inst = (*squash_it);
1025 // Only handle the instruction if it actually is in the IQ and
1026 // hasn't already been squashed in the IQ.
1027 if (squashed_inst->threadNumber != tid ||
1028 squashed_inst->isSquashedInIQ()) {
1033 if (!squashed_inst->isIssued() ||
1034 (squashed_inst->isMemRef() &&
1035 !squashed_inst->memOpDone)) {
1037 // Remove the instruction from the dependency list.
1038 if (!squashed_inst->isNonSpeculative() &&
1039 !squashed_inst->isStoreConditional() &&
1040 !squashed_inst->isMemBarrier() &&
1041 !squashed_inst->isWriteBarrier()) {
1043 for (int src_reg_idx = 0;
1044 src_reg_idx < squashed_inst->numSrcRegs();
1047 PhysRegIndex src_reg =
1048 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1050 // Only remove it from the dependency graph if it
1051 // was placed there in the first place.
1053 // Instead of doing a linked list traversal, we
1054 // can just remove these squashed instructions
1055 // either at issue time, or when the register is
1056 // overwritten. The only downside to this is it
1057 // leaves more room for error.
1059 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1060 src_reg < numPhysRegs) {
1061 dependGraph.remove(src_reg, squashed_inst);
1065 ++iqSquashedOperandsExamined;
1068 NonSpecMapIt ns_inst_it =
1069 nonSpecInsts.find(squashed_inst->seqNum);
1070 assert(ns_inst_it != nonSpecInsts.end());
1072 (*ns_inst_it).second = NULL;
1074 nonSpecInsts.erase(ns_inst_it);
1076 ++iqSquashedNonSpecRemoved;
1079 // Might want to also clear out the head of the dependency graph.
1081 // Mark it as squashed within the IQ.
1082 squashed_inst->setSquashedInIQ();
1084 // @todo: Remove this hack where several statuses are set so the
1085 // inst will flow through the rest of the pipeline.
1086 squashed_inst->setIssued();
1087 squashed_inst->setCanCommit();
1088 squashed_inst->clearInIQ();
1090 //Update Thread IQ Count
1091 count[squashed_inst->threadNumber]--;
1095 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
1097 tid, squashed_inst->seqNum, squashed_inst->readPC());
1100 instList[tid].erase(squash_it--);
1101 ++iqSquashedInstsExamined;
1105 template <class Impl>
1107 InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1109 // Loop through the instruction's source registers, adding
1110 // them to the dependency list if they are not ready.
1111 int8_t total_src_regs = new_inst->numSrcRegs();
1112 bool return_val = false;
1114 for (int src_reg_idx = 0;
1115 src_reg_idx < total_src_regs;
1118 // Only add it to the dependency graph if it's not ready.
1119 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1120 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1122 // Check the IQ's scoreboard to make sure the register
1123 // hasn't become ready while the instruction was in flight
1124 // between stages. Only if it really isn't ready should
1125 // it be added to the dependency graph.
1126 if (src_reg >= numPhysRegs) {
1128 } else if (regScoreboard[src_reg] == false) {
1129 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1130 "is being added to the dependency chain.\n",
1131 new_inst->readPC(), src_reg);
1133 dependGraph.insert(src_reg, new_inst);
1135 // Change the return value to indicate that something
1136 // was added to the dependency graph.
1139 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1140 "became ready before it reached the IQ.\n",
1141 new_inst->readPC(), src_reg);
1142 // Mark a register ready within the instruction.
1143 new_inst->markSrcRegReady(src_reg_idx);
1151 template <class Impl>
1153 InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1155 // Nothing really needs to be marked when an instruction becomes
1156 // the producer of a register's value, but for convenience a ptr
1157 // to the producing instruction will be placed in the head node of
1158 // the dependency links.
1159 int8_t total_dest_regs = new_inst->numDestRegs();
1161 for (int dest_reg_idx = 0;
1162 dest_reg_idx < total_dest_regs;
1165 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1167 // Instructions that use the misc regs will have a reg number
1168 // higher than the normal physical registers. In this case these
1169 // registers are not renamed, and there is no need to track
1170 // dependencies as these instructions must be executed at commit.
1171 if (dest_reg >= numPhysRegs) {
1175 if (!dependGraph.empty(dest_reg)) {
1177 panic("Dependency graph %i not empty!", dest_reg);
1180 dependGraph.setInst(dest_reg, new_inst);
1182 // Mark the scoreboard to say it's not yet ready.
1183 regScoreboard[dest_reg] = false;
1187 template <class Impl>
1189 InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1191 // If the instruction now has all of its source registers
1192 // available, then add it to the list of ready instructions.
1193 if (inst->readyToIssue()) {
1195 //Add the instruction to the proper ready list.
1196 if (inst->isMemRef()) {
1198 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1200 // Message to the mem dependence unit that this instruction has
1201 // its registers ready.
1202 memDepUnit[inst->threadNumber].regsReady(inst);
1207 OpClass op_class = inst->opClass();
1209 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1210 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1211 inst->readPC(), op_class, inst->seqNum);
1213 readyInsts[op_class].push(inst);
1215 // Will need to reorder the list if either a queue is not on the list,
1216 // or it has an older instruction than last time.
1217 if (!queueOnList[op_class]) {
1218 addToOrderList(op_class);
1219 } else if (readyInsts[op_class].top()->seqNum <
1220 (*readyIt[op_class]).oldestInst) {
1221 listOrder.erase(readyIt[op_class]);
1222 addToOrderList(op_class);
1227 template <class Impl>
1229 InstructionQueue<Impl>::countInsts()
1232 //ksewell:This works but definitely could use a cleaner write
1233 //with a more intuitive way of counting. Right now it's
1234 //just brute force ....
1235 // Change the #if if you want to use this method.
1236 int total_insts = 0;
1238 for (int i = 0; i < numThreads; ++i) {
1239 ListIt count_it = instList[i].begin();
1241 while (count_it != instList[i].end()) {
1242 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1243 if (!(*count_it)->isIssued()) {
1245 } else if ((*count_it)->isMemRef() &&
1246 !(*count_it)->memOpDone) {
1247 // Loads that have not been marked as executed still count
1248 // towards the total instructions.
1259 return numEntries - freeEntries;
1263 template <class Impl>
1265 InstructionQueue<Impl>::dumpLists()
1267 for (int i = 0; i < Num_OpClasses; ++i) {
1268 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1273 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1275 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1276 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1278 cprintf("Non speculative list: ");
1280 while (non_spec_it != non_spec_end_it) {
1281 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1282 (*non_spec_it).second->seqNum);
1288 ListOrderIt list_order_it = listOrder.begin();
1289 ListOrderIt list_order_end_it = listOrder.end();
1292 cprintf("List order: ");
1294 while (list_order_it != list_order_end_it) {
1295 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1296 (*list_order_it).oldestInst);
1306 template <class Impl>
1308 InstructionQueue<Impl>::dumpInsts()
1310 for (int i = 0; i < numThreads; ++i) {
1313 ListIt inst_list_it = instList[i].begin();
1315 while (inst_list_it != instList[i].end())
1317 cprintf("Instruction:%i\n",
1319 if (!(*inst_list_it)->isSquashed()) {
1320 if (!(*inst_list_it)->isIssued()) {
1322 cprintf("Count:%i\n", valid_num);
1323 } else if ((*inst_list_it)->isMemRef() &&
1324 !(*inst_list_it)->memOpDone) {
1325 // Loads that have not been marked as executed
1326 // still count towards the total instructions.
1328 cprintf("Count:%i\n", valid_num);
1332 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1333 "Issued:%i\nSquashed:%i\n",
1334 (*inst_list_it)->readPC(),
1335 (*inst_list_it)->seqNum,
1336 (*inst_list_it)->threadNumber,
1337 (*inst_list_it)->isIssued(),
1338 (*inst_list_it)->isSquashed());
1340 if ((*inst_list_it)->isMemRef()) {
1341 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1351 cprintf("Insts to Execute list:\n");
1355 ListIt inst_list_it = instsToExecute.begin();
1357 while (inst_list_it != instsToExecute.end())
1359 cprintf("Instruction:%i\n",
1361 if (!(*inst_list_it)->isSquashed()) {
1362 if (!(*inst_list_it)->isIssued()) {
1364 cprintf("Count:%i\n", valid_num);
1365 } else if ((*inst_list_it)->isMemRef() &&
1366 !(*inst_list_it)->memOpDone) {
1367 // Loads that have not been marked as executed
1368 // still count towards the total instructions.
1370 cprintf("Count:%i\n", valid_num);
1374 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1375 "Issued:%i\nSquashed:%i\n",
1376 (*inst_list_it)->readPC(),
1377 (*inst_list_it)->seqNum,
1378 (*inst_list_it)->threadNumber,
1379 (*inst_list_it)->isIssued(),
1380 (*inst_list_it)->isSquashed());
1382 if ((*inst_list_it)->isMemRef()) {
1383 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);