2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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35 #include "sim/root.hh"
37 #include "cpu/o3/fu_pool.hh"
38 #include "cpu/o3/inst_queue.hh"
41 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
43 InstructionQueue<Impl> *iq_ptr)
44 : Event(&mainEventQueue, Stat_Event_Pri),
45 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
47 this->setFlags(Event::AutoDelete);
52 InstructionQueue<Impl>::FUCompletion::process()
54 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
61 InstructionQueue<Impl>::FUCompletion::description()
63 return "Functional unit completion event";
67 InstructionQueue<Impl>::InstructionQueue(Params *params)
68 : fuPool(params->fuPool),
69 numEntries(params->numIQEntries),
70 totalWidth(params->issueWidth),
71 numPhysIntRegs(params->numPhysIntRegs),
72 numPhysFloatRegs(params->numPhysFloatRegs),
73 commitToIEWDelay(params->commitToIEWDelay)
79 numThreads = params->numberOfThreads;
81 // Set the number of physical registers as the number of int + float
82 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
84 DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
86 //Create an entry for each physical register within the
88 dependGraph.resize(numPhysRegs);
90 // Resize the register scoreboard.
91 regScoreboard.resize(numPhysRegs);
93 //Initialize Mem Dependence Units
94 for (int i = 0; i < numThreads; i++) {
95 memDepUnit[i].init(params,i);
96 memDepUnit[i].setIQ(this);
101 std::string policy = params->smtIQPolicy;
103 //Convert string to lowercase
104 std::transform(policy.begin(), policy.end(), policy.begin(),
105 (int(*)(int)) tolower);
107 //Figure out resource sharing policy
108 if (policy == "dynamic") {
111 //Set Max Entries to Total ROB Capacity
112 for (int i = 0; i < numThreads; i++) {
113 maxEntries[i] = numEntries;
116 } else if (policy == "partitioned") {
117 iqPolicy = Partitioned;
119 //@todo:make work if part_amt doesnt divide evenly.
120 int part_amt = numEntries / numThreads;
122 //Divide ROB up evenly
123 for (int i = 0; i < numThreads; i++) {
124 maxEntries[i] = part_amt;
127 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
128 "%i entries per thread.\n",part_amt);
130 } else if (policy == "threshold") {
131 iqPolicy = Threshold;
133 double threshold = (double)params->smtIQThreshold / 100;
135 int thresholdIQ = (int)((double)threshold * numEntries);
137 //Divide up by threshold amount
138 for (int i = 0; i < numThreads; i++) {
139 maxEntries[i] = thresholdIQ;
142 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
143 "%i entries per thread.\n",thresholdIQ);
145 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
146 "Partitioned, Threshold}");
150 template <class Impl>
151 InstructionQueue<Impl>::~InstructionQueue()
155 cprintf("Nodes traversed: %i, removed: %i\n",
156 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
160 template <class Impl>
162 InstructionQueue<Impl>::name() const
164 return cpu->name() + ".iq";
167 template <class Impl>
169 InstructionQueue<Impl>::regStats()
171 using namespace Stats;
173 .name(name() + ".iqInstsAdded")
174 .desc("Number of instructions added to the IQ (excludes non-spec)")
175 .prereq(iqInstsAdded);
178 .name(name() + ".iqNonSpecInstsAdded")
179 .desc("Number of non-speculative instructions added to the IQ")
180 .prereq(iqNonSpecInstsAdded);
183 .name(name() + ".iqInstsIssued")
184 .desc("Number of instructions issued")
185 .prereq(iqInstsIssued);
188 .name(name() + ".iqIntInstsIssued")
189 .desc("Number of integer instructions issued")
190 .prereq(iqIntInstsIssued);
193 .name(name() + ".iqFloatInstsIssued")
194 .desc("Number of float instructions issued")
195 .prereq(iqFloatInstsIssued);
198 .name(name() + ".iqBranchInstsIssued")
199 .desc("Number of branch instructions issued")
200 .prereq(iqBranchInstsIssued);
203 .name(name() + ".iqMemInstsIssued")
204 .desc("Number of memory instructions issued")
205 .prereq(iqMemInstsIssued);
208 .name(name() + ".iqMiscInstsIssued")
209 .desc("Number of miscellaneous instructions issued")
210 .prereq(iqMiscInstsIssued);
212 iqSquashedInstsIssued
213 .name(name() + ".iqSquashedInstsIssued")
214 .desc("Number of squashed instructions issued")
215 .prereq(iqSquashedInstsIssued);
217 iqSquashedInstsExamined
218 .name(name() + ".iqSquashedInstsExamined")
219 .desc("Number of squashed instructions iterated over during squash;"
220 " mainly for profiling")
221 .prereq(iqSquashedInstsExamined);
223 iqSquashedOperandsExamined
224 .name(name() + ".iqSquashedOperandsExamined")
225 .desc("Number of squashed operands that are examined and possibly "
226 "removed from graph")
227 .prereq(iqSquashedOperandsExamined);
229 iqSquashedNonSpecRemoved
230 .name(name() + ".iqSquashedNonSpecRemoved")
231 .desc("Number of squashed non-spec instructions that were removed")
232 .prereq(iqSquashedNonSpecRemoved);
235 .init(Num_OpClasses, 0, 99, 2)
236 .name(name() + ".IQ:residence:")
237 .desc("cycles from dispatch to issue")
238 .flags(total | pdf | cdf )
240 for (int i = 0; i < Num_OpClasses; ++i) {
241 queueResDist.subname(i, opClassStrings[i]);
244 .init(0,totalWidth,1)
245 .name(name() + ".ISSUE:issued_per_cycle")
246 .desc("Number of insts issued each cycle")
251 .init(Num_OpClasses+2)
252 .name(name() + ".ISSUE:unissued_cause")
253 .desc("Reason ready instruction not issued")
256 for (int i=0; i < (Num_OpClasses + 2); ++i) {
257 dist_unissued.subname(i, unissued_names[i]);
261 .init(numThreads,Num_OpClasses)
262 .name(name() + ".ISSUE:FU_type")
263 .desc("Type of FU issued")
264 .flags(total | pdf | dist)
266 statIssuedInstType.ysubnames(opClassStrings);
269 // How long did instructions for a particular FU type wait prior to issue
273 .init(Num_OpClasses,0,99,2)
274 .name(name() + ".ISSUE:")
275 .desc("cycles from operands ready to issue")
279 for (int i=0; i<Num_OpClasses; ++i) {
280 std::stringstream subname;
281 subname << opClassStrings[i] << "_delay";
282 issueDelayDist.subname(i, subname.str());
286 .name(name() + ".ISSUE:rate")
287 .desc("Inst issue rate")
290 issueRate = iqInstsIssued / cpu->numCycles;
294 .name(name() + ".ISSUE:fu_full")
295 .desc("attempts to use FU when none available")
298 for (int i=0; i < Num_OpClasses; ++i) {
299 statFuBusy.subname(i, opClassStrings[i]);
304 .name(name() + ".ISSUE:fu_busy_cnt")
305 .desc("FU busy when requested")
310 .name(name() + ".ISSUE:fu_busy_rate")
311 .desc("FU busy rate (busy events/executed inst)")
314 fuBusyRate = fuBusy / iqInstsIssued;
316 for ( int i=0; i < numThreads; i++) {
317 // Tell mem dependence unit to reg stats as well.
318 memDepUnit[i].regStats();
322 template <class Impl>
324 InstructionQueue<Impl>::resetState()
326 //Initialize thread IQ counts
327 for (int i = 0; i <numThreads; i++) {
332 // Initialize the number of free IQ entries.
333 freeEntries = numEntries;
335 // Note that in actuality, the registers corresponding to the logical
336 // registers start off as ready. However this doesn't matter for the
337 // IQ as the instruction should have been correctly told if those
338 // registers are ready in rename. Thus it can all be initialized as
340 for (int i = 0; i < numPhysRegs; ++i) {
341 regScoreboard[i] = false;
344 for (int i = 0; i < numThreads; ++i) {
345 squashedSeqNum[i] = 0;
348 for (int i = 0; i < Num_OpClasses; ++i) {
349 while (!readyInsts[i].empty())
351 queueOnList[i] = false;
352 readyIt[i] = listOrder.end();
354 nonSpecInsts.clear();
358 template <class Impl>
360 InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
362 DPRINTF(IQ, "Setting active threads list pointer.\n");
363 activeThreads = at_ptr;
366 template <class Impl>
368 InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
370 DPRINTF(IQ, "Set the issue to execute queue.\n");
371 issueToExecuteQueue = i2e_ptr;
374 template <class Impl>
376 InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
378 DPRINTF(IQ, "Set the time buffer.\n");
381 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
384 template <class Impl>
386 InstructionQueue<Impl>::switchOut()
391 for (int i = 0; i < numThreads; ++i) {
392 memDepUnit[i].switchOut();
396 template <class Impl>
398 InstructionQueue<Impl>::takeOverFrom()
403 template <class Impl>
405 InstructionQueue<Impl>::entryAmount(int num_threads)
407 if (iqPolicy == Partitioned) {
408 return numEntries / num_threads;
415 template <class Impl>
417 InstructionQueue<Impl>::resetEntries()
419 if (iqPolicy != Dynamic || numThreads > 1) {
420 int active_threads = (*activeThreads).size();
422 std::list<unsigned>::iterator threads = (*activeThreads).begin();
423 std::list<unsigned>::iterator list_end = (*activeThreads).end();
425 while (threads != list_end) {
426 if (iqPolicy == Partitioned) {
427 maxEntries[*threads++] = numEntries / active_threads;
428 } else if(iqPolicy == Threshold && active_threads == 1) {
429 maxEntries[*threads++] = numEntries;
435 template <class Impl>
437 InstructionQueue<Impl>::numFreeEntries()
442 template <class Impl>
444 InstructionQueue<Impl>::numFreeEntries(unsigned tid)
446 return maxEntries[tid] - count[tid];
449 // Might want to do something more complex if it knows how many instructions
450 // will be issued this cycle.
451 template <class Impl>
453 InstructionQueue<Impl>::isFull()
455 if (freeEntries == 0) {
462 template <class Impl>
464 InstructionQueue<Impl>::isFull(unsigned tid)
466 if (numFreeEntries(tid) == 0) {
473 template <class Impl>
475 InstructionQueue<Impl>::hasReadyInsts()
477 if (!listOrder.empty()) {
481 for (int i = 0; i < Num_OpClasses; ++i) {
482 if (!readyInsts[i].empty()) {
490 template <class Impl>
492 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
494 // Make sure the instruction is valid
497 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
498 new_inst->seqNum, new_inst->readPC());
500 assert(freeEntries != 0);
502 instList[new_inst->threadNumber].push_back(new_inst);
508 // Look through its source registers (physical regs), and mark any
510 addToDependents(new_inst);
512 // Have this instruction set itself as the producer of its destination
514 addToProducers(new_inst);
516 if (new_inst->isMemRef()) {
517 memDepUnit[new_inst->threadNumber].insert(new_inst);
519 addIfReady(new_inst);
524 count[new_inst->threadNumber]++;
526 assert(freeEntries == (numEntries - countInsts()));
529 template <class Impl>
531 InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
533 // @todo: Clean up this code; can do it by setting inst as unable
534 // to issue, then calling normal insert on the inst.
538 nonSpecInsts[new_inst->seqNum] = new_inst;
540 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
542 new_inst->seqNum, new_inst->readPC());
544 assert(freeEntries != 0);
546 instList[new_inst->threadNumber].push_back(new_inst);
552 // Have this instruction set itself as the producer of its destination
554 addToProducers(new_inst);
556 // If it's a memory instruction, add it to the memory dependency
558 if (new_inst->isMemRef()) {
559 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
562 ++iqNonSpecInstsAdded;
564 count[new_inst->threadNumber]++;
566 assert(freeEntries == (numEntries - countInsts()));
569 template <class Impl>
571 InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
573 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
575 insertNonSpec(barr_inst);
578 template <class Impl>
579 typename Impl::DynInstPtr
580 InstructionQueue<Impl>::getInstToExecute()
582 assert(!instsToExecute.empty());
583 DynInstPtr inst = instsToExecute.front();
584 instsToExecute.pop_front();
588 template <class Impl>
590 InstructionQueue<Impl>::addToOrderList(OpClass op_class)
592 assert(!readyInsts[op_class].empty());
594 ListOrderEntry queue_entry;
596 queue_entry.queueType = op_class;
598 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
600 ListOrderIt list_it = listOrder.begin();
601 ListOrderIt list_end_it = listOrder.end();
603 while (list_it != list_end_it) {
604 if ((*list_it).oldestInst > queue_entry.oldestInst) {
611 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
612 queueOnList[op_class] = true;
615 template <class Impl>
617 InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
619 // Get iterator of next item on the list
620 // Delete the original iterator
621 // Determine if the next item is either the end of the list or younger
622 // than the new instruction. If so, then add in a new iterator right here.
623 // If not, then move along.
624 ListOrderEntry queue_entry;
625 OpClass op_class = (*list_order_it).queueType;
626 ListOrderIt next_it = list_order_it;
630 queue_entry.queueType = op_class;
631 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
633 while (next_it != listOrder.end() &&
634 (*next_it).oldestInst < queue_entry.oldestInst) {
638 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
641 template <class Impl>
643 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
645 // The CPU could have been sleeping until this op completed (*extremely*
646 // long latency op). Wake it if it was. This may be overkill.
647 if (isSwitchedOut()) {
654 fuPool->freeUnitNextCycle(fu_idx);
656 // @todo: Ensure that these FU Completions happen at the beginning
657 // of a cycle, otherwise they could add too many instructions to
659 issueToExecuteQueue->access(0)->size++;
660 instsToExecute.push_back(inst);
663 // @todo: Figure out a better way to remove the squashed items from the
664 // lists. Checking the top item of each list to see if it's squashed
665 // wastes time and forces jumps.
666 template <class Impl>
668 InstructionQueue<Impl>::scheduleReadyInsts()
670 DPRINTF(IQ, "Attempting to schedule ready instructions from "
673 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
675 // Have iterator to head of the list
676 // While I haven't exceeded bandwidth or reached the end of the list,
677 // Try to get a FU that can do what this op needs.
678 // If successful, change the oldestInst to the new top of the list, put
679 // the queue in the proper place in the list.
680 // Increment the iterator.
681 // This will avoid trying to schedule a certain op class if there are no
682 // FUs that handle it.
683 ListOrderIt order_it = listOrder.begin();
684 ListOrderIt order_end_it = listOrder.end();
685 int total_issued = 0;
687 while (total_issued < totalWidth &&
688 iewStage->canIssue() &&
689 order_it != order_end_it) {
690 OpClass op_class = (*order_it).queueType;
692 assert(!readyInsts[op_class].empty());
694 DynInstPtr issuing_inst = readyInsts[op_class].top();
696 assert(issuing_inst->seqNum == (*order_it).oldestInst);
698 if (issuing_inst->isSquashed()) {
699 readyInsts[op_class].pop();
701 if (!readyInsts[op_class].empty()) {
702 moveToYoungerInst(order_it);
704 readyIt[op_class] = listOrder.end();
705 queueOnList[op_class] = false;
708 listOrder.erase(order_it++);
710 ++iqSquashedInstsIssued;
717 int tid = issuing_inst->threadNumber;
719 if (op_class != No_OpClass) {
720 idx = fuPool->getUnit(op_class);
723 op_latency = fuPool->getOpLatency(op_class);
727 // If we have an instruction that doesn't require a FU, or a
728 // valid FU, then schedule for execution.
729 if (idx == -2 || idx != -1) {
730 if (op_latency == 1) {
732 instsToExecute.push_back(issuing_inst);
734 // Add the FU onto the list of FU's to be freed next
735 // cycle if we used one.
737 fuPool->freeUnitNextCycle(idx);
739 int issue_latency = fuPool->getIssueLatency(op_class);
740 // Generate completion event for the FU
741 FUCompletion *execution = new FUCompletion(issuing_inst,
744 execution->schedule(curTick + cpu->cycles(issue_latency - 1));
746 // @todo: Enforce that issue_latency == 1 or op_latency
747 if (issue_latency > 1) {
748 // If FU isn't pipelined, then it must be freed
749 // upon the execution completing.
750 execution->setFreeFU();
752 // Add the FU onto the list of FU's to be freed next cycle.
753 fuPool->freeUnitNextCycle(idx);
757 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
759 tid, issuing_inst->readPC(),
760 issuing_inst->seqNum);
762 readyInsts[op_class].pop();
764 if (!readyInsts[op_class].empty()) {
765 moveToYoungerInst(order_it);
767 readyIt[op_class] = listOrder.end();
768 queueOnList[op_class] = false;
771 issuing_inst->setIssued();
774 if (!issuing_inst->isMemRef()) {
775 // Memory instructions can not be freed from the IQ until they
779 issuing_inst->clearInIQ();
781 memDepUnit[tid].issue(issuing_inst);
784 listOrder.erase(order_it++);
785 statIssuedInstType[tid][op_class]++;
786 iewStage->incrWb(issuing_inst->seqNum);
788 statFuBusy[op_class]++;
794 numIssuedDist.sample(total_issued);
795 iqInstsIssued+= total_issued;
797 // If we issued any instructions, tell the CPU we had activity.
799 cpu->activityThisCycle();
801 DPRINTF(IQ, "Not able to schedule any instructions.\n");
805 template <class Impl>
807 InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
809 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
810 "to execute.\n", inst);
812 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
814 assert(inst_it != nonSpecInsts.end());
816 unsigned tid = (*inst_it).second->threadNumber;
818 (*inst_it).second->setCanIssue();
820 if (!(*inst_it).second->isMemRef()) {
821 addIfReady((*inst_it).second);
823 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
826 (*inst_it).second = NULL;
828 nonSpecInsts.erase(inst_it);
831 template <class Impl>
833 InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
835 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
838 ListIt iq_it = instList[tid].begin();
840 while (iq_it != instList[tid].end() &&
841 (*iq_it)->seqNum <= inst) {
843 instList[tid].pop_front();
846 assert(freeEntries == (numEntries - countInsts()));
849 template <class Impl>
851 InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
855 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
857 assert(!completed_inst->isSquashed());
859 // Tell the memory dependence unit to wake any dependents on this
860 // instruction if it is a memory instruction. Also complete the memory
861 // instruction at this point since we know it executed without issues.
862 // @todo: Might want to rename "completeMemInst" to something that
863 // indicates that it won't need to be replayed, and call this
864 // earlier. Might not be a big deal.
865 if (completed_inst->isMemRef()) {
866 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
867 completeMemInst(completed_inst);
868 } else if (completed_inst->isMemBarrier() ||
869 completed_inst->isWriteBarrier()) {
870 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
873 for (int dest_reg_idx = 0;
874 dest_reg_idx < completed_inst->numDestRegs();
877 PhysRegIndex dest_reg =
878 completed_inst->renamedDestRegIdx(dest_reg_idx);
880 // Special case of uniq or control registers. They are not
881 // handled by the IQ and thus have no dependency graph entry.
882 // @todo Figure out a cleaner way to handle this.
883 if (dest_reg >= numPhysRegs) {
887 DPRINTF(IQ, "Waking any dependents on register %i.\n",
890 //Go through the dependency chain, marking the registers as
891 //ready within the waiting instructions.
892 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
895 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
898 // Might want to give more information to the instruction
899 // so that it knows which of its source registers is
900 // ready. However that would mean that the dependency
901 // graph entries would need to hold the src_reg_idx.
902 dep_inst->markSrcRegReady();
904 addIfReady(dep_inst);
906 dep_inst = dependGraph.pop(dest_reg);
911 // Reset the head node now that all of its dependents have
913 assert(dependGraph.empty(dest_reg));
914 dependGraph.clearInst(dest_reg);
916 // Mark the scoreboard as having that register ready.
917 regScoreboard[dest_reg] = true;
922 template <class Impl>
924 InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
926 OpClass op_class = ready_inst->opClass();
928 readyInsts[op_class].push(ready_inst);
930 // Will need to reorder the list if either a queue is not on the list,
931 // or it has an older instruction than last time.
932 if (!queueOnList[op_class]) {
933 addToOrderList(op_class);
934 } else if (readyInsts[op_class].top()->seqNum <
935 (*readyIt[op_class]).oldestInst) {
936 listOrder.erase(readyIt[op_class]);
937 addToOrderList(op_class);
940 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
941 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
942 ready_inst->readPC(), op_class, ready_inst->seqNum);
945 template <class Impl>
947 InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
949 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
952 template <class Impl>
954 InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
956 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
959 template <class Impl>
961 InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
963 int tid = completed_inst->threadNumber;
965 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
966 completed_inst->readPC(), completed_inst->seqNum);
970 completed_inst->memOpDone = true;
972 memDepUnit[tid].completed(completed_inst);
977 template <class Impl>
979 InstructionQueue<Impl>::violation(DynInstPtr &store,
980 DynInstPtr &faulting_load)
982 memDepUnit[store->threadNumber].violation(store, faulting_load);
985 template <class Impl>
987 InstructionQueue<Impl>::squash(unsigned tid)
989 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
992 // Read instruction sequence number of last instruction out of the
994 #if ISA_HAS_DELAY_SLOT
995 squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
997 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1000 // Call doSquash if there are insts in the IQ
1001 if (count[tid] > 0) {
1005 // Also tell the memory dependence unit to squash.
1006 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1009 template <class Impl>
1011 InstructionQueue<Impl>::doSquash(unsigned tid)
1013 // Start at the tail.
1014 ListIt squash_it = instList[tid].end();
1017 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1018 tid, squashedSeqNum[tid]);
1020 // Squash any instructions younger than the squashed sequence number
1022 while (squash_it != instList[tid].end() &&
1023 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1025 DynInstPtr squashed_inst = (*squash_it);
1027 // Only handle the instruction if it actually is in the IQ and
1028 // hasn't already been squashed in the IQ.
1029 if (squashed_inst->threadNumber != tid ||
1030 squashed_inst->isSquashedInIQ()) {
1035 if (!squashed_inst->isIssued() ||
1036 (squashed_inst->isMemRef() &&
1037 !squashed_inst->memOpDone)) {
1039 // Remove the instruction from the dependency list.
1040 if (!squashed_inst->isNonSpeculative() &&
1041 !squashed_inst->isStoreConditional() &&
1042 !squashed_inst->isMemBarrier() &&
1043 !squashed_inst->isWriteBarrier()) {
1045 for (int src_reg_idx = 0;
1046 src_reg_idx < squashed_inst->numSrcRegs();
1049 PhysRegIndex src_reg =
1050 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1052 // Only remove it from the dependency graph if it
1053 // was placed there in the first place.
1055 // Instead of doing a linked list traversal, we
1056 // can just remove these squashed instructions
1057 // either at issue time, or when the register is
1058 // overwritten. The only downside to this is it
1059 // leaves more room for error.
1061 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1062 src_reg < numPhysRegs) {
1063 dependGraph.remove(src_reg, squashed_inst);
1067 ++iqSquashedOperandsExamined;
1070 NonSpecMapIt ns_inst_it =
1071 nonSpecInsts.find(squashed_inst->seqNum);
1072 assert(ns_inst_it != nonSpecInsts.end());
1074 (*ns_inst_it).second = NULL;
1076 nonSpecInsts.erase(ns_inst_it);
1078 ++iqSquashedNonSpecRemoved;
1081 // Might want to also clear out the head of the dependency graph.
1083 // Mark it as squashed within the IQ.
1084 squashed_inst->setSquashedInIQ();
1086 // @todo: Remove this hack where several statuses are set so the
1087 // inst will flow through the rest of the pipeline.
1088 squashed_inst->setIssued();
1089 squashed_inst->setCanCommit();
1090 squashed_inst->clearInIQ();
1092 //Update Thread IQ Count
1093 count[squashed_inst->threadNumber]--;
1097 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
1099 tid, squashed_inst->seqNum, squashed_inst->readPC());
1102 instList[tid].erase(squash_it--);
1103 ++iqSquashedInstsExamined;
1107 template <class Impl>
1109 InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1111 // Loop through the instruction's source registers, adding
1112 // them to the dependency list if they are not ready.
1113 int8_t total_src_regs = new_inst->numSrcRegs();
1114 bool return_val = false;
1116 for (int src_reg_idx = 0;
1117 src_reg_idx < total_src_regs;
1120 // Only add it to the dependency graph if it's not ready.
1121 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1122 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1124 // Check the IQ's scoreboard to make sure the register
1125 // hasn't become ready while the instruction was in flight
1126 // between stages. Only if it really isn't ready should
1127 // it be added to the dependency graph.
1128 if (src_reg >= numPhysRegs) {
1130 } else if (regScoreboard[src_reg] == false) {
1131 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1132 "is being added to the dependency chain.\n",
1133 new_inst->readPC(), src_reg);
1135 dependGraph.insert(src_reg, new_inst);
1137 // Change the return value to indicate that something
1138 // was added to the dependency graph.
1141 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1142 "became ready before it reached the IQ.\n",
1143 new_inst->readPC(), src_reg);
1144 // Mark a register ready within the instruction.
1145 new_inst->markSrcRegReady(src_reg_idx);
1153 template <class Impl>
1155 InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1157 // Nothing really needs to be marked when an instruction becomes
1158 // the producer of a register's value, but for convenience a ptr
1159 // to the producing instruction will be placed in the head node of
1160 // the dependency links.
1161 int8_t total_dest_regs = new_inst->numDestRegs();
1163 for (int dest_reg_idx = 0;
1164 dest_reg_idx < total_dest_regs;
1167 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1169 // Instructions that use the misc regs will have a reg number
1170 // higher than the normal physical registers. In this case these
1171 // registers are not renamed, and there is no need to track
1172 // dependencies as these instructions must be executed at commit.
1173 if (dest_reg >= numPhysRegs) {
1177 if (!dependGraph.empty(dest_reg)) {
1179 panic("Dependency graph %i not empty!", dest_reg);
1182 dependGraph.setInst(dest_reg, new_inst);
1184 // Mark the scoreboard to say it's not yet ready.
1185 regScoreboard[dest_reg] = false;
1189 template <class Impl>
1191 InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1193 // If the instruction now has all of its source registers
1194 // available, then add it to the list of ready instructions.
1195 if (inst->readyToIssue()) {
1197 //Add the instruction to the proper ready list.
1198 if (inst->isMemRef()) {
1200 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1202 // Message to the mem dependence unit that this instruction has
1203 // its registers ready.
1204 memDepUnit[inst->threadNumber].regsReady(inst);
1209 OpClass op_class = inst->opClass();
1211 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1212 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1213 inst->readPC(), op_class, inst->seqNum);
1215 readyInsts[op_class].push(inst);
1217 // Will need to reorder the list if either a queue is not on the list,
1218 // or it has an older instruction than last time.
1219 if (!queueOnList[op_class]) {
1220 addToOrderList(op_class);
1221 } else if (readyInsts[op_class].top()->seqNum <
1222 (*readyIt[op_class]).oldestInst) {
1223 listOrder.erase(readyIt[op_class]);
1224 addToOrderList(op_class);
1229 template <class Impl>
1231 InstructionQueue<Impl>::countInsts()
1234 //ksewell:This works but definitely could use a cleaner write
1235 //with a more intuitive way of counting. Right now it's
1236 //just brute force ....
1237 // Change the #if if you want to use this method.
1238 int total_insts = 0;
1240 for (int i = 0; i < numThreads; ++i) {
1241 ListIt count_it = instList[i].begin();
1243 while (count_it != instList[i].end()) {
1244 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1245 if (!(*count_it)->isIssued()) {
1247 } else if ((*count_it)->isMemRef() &&
1248 !(*count_it)->memOpDone) {
1249 // Loads that have not been marked as executed still count
1250 // towards the total instructions.
1261 return numEntries - freeEntries;
1265 template <class Impl>
1267 InstructionQueue<Impl>::dumpLists()
1269 for (int i = 0; i < Num_OpClasses; ++i) {
1270 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1275 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1277 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1278 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1280 cprintf("Non speculative list: ");
1282 while (non_spec_it != non_spec_end_it) {
1283 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1284 (*non_spec_it).second->seqNum);
1290 ListOrderIt list_order_it = listOrder.begin();
1291 ListOrderIt list_order_end_it = listOrder.end();
1294 cprintf("List order: ");
1296 while (list_order_it != list_order_end_it) {
1297 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1298 (*list_order_it).oldestInst);
1308 template <class Impl>
1310 InstructionQueue<Impl>::dumpInsts()
1312 for (int i = 0; i < numThreads; ++i) {
1315 ListIt inst_list_it = instList[i].begin();
1317 while (inst_list_it != instList[i].end())
1319 cprintf("Instruction:%i\n",
1321 if (!(*inst_list_it)->isSquashed()) {
1322 if (!(*inst_list_it)->isIssued()) {
1324 cprintf("Count:%i\n", valid_num);
1325 } else if ((*inst_list_it)->isMemRef() &&
1326 !(*inst_list_it)->memOpDone) {
1327 // Loads that have not been marked as executed
1328 // still count towards the total instructions.
1330 cprintf("Count:%i\n", valid_num);
1334 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1335 "Issued:%i\nSquashed:%i\n",
1336 (*inst_list_it)->readPC(),
1337 (*inst_list_it)->seqNum,
1338 (*inst_list_it)->threadNumber,
1339 (*inst_list_it)->isIssued(),
1340 (*inst_list_it)->isSquashed());
1342 if ((*inst_list_it)->isMemRef()) {
1343 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1353 cprintf("Insts to Execute list:\n");
1357 ListIt inst_list_it = instsToExecute.begin();
1359 while (inst_list_it != instsToExecute.end())
1361 cprintf("Instruction:%i\n",
1363 if (!(*inst_list_it)->isSquashed()) {
1364 if (!(*inst_list_it)->isIssued()) {
1366 cprintf("Count:%i\n", valid_num);
1367 } else if ((*inst_list_it)->isMemRef() &&
1368 !(*inst_list_it)->memOpDone) {
1369 // Loads that have not been marked as executed
1370 // still count towards the total instructions.
1372 cprintf("Count:%i\n", valid_num);
1376 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1377 "Issued:%i\nSquashed:%i\n",
1378 (*inst_list_it)->readPC(),
1379 (*inst_list_it)->seqNum,
1380 (*inst_list_it)->threadNumber,
1381 (*inst_list_it)->isIssued(),
1382 (*inst_list_it)->isSquashed());
1384 if ((*inst_list_it)->isMemRef()) {
1385 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);