2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
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13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
31 #ifndef __CPU_O3_LSQ_HH__
32 #define __CPU_O3_LSQ_HH__
37 #include "config/full_system.hh"
38 #include "cpu/inst_seq.hh"
39 #include "cpu/o3/lsq_unit.hh"
40 #include "mem/port.hh"
41 #include "sim/sim_object.hh"
43 class DerivO3CPUParams;
48 typedef typename Impl::O3CPU O3CPU;
49 typedef typename Impl::DynInstPtr DynInstPtr;
50 typedef typename Impl::CPUPol::IEW IEW;
51 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
60 /** Constructs an LSQ with the given parameters. */
61 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
63 /** Returns the name of the LSQ. */
64 std::string name() const;
66 /** Registers statistics of each LSQ unit. */
69 /** Returns dcache port.
70 * @todo: Dcache port needs to be moved up to this level for SMT
71 * to work. For now it just returns the port from one of the
74 Port *getDcachePort() { return &dcachePort; }
76 /** Sets the pointer to the list of active threads. */
77 void setActiveThreads(std::list<unsigned> *at_ptr);
78 /** Switches out the LSQ. */
80 /** Takes over execution from another CPU's thread. */
83 /** Number of entries needed for the given amount of threads.*/
84 int entryAmount(int num_threads);
85 void removeEntries(unsigned tid);
86 /** Reset the max entries for each thread. */
88 /** Resize the max entries for a thread. */
89 void resizeEntries(unsigned size, unsigned tid);
93 /** Ticks a specific LSQ Unit. */
94 void tick(unsigned tid)
95 { thread[tid].tick(); }
97 /** Inserts a load into the LSQ. */
98 void insertLoad(DynInstPtr &load_inst);
99 /** Inserts a store into the LSQ. */
100 void insertStore(DynInstPtr &store_inst);
102 /** Executes a load. */
103 Fault executeLoad(DynInstPtr &inst);
105 /** Executes a store. */
106 Fault executeStore(DynInstPtr &inst);
109 * Commits loads up until the given sequence number for a specific thread.
111 void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
112 { thread[tid].commitLoads(youngest_inst); }
115 * Commits stores up until the given sequence number for a specific thread.
117 void commitStores(InstSeqNum &youngest_inst, unsigned tid)
118 { thread[tid].commitStores(youngest_inst); }
121 * Attempts to write back stores until all cache ports are used or the
122 * interface becomes blocked.
124 void writebackStores();
125 /** Same as above, but only for one thread. */
126 void writebackStores(unsigned tid);
129 * Squash instructions from a thread until the specified sequence number.
131 void squash(const InstSeqNum &squashed_num, unsigned tid)
132 { thread[tid].squash(squashed_num); }
134 /** Returns whether or not there was a memory ordering violation. */
137 * Returns whether or not there was a memory ordering violation for a
140 bool violation(unsigned tid)
141 { return thread[tid].violation(); }
143 /** Returns if a load is blocked due to the memory system for a specific
146 bool loadBlocked(unsigned tid)
147 { return thread[tid].loadBlocked(); }
149 bool isLoadBlockedHandled(unsigned tid)
150 { return thread[tid].isLoadBlockedHandled(); }
152 void setLoadBlockedHandled(unsigned tid)
153 { thread[tid].setLoadBlockedHandled(); }
155 /** Gets the instruction that caused the memory ordering violation. */
156 DynInstPtr getMemDepViolator(unsigned tid)
157 { return thread[tid].getMemDepViolator(); }
159 /** Returns the head index of the load queue for a specific thread. */
160 int getLoadHead(unsigned tid)
161 { return thread[tid].getLoadHead(); }
163 /** Returns the sequence number of the head of the load queue. */
164 InstSeqNum getLoadHeadSeqNum(unsigned tid)
166 return thread[tid].getLoadHeadSeqNum();
169 /** Returns the head index of the store queue. */
170 int getStoreHead(unsigned tid)
171 { return thread[tid].getStoreHead(); }
173 /** Returns the sequence number of the head of the store queue. */
174 InstSeqNum getStoreHeadSeqNum(unsigned tid)
176 return thread[tid].getStoreHeadSeqNum();
179 /** Returns the number of instructions in all of the queues. */
181 /** Returns the number of instructions in the queues of one thread. */
182 int getCount(unsigned tid)
183 { return thread[tid].getCount(); }
185 /** Returns the total number of loads in the load queue. */
187 /** Returns the total number of loads for a single thread. */
188 int numLoads(unsigned tid)
189 { return thread[tid].numLoads(); }
191 /** Returns the total number of stores in the store queue. */
193 /** Returns the total number of stores for a single thread. */
194 int numStores(unsigned tid)
195 { return thread[tid].numStores(); }
197 /** Returns the total number of loads that are ready. */
199 /** Returns the number of loads that are ready for a single thread. */
200 int numLoadsReady(unsigned tid)
201 { return thread[tid].numLoadsReady(); }
203 /** Returns the number of free entries. */
204 unsigned numFreeEntries();
205 /** Returns the number of free entries for a specific thread. */
206 unsigned numFreeEntries(unsigned tid);
208 /** Returns if the LSQ is full (either LQ or SQ is full). */
211 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
214 bool isFull(unsigned tid);
216 /** Returns if any of the LQs are full. */
218 /** Returns if the LQ of a given thread is full. */
219 bool lqFull(unsigned tid);
221 /** Returns if any of the SQs are full. */
223 /** Returns if the SQ of a given thread is full. */
224 bool sqFull(unsigned tid);
227 * Returns if the LSQ is stalled due to a memory operation that must be
232 * Returns if the LSQ of a specific thread is stalled due to a memory
233 * operation that must be replayed.
235 bool isStalled(unsigned tid);
237 /** Returns whether or not there are any stores to write back to memory. */
238 bool hasStoresToWB();
240 /** Returns whether or not a specific thread has any stores to write back
243 bool hasStoresToWB(unsigned tid)
244 { return thread[tid].hasStoresToWB(); }
246 /** Returns the number of stores a specific thread has to write back. */
247 int numStoresToWB(unsigned tid)
248 { return thread[tid].numStoresToWB(); }
250 /** Returns if the LSQ will write back to memory this cycle. */
252 /** Returns if the LSQ of a specific thread will write back to memory this
255 bool willWB(unsigned tid)
256 { return thread[tid].willWB(); }
258 /** Returns if the cache is currently blocked. */
260 { return retryTid != -1; }
262 /** Sets the retry thread id, indicating that one of the LSQUnits
263 * tried to access the cache but the cache was blocked. */
264 void setRetryTid(int tid)
267 /** Debugging function to print out all instructions. */
269 /** Debugging function to print out instructions from a specific thread. */
270 void dumpInsts(unsigned tid)
271 { thread[tid].dumpInsts(); }
273 /** Executes a read operation, using the load specified at the load index. */
275 Fault read(RequestPtr req, T &data, int load_idx);
277 /** Executes a store operation, using the store specified at the store
281 Fault write(RequestPtr req, T &data, int store_idx);
283 /** The CPU pointer. */
286 /** The IEW stage pointer. */
289 /** DcachePort class for this LSQ. Handles doing the
290 * communication with the cache/memory.
292 class DcachePort : public Port
295 /** Pointer to LSQ. */
299 /** Default constructor. */
300 DcachePort(LSQ *_lsq)
301 : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq)
306 virtual void setPeer(Port *port);
309 /** Atomic version of receive. Panics. */
310 virtual Tick recvAtomic(PacketPtr pkt);
312 /** Functional version of receive. Panics. */
313 virtual void recvFunctional(PacketPtr pkt);
315 /** Receives status change. Other than range changing, panics. */
316 virtual void recvStatusChange(Status status);
318 /** Returns the address ranges of this device. */
319 virtual void getDeviceAddressRanges(AddrRangeList &resp,
321 { resp.clear(); snoop = true; }
323 /** Timing version of receive. Handles writing back and
324 * completing the load or store that has returned from
326 virtual bool recvTiming(PacketPtr pkt);
328 /** Handles doing a retry of the previous send. */
329 virtual void recvRetry();
333 DcachePort dcachePort;
336 /** Tell the CPU to update the Phys and Virt ports. */
337 void updateMemPorts() { cpu->updateMemPorts(); }
341 /** The LSQ policy for SMT mode. */
344 /** The LSQ units for individual threads. */
345 LSQUnit thread[Impl::MaxThreads];
347 /** List of Active Threads in System. */
348 std::list<unsigned> *activeThreads;
350 /** Total Size of LQ Entries. */
352 /** Total Size of SQ Entries. */
355 /** Max LQ Size - Used to Enforce Sharing Policies. */
356 unsigned maxLQEntries;
358 /** Max SQ Size - Used to Enforce Sharing Policies. */
359 unsigned maxSQEntries;
361 /** Number of Threads. */
364 /** The thread id of the LSQ Unit that is currently waiting for a
369 template <class Impl>
372 LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
374 unsigned tid = req->getThreadNum();
376 return thread[tid].read(req, data, load_idx);
379 template <class Impl>
382 LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
384 unsigned tid = req->getThreadNum();
386 return thread[tid].write(req, data, store_idx);
389 #endif // __CPU_O3_LSQ_HH__