src/cpu/o3/lsq.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #ifndef __CPU_O3_LSQ_HH__
  32 #define __CPU_O3_LSQ_HH__
  33
  34 #include <map>
  35 #include <queue>
  36
  37 #include "config/full_system.hh"
  38 #include "cpu/o3/lsq_unit.hh"
  39 #include "cpu/inst_seq.hh"
  40 #include "mem/port.hh"
  41 #include "sim/sim_object.hh"
  42
  43 class DerivO3CPUParams;
  44
  45 template <class Impl>
  46 class LSQ {
  47   public:
  48     typedef typename Impl::O3CPU O3CPU;
  49     typedef typename Impl::DynInstPtr DynInstPtr;
  50     typedef typename Impl::CPUPol::IEW IEW;
  51     typedef typename Impl::CPUPol::LSQUnit LSQUnit;
  52
  53     /** SMT policy. */
  54     enum LSQPolicy {
  55         Dynamic,
  56         Partitioned,
  57         Threshold
  58     };
  59
  60     /** Constructs an LSQ with the given parameters. */
  61     LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
  62
  63     /** Returns the name of the LSQ. */
  64     std::string name() const;
  65
  66     /** Registers statistics of each LSQ unit. */
  67     void regStats();
  68
  69     /** Returns dcache port.
  70      *  @todo: Dcache port needs to be moved up to this level for SMT
  71      *  to work.  For now it just returns the port from one of the
  72      *  threads.
  73      */
  74     Port *getDcachePort() { return &dcachePort; }
  75
  76     /** Sets the pointer to the list of active threads. */
  77     void setActiveThreads(std::list<ThreadID> *at_ptr);
  78     /** Switches out the LSQ. */
  79     void switchOut();
  80     /** Takes over execution from another CPU's thread. */
  81     void takeOverFrom();
  82
  83     /** Number of entries needed for the given amount of threads.*/
  84     int entryAmount(ThreadID num_threads);
  85     void removeEntries(ThreadID tid);
  86     /** Reset the max entries for each thread. */
  87     void resetEntries();
  88     /** Resize the max entries for a thread. */
  89     void resizeEntries(unsigned size, ThreadID tid);
  90
  91     /** Ticks the LSQ. */
  92     void tick();
  93     /** Ticks a specific LSQ Unit. */
  94     void tick(ThreadID tid)
  95     { thread[tid].tick(); }
  96
  97     /** Inserts a load into the LSQ. */
  98     void insertLoad(DynInstPtr &load_inst);
  99     /** Inserts a store into the LSQ. */
 100     void insertStore(DynInstPtr &store_inst);
 101
 102     /** Executes a load. */
 103     Fault executeLoad(DynInstPtr &inst);
 104
 105     /** Executes a store. */
 106     Fault executeStore(DynInstPtr &inst);
 107
 108     /**
 109      * Commits loads up until the given sequence number for a specific thread.
 110      */
 111     void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
 112     { thread[tid].commitLoads(youngest_inst); }
 113
 114     /**
 115      * Commits stores up until the given sequence number for a specific thread.
 116      */
 117     void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
 118     { thread[tid].commitStores(youngest_inst); }
 119
 120     /**
 121      * Attempts to write back stores until all cache ports are used or the
 122      * interface becomes blocked.
 123      */
 124     void writebackStores();
 125     /** Same as above, but only for one thread. */
 126     void writebackStores(ThreadID tid);
 127
 128     /**
 129      * Squash instructions from a thread until the specified sequence number.
 130      */
 131     void squash(const InstSeqNum &squashed_num, ThreadID tid)
 132     { thread[tid].squash(squashed_num); }
 133
 134     /** Returns whether or not there was a memory ordering violation. */
 135     bool violation();
 136     /**
 137      * Returns whether or not there was a memory ordering violation for a
 138      * specific thread.
 139      */
 140     bool violation(ThreadID tid)
 141     { return thread[tid].violation(); }
 142
 143     /** Returns if a load is blocked due to the memory system for a specific
 144      *  thread.
 145      */
 146     bool loadBlocked(ThreadID tid)
 147     { return thread[tid].loadBlocked(); }
 148
 149     bool isLoadBlockedHandled(ThreadID tid)
 150     { return thread[tid].isLoadBlockedHandled(); }
 151
 152     void setLoadBlockedHandled(ThreadID tid)
 153     { thread[tid].setLoadBlockedHandled(); }
 154
 155     /** Gets the instruction that caused the memory ordering violation. */
 156     DynInstPtr getMemDepViolator(ThreadID tid)
 157     { return thread[tid].getMemDepViolator(); }
 158
 159     /** Returns the head index of the load queue for a specific thread. */
 160     int getLoadHead(ThreadID tid)
 161     { return thread[tid].getLoadHead(); }
 162
 163     /** Returns the sequence number of the head of the load queue. */
 164     InstSeqNum getLoadHeadSeqNum(ThreadID tid)
 165     {
 166         return thread[tid].getLoadHeadSeqNum();
 167     }
 168
 169     /** Returns the head index of the store queue. */
 170     int getStoreHead(ThreadID tid)
 171     { return thread[tid].getStoreHead(); }
 172
 173     /** Returns the sequence number of the head of the store queue. */
 174     InstSeqNum getStoreHeadSeqNum(ThreadID tid)
 175     {
 176         return thread[tid].getStoreHeadSeqNum();
 177     }
 178
 179     /** Returns the number of instructions in all of the queues. */
 180     int getCount();
 181     /** Returns the number of instructions in the queues of one thread. */
 182     int getCount(ThreadID tid)
 183     { return thread[tid].getCount(); }
 184
 185     /** Returns the total number of loads in the load queue. */
 186     int numLoads();
 187     /** Returns the total number of loads for a single thread. */
 188     int numLoads(ThreadID tid)
 189     { return thread[tid].numLoads(); }
 190
 191     /** Returns the total number of stores in the store queue. */
 192     int numStores();
 193     /** Returns the total number of stores for a single thread. */
 194     int numStores(ThreadID tid)
 195     { return thread[tid].numStores(); }
 196
 197     /** Returns the total number of loads that are ready. */
 198     int numLoadsReady();
 199     /** Returns the number of loads that are ready for a single thread. */
 200     int numLoadsReady(ThreadID tid)
 201     { return thread[tid].numLoadsReady(); }
 202
 203     /** Returns the number of free entries. */
 204     unsigned numFreeEntries();
 205     /** Returns the number of free entries for a specific thread. */
 206     unsigned numFreeEntries(ThreadID tid);
 207
 208     /** Returns if the LSQ is full (either LQ or SQ is full). */
 209     bool isFull();
 210     /**
 211      * Returns if the LSQ is full for a specific thread (either LQ or SQ is
 212      * full).
 213      */
 214     bool isFull(ThreadID tid);
 215
 216     /** Returns if any of the LQs are full. */
 217     bool lqFull();
 218     /** Returns if the LQ of a given thread is full. */
 219     bool lqFull(ThreadID tid);
 220
 221     /** Returns if any of the SQs are full. */
 222     bool sqFull();
 223     /** Returns if the SQ of a given thread is full. */
 224     bool sqFull(ThreadID tid);
 225
 226     /**
 227      * Returns if the LSQ is stalled due to a memory operation that must be
 228      * replayed.
 229      */
 230     bool isStalled();
 231     /**
 232      * Returns if the LSQ of a specific thread is stalled due to a memory
 233      * operation that must be replayed.
 234      */
 235     bool isStalled(ThreadID tid);
 236
 237     /** Returns whether or not there are any stores to write back to memory. */
 238     bool hasStoresToWB();
 239
 240     /** Returns whether or not a specific thread has any stores to write back
 241      * to memory.
 242      */
 243     bool hasStoresToWB(ThreadID tid)
 244     { return thread[tid].hasStoresToWB(); }
 245
 246     /** Returns the number of stores a specific thread has to write back. */
 247     int numStoresToWB(ThreadID tid)
 248     { return thread[tid].numStoresToWB(); }
 249
 250     /** Returns if the LSQ will write back to memory this cycle. */
 251     bool willWB();
 252     /** Returns if the LSQ of a specific thread will write back to memory this
 253      * cycle.
 254      */
 255     bool willWB(ThreadID tid)
 256     { return thread[tid].willWB(); }
 257
 258     /** Returns if the cache is currently blocked. */
 259     bool cacheBlocked()
 260     { return retryTid != InvalidThreadID; }
 261
 262     /** Sets the retry thread id, indicating that one of the LSQUnits
 263      * tried to access the cache but the cache was blocked. */
 264     void setRetryTid(ThreadID tid)
 265     { retryTid = tid; }
 266
 267     /** Debugging function to print out all instructions. */
 268     void dumpInsts();
 269     /** Debugging function to print out instructions from a specific thread. */
 270     void dumpInsts(ThreadID tid)
 271     { thread[tid].dumpInsts(); }
 272
 273     /** Executes a read operation, using the load specified at the load
 274      * index.
 275      */
 276     Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
 277                uint8_t *data, int load_idx);
 278
 279     /** Executes a store operation, using the store specified at the store
 280      * index.
 281      */
 282     Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
 283                 uint8_t *data, int store_idx);
 284
 285     /** The CPU pointer. */
 286     O3CPU *cpu;
 287
 288     /** The IEW stage pointer. */
 289     IEW *iewStage;
 290
 291     /** DcachePort class for this LSQ.  Handles doing the
 292      * communication with the cache/memory.
 293      */
 294     class DcachePort : public Port
 295     {
 296       protected:
 297         /** Pointer to LSQ. */
 298         LSQ *lsq;
 299
 300       public:
 301         /** Default constructor. */
 302         DcachePort(LSQ *_lsq)
 303             : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq)
 304         { }
 305
 306         bool snoopRangeSent;
 307
 308         virtual void setPeer(Port *port);
 309
 310       protected:
 311         /** Atomic version of receive.  Panics. */
 312         virtual Tick recvAtomic(PacketPtr pkt);
 313
 314         /** Functional version of receive.  Panics. */
 315         virtual void recvFunctional(PacketPtr pkt);
 316
 317         /** Receives status change.  Other than range changing, panics. */
 318         virtual void recvStatusChange(Status status);
 319
 320         /** Returns the address ranges of this device. */
 321         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 322                                             bool &snoop)
 323         { resp.clear(); snoop = true; }
 324
 325         /** Timing version of receive.  Handles writing back and
 326          * completing the load or store that has returned from
 327          * memory. */
 328         virtual bool recvTiming(PacketPtr pkt);
 329
 330         /** Handles doing a retry of the previous send. */
 331         virtual void recvRetry();
 332     };
 333
 334     /** D-cache port. */
 335     DcachePort dcachePort;
 336
 337 #if FULL_SYSTEM
 338     /** Tell the CPU to update the Phys and Virt ports. */
 339     void updateMemPorts() { cpu->updateMemPorts(); }
 340 #endif
 341
 342   protected:
 343     /** The LSQ policy for SMT mode. */
 344     LSQPolicy lsqPolicy;
 345
 346     /** The LSQ units for individual threads. */
 347     LSQUnit thread[Impl::MaxThreads];
 348
 349     /** List of Active Threads in System. */
 350     std::list<ThreadID> *activeThreads;
 351
 352     /** Total Size of LQ Entries. */
 353     unsigned LQEntries;
 354     /** Total Size of SQ Entries. */
 355     unsigned SQEntries;
 356
 357     /** Max LQ Size - Used to Enforce Sharing Policies. */
 358     unsigned maxLQEntries;
 359
 360     /** Max SQ Size - Used to Enforce Sharing Policies. */
 361     unsigned maxSQEntries;
 362
 363     /** Number of Threads. */
 364     ThreadID numThreads;
 365
 366     /** The thread id of the LSQ Unit that is currently waiting for a
 367      * retry. */
 368     ThreadID retryTid;
 369 };
 370
 371 template <class Impl>
 372 Fault
 373 LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
 374                 uint8_t *data, int load_idx)
 375 {
 376     ThreadID tid = req->threadId();
 377
 378     return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
 379 }
 380
 381 template <class Impl>
 382 Fault
 383 LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
 384                  uint8_t *data, int store_idx)
 385 {
 386     ThreadID tid = req->threadId();
 387
 388     return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
 389 }
 390
 391 #endif // __CPU_O3_LSQ_HH__