src/cpu/o3/lsq.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_O3_LSQ_HH__
  30 #define __CPU_O3_LSQ_HH__
  31
  32 #include <map>
  33 #include <queue>
  34
  35 #include "config/full_system.hh"
  36 #include "cpu/inst_seq.hh"
  37 //#include "cpu/o3/cpu_policy.hh"
  38 #include "cpu/o3/lsq_unit.hh"
  39 #include "mem/port.hh"
  40 //#include "mem/page_table.hh"
  41 #include "sim/sim_object.hh"
  42
  43 template <class Impl>
  44 class LSQ {
  45   public:
  46     typedef typename Impl::Params Params;
  47     typedef typename Impl::FullCPU FullCPU;
  48     typedef typename Impl::DynInstPtr DynInstPtr;
  49     typedef typename Impl::CPUPol::IEW IEW;
  50     typedef typename Impl::CPUPol::LSQUnit LSQUnit;
  51
  52     enum LSQPolicy {
  53         Dynamic,
  54         Partitioned,
  55         Threshold
  56     };
  57
  58     /** Constructs an LSQ with the given parameters. */
  59     LSQ(Params *params);
  60
  61     /** Returns the name of the LSQ. */
  62     std::string name() const;
  63
  64     /** Sets the pointer to the list of active threads. */
  65     void setActiveThreads(std::list<unsigned> *at_ptr);
  66     /** Sets the CPU pointer. */
  67     void setCPU(FullCPU *cpu_ptr);
  68     /** Sets the IEW stage pointer. */
  69     void setIEW(IEW *iew_ptr);
  70     /** Sets the page table pointer. */
  71 //    void setPageTable(PageTable *pt_ptr);
  72
  73     void switchOut();
  74     void takeOverFrom();
  75
  76     /** Number of entries needed for the given amount of threads.*/
  77     int entryAmount(int num_threads);
  78     void removeEntries(unsigned tid);
  79     /** Reset the max entries for each thread. */
  80     void resetEntries();
  81     /** Resize the max entries for a thread. */
  82     void resizeEntries(unsigned size, unsigned tid);
  83
  84     /** Ticks the LSQ. */
  85     void tick();
  86     /** Ticks a specific LSQ Unit. */
  87     void tick(unsigned tid)
  88     { thread[tid].tick(); }
  89
  90     /** Inserts a load into the LSQ. */
  91     void insertLoad(DynInstPtr &load_inst);
  92     /** Inserts a store into the LSQ. */
  93     void insertStore(DynInstPtr &store_inst);
  94
  95     /** Executes a load. */
  96     Fault executeLoad(DynInstPtr &inst);
  97
  98     Fault executeLoad(int lq_idx, unsigned tid)
  99     { return thread[tid].executeLoad(lq_idx); }
 100
 101     /** Executes a store. */
 102     Fault executeStore(DynInstPtr &inst);
 103
 104     /**
 105      * Commits loads up until the given sequence number for a specific thread.
 106      */
 107     void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
 108     { thread[tid].commitLoads(youngest_inst); }
 109
 110     /**
 111      * Commits stores up until the given sequence number for a specific thread.
 112      */
 113     void commitStores(InstSeqNum &youngest_inst, unsigned tid)
 114     { thread[tid].commitStores(youngest_inst); }
 115
 116     /**
 117      * Attempts to write back stores until all cache ports are used or the
 118      * interface becomes blocked.
 119      */
 120     void writebackStores();
 121     /** Same as above, but only for one thread. */
 122     void writebackStores(unsigned tid);
 123
 124     /**
 125      * Squash instructions from a thread until the specified sequence number.
 126      */
 127     void squash(const InstSeqNum &squashed_num, unsigned tid)
 128     { thread[tid].squash(squashed_num); }
 129
 130     /** Returns whether or not there was a memory ordering violation. */
 131     bool violation();
 132     /**
 133      * Returns whether or not there was a memory ordering violation for a
 134      * specific thread.
 135      */
 136     bool violation(unsigned tid)
 137     { return thread[tid].violation(); }
 138
 139     /** Returns if a load is blocked due to the memory system for a specific
 140      *  thread.
 141      */
 142     bool loadBlocked(unsigned tid)
 143     { return thread[tid].loadBlocked(); }
 144
 145     bool isLoadBlockedHandled(unsigned tid)
 146     { return thread[tid].isLoadBlockedHandled(); }
 147
 148     void setLoadBlockedHandled(unsigned tid)
 149     { thread[tid].setLoadBlockedHandled(); }
 150
 151     /** Gets the instruction that caused the memory ordering violation. */
 152     DynInstPtr getMemDepViolator(unsigned tid)
 153     { return thread[tid].getMemDepViolator(); }
 154
 155     /** Returns the head index of the load queue for a specific thread. */
 156     int getLoadHead(unsigned tid)
 157     { return thread[tid].getLoadHead(); }
 158
 159     /** Returns the sequence number of the head of the load queue. */
 160     InstSeqNum getLoadHeadSeqNum(unsigned tid)
 161     {
 162         return thread[tid].getLoadHeadSeqNum();
 163     }
 164
 165     /** Returns the head index of the store queue. */
 166     int getStoreHead(unsigned tid)
 167     { return thread[tid].getStoreHead(); }
 168
 169     /** Returns the sequence number of the head of the store queue. */
 170     InstSeqNum getStoreHeadSeqNum(unsigned tid)
 171     {
 172         return thread[tid].getStoreHeadSeqNum();
 173     }
 174
 175     /** Returns the number of instructions in all of the queues. */
 176     int getCount();
 177     /** Returns the number of instructions in the queues of one thread. */
 178     int getCount(unsigned tid)
 179     { return thread[tid].getCount(); }
 180
 181     /** Returns the total number of loads in the load queue. */
 182     int numLoads();
 183     /** Returns the total number of loads for a single thread. */
 184     int numLoads(unsigned tid)
 185     { return thread[tid].numLoads(); }
 186
 187     /** Returns the total number of stores in the store queue. */
 188     int numStores();
 189     /** Returns the total number of stores for a single thread. */
 190     int numStores(unsigned tid)
 191     { return thread[tid].numStores(); }
 192
 193     /** Returns the total number of loads that are ready. */
 194     int numLoadsReady();
 195     /** Returns the number of loads that are ready for a single thread. */
 196     int numLoadsReady(unsigned tid)
 197     { return thread[tid].numLoadsReady(); }
 198
 199     /** Returns the number of free entries. */
 200     unsigned numFreeEntries();
 201     /** Returns the number of free entries for a specific thread. */
 202     unsigned numFreeEntries(unsigned tid);
 203
 204     /** Returns if the LSQ is full (either LQ or SQ is full). */
 205     bool isFull();
 206     /**
 207      * Returns if the LSQ is full for a specific thread (either LQ or SQ is
 208      * full).
 209      */
 210     bool isFull(unsigned tid);
 211
 212     /** Returns if any of the LQs are full. */
 213     bool lqFull();
 214     /** Returns if the LQ of a given thread is full. */
 215     bool lqFull(unsigned tid);
 216
 217     /** Returns if any of the SQs are full. */
 218     bool sqFull();
 219     /** Returns if the SQ of a given thread is full. */
 220     bool sqFull(unsigned tid);
 221
 222     /**
 223      * Returns if the LSQ is stalled due to a memory operation that must be
 224      * replayed.
 225      */
 226     bool isStalled();
 227     /**
 228      * Returns if the LSQ of a specific thread is stalled due to a memory
 229      * operation that must be replayed.
 230      */
 231     bool isStalled(unsigned tid);
 232
 233     /** Returns whether or not there are any stores to write back to memory. */
 234     bool hasStoresToWB();
 235
 236     /** Returns whether or not a specific thread has any stores to write back
 237      * to memory.
 238      */
 239     bool hasStoresToWB(unsigned tid)
 240     { return thread[tid].hasStoresToWB(); }
 241
 242     /** Returns the number of stores a specific thread has to write back. */
 243     int  numStoresToWB(unsigned tid)
 244     { return thread[tid].numStoresToWB(); }
 245
 246     /** Returns if the LSQ will write back to memory this cycle. */
 247     bool willWB();
 248     /** Returns if the LSQ of a specific thread will write back to memory this
 249      * cycle.
 250      */
 251     bool willWB(unsigned tid)
 252     { return thread[tid].willWB(); }
 253
 254     /** Debugging function to print out all instructions. */
 255     void dumpInsts();
 256     /** Debugging function to print out instructions from a specific thread. */
 257     void dumpInsts(unsigned tid)
 258     { thread[tid].dumpInsts(); }
 259
 260     /** Executes a read operation, using the load specified at the load index. */
 261     template <class T>
 262     Fault read(RequestPtr req, T &data, int load_idx);
 263
 264     /** Executes a store operation, using the store specified at the store
 265      *   index.
 266      */
 267     template <class T>
 268     Fault write(RequestPtr req, T &data, int store_idx);
 269
 270   private:
 271     /** The LSQ policy for SMT mode. */
 272     LSQPolicy lsqPolicy;
 273
 274     /** The LSQ units for individual threads. */
 275     LSQUnit thread[Impl::MaxThreads];
 276
 277     /** The CPU pointer. */
 278     FullCPU *cpu;
 279
 280     /** The IEW stage pointer. */
 281     IEW *iewStage;
 282
 283     /** The pointer to the page table. */
 284 //    PageTable *pTable;
 285
 286     /** List of Active Threads in System. */
 287     std::list<unsigned> *activeThreads;
 288
 289     /** Total Size of LQ Entries. */
 290     unsigned LQEntries;
 291     /** Total Size of SQ Entries. */
 292     unsigned SQEntries;
 293
 294     /** Max LQ Size - Used to Enforce Sharing Policies. */
 295     unsigned maxLQEntries;
 296
 297     /** Max SQ Size - Used to Enforce Sharing Policies. */
 298     unsigned maxSQEntries;
 299
 300     /** Number of Threads. */
 301     unsigned numThreads;
 302 };
 303
 304 template <class Impl>
 305 template <class T>
 306 Fault
 307 LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
 308 {
 309     unsigned tid = req->getThreadNum();
 310
 311     return thread[tid].read(req, data, load_idx);
 312 }
 313
 314 template <class Impl>
 315 template <class T>
 316 Fault
 317 LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
 318 {
 319     unsigned tid = req->getThreadNum();
 320
 321     return thread[tid].write(req, data, store_idx);
 322 }
 323
 324 #endif // __CPU_O3_LSQ_HH__