2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
31 #ifndef __CPU_O3_LSQ_HH__
32 #define __CPU_O3_LSQ_HH__
37 #include "config/full_system.hh"
38 #include "cpu/inst_seq.hh"
39 #include "cpu/o3/lsq_unit.hh"
40 #include "mem/port.hh"
41 #include "sim/sim_object.hh"
46 typedef typename Impl::Params Params;
47 typedef typename Impl::O3CPU O3CPU;
48 typedef typename Impl::DynInstPtr DynInstPtr;
49 typedef typename Impl::CPUPol::IEW IEW;
50 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
59 /** Constructs an LSQ with the given parameters. */
62 /** Returns the name of the LSQ. */
63 std::string name() const;
65 /** Registers statistics of each LSQ unit. */
68 /** Returns dcache port.
69 * @todo: Dcache port needs to be moved up to this level for SMT
70 * to work. For now it just returns the port from one of the
73 Port *getDcachePort() { return &dcachePort; }
75 /** Sets the pointer to the list of active threads. */
76 void setActiveThreads(std::list<unsigned> *at_ptr);
77 /** Sets the CPU pointer. */
78 void setCPU(O3CPU *cpu_ptr);
79 /** Sets the IEW stage pointer. */
80 void setIEW(IEW *iew_ptr);
81 /** Switches out the LSQ. */
83 /** Takes over execution from another CPU's thread. */
86 /** Number of entries needed for the given amount of threads.*/
87 int entryAmount(int num_threads);
88 void removeEntries(unsigned tid);
89 /** Reset the max entries for each thread. */
91 /** Resize the max entries for a thread. */
92 void resizeEntries(unsigned size, unsigned tid);
96 /** Ticks a specific LSQ Unit. */
97 void tick(unsigned tid)
98 { thread[tid].tick(); }
100 /** Inserts a load into the LSQ. */
101 void insertLoad(DynInstPtr &load_inst);
102 /** Inserts a store into the LSQ. */
103 void insertStore(DynInstPtr &store_inst);
105 /** Executes a load. */
106 Fault executeLoad(DynInstPtr &inst);
108 /** Executes a store. */
109 Fault executeStore(DynInstPtr &inst);
112 * Commits loads up until the given sequence number for a specific thread.
114 void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
115 { thread[tid].commitLoads(youngest_inst); }
118 * Commits stores up until the given sequence number for a specific thread.
120 void commitStores(InstSeqNum &youngest_inst, unsigned tid)
121 { thread[tid].commitStores(youngest_inst); }
124 * Attempts to write back stores until all cache ports are used or the
125 * interface becomes blocked.
127 void writebackStores();
128 /** Same as above, but only for one thread. */
129 void writebackStores(unsigned tid);
132 * Squash instructions from a thread until the specified sequence number.
134 void squash(const InstSeqNum &squashed_num, unsigned tid)
135 { thread[tid].squash(squashed_num); }
137 /** Returns whether or not there was a memory ordering violation. */
140 * Returns whether or not there was a memory ordering violation for a
143 bool violation(unsigned tid)
144 { return thread[tid].violation(); }
146 /** Returns if a load is blocked due to the memory system for a specific
149 bool loadBlocked(unsigned tid)
150 { return thread[tid].loadBlocked(); }
152 bool isLoadBlockedHandled(unsigned tid)
153 { return thread[tid].isLoadBlockedHandled(); }
155 void setLoadBlockedHandled(unsigned tid)
156 { thread[tid].setLoadBlockedHandled(); }
158 /** Gets the instruction that caused the memory ordering violation. */
159 DynInstPtr getMemDepViolator(unsigned tid)
160 { return thread[tid].getMemDepViolator(); }
162 /** Returns the head index of the load queue for a specific thread. */
163 int getLoadHead(unsigned tid)
164 { return thread[tid].getLoadHead(); }
166 /** Returns the sequence number of the head of the load queue. */
167 InstSeqNum getLoadHeadSeqNum(unsigned tid)
169 return thread[tid].getLoadHeadSeqNum();
172 /** Returns the head index of the store queue. */
173 int getStoreHead(unsigned tid)
174 { return thread[tid].getStoreHead(); }
176 /** Returns the sequence number of the head of the store queue. */
177 InstSeqNum getStoreHeadSeqNum(unsigned tid)
179 return thread[tid].getStoreHeadSeqNum();
182 /** Returns the number of instructions in all of the queues. */
184 /** Returns the number of instructions in the queues of one thread. */
185 int getCount(unsigned tid)
186 { return thread[tid].getCount(); }
188 /** Returns the total number of loads in the load queue. */
190 /** Returns the total number of loads for a single thread. */
191 int numLoads(unsigned tid)
192 { return thread[tid].numLoads(); }
194 /** Returns the total number of stores in the store queue. */
196 /** Returns the total number of stores for a single thread. */
197 int numStores(unsigned tid)
198 { return thread[tid].numStores(); }
200 /** Returns the total number of loads that are ready. */
202 /** Returns the number of loads that are ready for a single thread. */
203 int numLoadsReady(unsigned tid)
204 { return thread[tid].numLoadsReady(); }
206 /** Returns the number of free entries. */
207 unsigned numFreeEntries();
208 /** Returns the number of free entries for a specific thread. */
209 unsigned numFreeEntries(unsigned tid);
211 /** Returns if the LSQ is full (either LQ or SQ is full). */
214 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
217 bool isFull(unsigned tid);
219 /** Returns if any of the LQs are full. */
221 /** Returns if the LQ of a given thread is full. */
222 bool lqFull(unsigned tid);
224 /** Returns if any of the SQs are full. */
226 /** Returns if the SQ of a given thread is full. */
227 bool sqFull(unsigned tid);
230 * Returns if the LSQ is stalled due to a memory operation that must be
235 * Returns if the LSQ of a specific thread is stalled due to a memory
236 * operation that must be replayed.
238 bool isStalled(unsigned tid);
240 /** Returns whether or not there are any stores to write back to memory. */
241 bool hasStoresToWB();
243 /** Returns whether or not a specific thread has any stores to write back
246 bool hasStoresToWB(unsigned tid)
247 { return thread[tid].hasStoresToWB(); }
249 /** Returns the number of stores a specific thread has to write back. */
250 int numStoresToWB(unsigned tid)
251 { return thread[tid].numStoresToWB(); }
253 /** Returns if the LSQ will write back to memory this cycle. */
255 /** Returns if the LSQ of a specific thread will write back to memory this
258 bool willWB(unsigned tid)
259 { return thread[tid].willWB(); }
261 /** Returns if the cache is currently blocked. */
263 { return retryTid != -1; }
265 /** Sets the retry thread id, indicating that one of the LSQUnits
266 * tried to access the cache but the cache was blocked. */
267 void setRetryTid(int tid)
270 /** Debugging function to print out all instructions. */
272 /** Debugging function to print out instructions from a specific thread. */
273 void dumpInsts(unsigned tid)
274 { thread[tid].dumpInsts(); }
276 /** Executes a read operation, using the load specified at the load index. */
278 Fault read(RequestPtr req, T &data, int load_idx);
280 /** Executes a store operation, using the store specified at the store
284 Fault write(RequestPtr req, T &data, int store_idx);
286 /** DcachePort class for this LSQ. Handles doing the
287 * communication with the cache/memory.
289 class DcachePort : public Port
292 /** Pointer to LSQ. */
296 /** Default constructor. */
297 DcachePort(LSQ *_lsq)
304 /** Atomic version of receive. Panics. */
305 virtual Tick recvAtomic(PacketPtr pkt);
307 /** Functional version of receive. Panics. */
308 virtual void recvFunctional(PacketPtr pkt);
310 /** Receives status change. Other than range changing, panics. */
311 virtual void recvStatusChange(Status status);
313 /** Returns the address ranges of this device. */
314 virtual void getDeviceAddressRanges(AddrRangeList &resp,
315 AddrRangeList &snoop)
316 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
318 /** Timing version of receive. Handles writing back and
319 * completing the load or store that has returned from
321 virtual bool recvTiming(PacketPtr pkt);
323 /** Handles doing a retry of the previous send. */
324 virtual void recvRetry();
328 DcachePort dcachePort;
331 /** The LSQ policy for SMT mode. */
334 /** The LSQ units for individual threads. */
335 LSQUnit thread[Impl::MaxThreads];
337 /** The CPU pointer. */
340 /** The IEW stage pointer. */
343 /** List of Active Threads in System. */
344 std::list<unsigned> *activeThreads;
346 /** Total Size of LQ Entries. */
348 /** Total Size of SQ Entries. */
351 /** Max LQ Size - Used to Enforce Sharing Policies. */
352 unsigned maxLQEntries;
354 /** Max SQ Size - Used to Enforce Sharing Policies. */
355 unsigned maxSQEntries;
357 /** Number of Threads. */
360 /** The thread id of the LSQ Unit that is currently waiting for a
365 template <class Impl>
368 LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
370 unsigned tid = req->getThreadNum();
372 return thread[tid].read(req, data, load_idx);
375 template <class Impl>
378 LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
380 unsigned tid = req->getThreadNum();
382 return thread[tid].write(req, data, store_idx);
385 #endif // __CPU_O3_LSQ_HH__