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32 #ifndef __CPU_O3_LSQ_UNIT_HH__
33 #define __CPU_O3_LSQ_UNIT_HH__
40 #include "arch/generic/debugfaults.hh"
41 #include "arch/isa_traits.hh"
42 #include "arch/locked_mem.hh"
43 #include "arch/mmapped_ipr.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/hashmap.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/inst_seq.hh"
48 #include "cpu/timebuf.hh"
49 #include "debug/LSQUnit.hh"
50 #include "mem/packet.hh"
51 #include "mem/port.hh"
52 #include "sim/fault_fwd.hh"
54 struct DerivO3CPUParams;
57 * Class that implements the actual LQ and SQ for each specific
58 * thread. Both are circular queues; load entries are freed upon
59 * committing, while store entries are freed once they writeback. The
60 * LSQUnit tracks if there are memory ordering violations, and also
61 * detects partial load to store forwarding cases (a store only has
62 * part of a load's data) that requires the load to wait until the
63 * store writes back. In the former case it holds onto the instruction
64 * until the dependence unit looks at it, and in the latter it stalls
65 * the LSQ until the store writes back. At that point the load is
71 typedef typename Impl::O3CPU O3CPU;
72 typedef typename Impl::DynInstPtr DynInstPtr;
73 typedef typename Impl::CPUPol::IEW IEW;
74 typedef typename Impl::CPUPol::LSQ LSQ;
75 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
78 /** Constructs an LSQ unit. init() must be called prior to use. */
81 /** Initializes the LSQ unit with the specified number of entries. */
82 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
83 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
86 /** Returns the name of the LSQ unit. */
87 std::string name() const;
89 /** Registers statistics. */
92 /** Sets the pointer to the dcache port. */
93 void setDcachePort(MasterPort *dcache_port);
95 /** Switches out LSQ unit. */
98 /** Takes over from another CPU's thread. */
101 /** Returns if the LSQ is switched out. */
102 bool isSwitchedOut() { return switchedOut; }
104 /** Ticks the LSQ unit, which in this case only resets the number of
106 * @todo: Move the number of used ports up to the LSQ level so it can
107 * be shared by all LSQ units.
109 void tick() { usedPorts = 0; }
111 /** Inserts an instruction. */
112 void insert(DynInstPtr &inst);
113 /** Inserts a load instruction. */
114 void insertLoad(DynInstPtr &load_inst);
115 /** Inserts a store instruction. */
116 void insertStore(DynInstPtr &store_inst);
118 /** Check for ordering violations in the LSQ. For a store squash if we
119 * ever find a conflicting load. For a load, only squash if we
120 * an external snoop invalidate has been seen for that load address
121 * @param load_idx index to start checking at
122 * @param inst the instruction to check
124 Fault checkViolations(int load_idx, DynInstPtr &inst);
126 /** Check if an incoming invalidate hits in the lsq on a load
127 * that might have issued out of order wrt another load beacuse
128 * of the intermediate invalidate.
130 void checkSnoop(PacketPtr pkt);
132 /** Executes a load instruction. */
133 Fault executeLoad(DynInstPtr &inst);
135 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
136 /** Executes a store instruction. */
137 Fault executeStore(DynInstPtr &inst);
139 /** Commits the head load. */
141 /** Commits loads older than a specific sequence number. */
142 void commitLoads(InstSeqNum &youngest_inst);
144 /** Commits stores older than a specific sequence number. */
145 void commitStores(InstSeqNum &youngest_inst);
147 /** Writes back stores. */
148 void writebackStores();
150 /** Completes the data access that has been returned from the
152 void completeDataAccess(PacketPtr pkt);
154 /** Clears all the entries in the LQ. */
157 /** Clears all the entries in the SQ. */
160 /** Resizes the LQ to a given size. */
161 void resizeLQ(unsigned size);
163 /** Resizes the SQ to a given size. */
164 void resizeSQ(unsigned size);
166 /** Squashes all instructions younger than a specific sequence number. */
167 void squash(const InstSeqNum &squashed_num);
169 /** Returns if there is a memory ordering violation. Value is reset upon
170 * call to getMemDepViolator().
172 bool violation() { return memDepViolator; }
174 /** Returns the memory ordering violator. */
175 DynInstPtr getMemDepViolator();
177 /** Returns if a load became blocked due to the memory system. */
179 { return isLoadBlocked; }
181 /** Clears the signal that a load became blocked. */
182 void clearLoadBlocked()
183 { isLoadBlocked = false; }
185 /** Returns if the blocked load was handled. */
186 bool isLoadBlockedHandled()
187 { return loadBlockedHandled; }
189 /** Records the blocked load as being handled. */
190 void setLoadBlockedHandled()
191 { loadBlockedHandled = true; }
193 /** Returns the number of free entries (min of free LQ and SQ entries). */
194 unsigned numFreeEntries();
196 /** Returns the number of loads ready to execute. */
199 /** Returns the number of loads in the LQ. */
200 int numLoads() { return loads; }
202 /** Returns the number of stores in the SQ. */
203 int numStores() { return stores; }
205 /** Returns if either the LQ or SQ is full. */
206 bool isFull() { return lqFull() || sqFull(); }
208 /** Returns if the LQ is full. */
209 bool lqFull() { return loads >= (LQEntries - 1); }
211 /** Returns if the SQ is full. */
212 bool sqFull() { return stores >= (SQEntries - 1); }
214 /** Returns the number of instructions in the LSQ. */
215 unsigned getCount() { return loads + stores; }
217 /** Returns if there are any stores to writeback. */
218 bool hasStoresToWB() { return storesToWB; }
220 /** Returns the number of stores to writeback. */
221 int numStoresToWB() { return storesToWB; }
223 /** Returns if the LSQ unit will writeback on this cycle. */
224 bool willWB() { return storeQueue[storeWBIdx].canWB &&
225 !storeQueue[storeWBIdx].completed &&
228 /** Handles doing the retry. */
232 /** Writes back the instruction, sending it to IEW. */
233 void writeback(DynInstPtr &inst, PacketPtr pkt);
235 /** Writes back a store that couldn't be completed the previous cycle. */
236 void writebackPendingStore();
238 /** Handles completing the send of a store to memory. */
239 void storePostSend(PacketPtr pkt);
241 /** Completes the store at the specified index. */
242 void completeStore(int store_idx);
244 /** Attempts to send a store to the cache. */
245 bool sendStore(PacketPtr data_pkt);
247 /** Increments the given store index (circular queue). */
248 inline void incrStIdx(int &store_idx);
249 /** Decrements the given store index (circular queue). */
250 inline void decrStIdx(int &store_idx);
251 /** Increments the given load index (circular queue). */
252 inline void incrLdIdx(int &load_idx);
253 /** Decrements the given load index (circular queue). */
254 inline void decrLdIdx(int &load_idx);
257 /** Debugging function to dump instructions in the LSQ. */
261 /** Pointer to the CPU. */
264 /** Pointer to the IEW stage. */
267 /** Pointer to the LSQ. */
270 /** Pointer to the dcache port. Used only for sending. */
271 MasterPort *dcachePort;
273 /** Derived class to hold any sender state the LSQ needs. */
274 class LSQSenderState : public Packet::SenderState, public FastAlloc
277 /** Default constructor. */
279 : noWB(false), isSplit(false), pktToSend(false), outstanding(1),
280 mainPkt(NULL), pendingPacket(NULL)
283 /** Instruction who initiated the access to memory. */
285 /** Whether or not it is a load. */
287 /** The LQ/SQ index of the instruction. */
289 /** Whether or not the instruction will need to writeback. */
291 /** Whether or not this access is split in two. */
293 /** Whether or not there is a packet that needs sending. */
295 /** Number of outstanding packets to complete. */
297 /** The main packet from a split load, used during writeback. */
299 /** A second packet from a split store that needs sending. */
300 PacketPtr pendingPacket;
302 /** Completes a packet and returns whether the access is finished. */
303 inline bool complete() { return --outstanding == 0; }
306 /** Writeback event, specifically for when stores forward data to loads. */
307 class WritebackEvent : public Event {
309 /** Constructs a writeback event. */
310 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
312 /** Processes the writeback event. */
315 /** Returns the description of this event. */
316 const char *description() const;
319 /** Instruction whose results are being written back. */
322 /** The packet that would have been sent to memory. */
325 /** The pointer to the LSQ unit that issued the store. */
326 LSQUnit<Impl> *lsqPtr;
331 /** Constructs an empty store queue entry. */
333 : inst(NULL), req(NULL), size(0),
334 canWB(0), committed(0), completed(0)
336 std::memset(data, 0, sizeof(data));
339 /** Constructs a store queue entry for a given instruction. */
340 SQEntry(DynInstPtr &_inst)
341 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
342 isSplit(0), canWB(0), committed(0), completed(0)
344 std::memset(data, 0, sizeof(data));
347 /** The store instruction. */
349 /** The request for the store. */
351 /** The split requests for the store. */
354 /** The size of the store. */
356 /** The store data. */
358 /** Whether or not the store is split into two requests. */
360 /** Whether or not the store can writeback. */
362 /** Whether or not the store is committed. */
364 /** Whether or not the store is completed. */
369 /** The LSQUnit thread id. */
372 /** The store queue. */
373 std::vector<SQEntry> storeQueue;
375 /** The load queue. */
376 std::vector<DynInstPtr> loadQueue;
378 /** The number of LQ entries, plus a sentinel entry (circular queue).
379 * @todo: Consider having var that records the true number of LQ entries.
382 /** The number of SQ entries, plus a sentinel entry (circular queue).
383 * @todo: Consider having var that records the true number of SQ entries.
387 /** The number of places to shift addresses in the LSQ before checking
388 * for dependency violations
390 unsigned depCheckShift;
392 /** Should loads be checked for dependency issues */
395 /** The number of load instructions in the LQ. */
397 /** The number of store instructions in the SQ. */
399 /** The number of store instructions in the SQ waiting to writeback. */
402 /** The index of the head instruction in the LQ. */
404 /** The index of the tail instruction in the LQ. */
407 /** The index of the head instruction in the SQ. */
409 /** The index of the first instruction that may be ready to be
410 * written back, and has not yet been written back.
413 /** The index of the tail instruction in the SQ. */
416 /// @todo Consider moving to a more advanced model with write vs read ports
417 /** The number of cache ports available each cycle. */
420 /** The number of used cache ports in this cycle. */
423 /** Is the LSQ switched out. */
426 //list<InstSeqNum> mshrSeqNums;
428 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
431 /** Wire to read information from the issue stage time queue. */
432 typename TimeBuffer<IssueStruct>::wire fromIssue;
434 /** Whether or not the LSQ is stalled. */
436 /** The store that causes the stall due to partial store to load
439 InstSeqNum stallingStoreIsn;
440 /** The index of the above store. */
443 /** The packet that needs to be retried. */
446 /** Whehter or not a store is blocked due to the memory system. */
449 /** Whether or not a load is blocked due to the memory system. */
452 /** Has the blocked load been handled. */
453 bool loadBlockedHandled;
455 /** Whether or not a store is in flight. */
458 /** The sequence number of the blocked load. */
459 InstSeqNum blockedLoadSeqNum;
461 /** The oldest load that caused a memory ordering violation. */
462 DynInstPtr memDepViolator;
464 /** Whether or not there is a packet that couldn't be sent because of
465 * a lack of cache ports. */
468 /** The packet that is pending free cache ports. */
469 PacketPtr pendingPkt;
471 /** Flag for memory model. */
474 // Will also need how many read/write ports the Dcache has. Or keep track
475 // of that in stage that is one level up, and only call executeLoad/Store
476 // the appropriate number of times.
477 /** Total number of loads forwaded from LSQ stores. */
478 Stats::Scalar lsqForwLoads;
480 /** Total number of loads ignored due to invalid addresses. */
481 Stats::Scalar invAddrLoads;
483 /** Total number of squashed loads. */
484 Stats::Scalar lsqSquashedLoads;
486 /** Total number of responses from the memory system that are
487 * ignored due to the instruction already being squashed. */
488 Stats::Scalar lsqIgnoredResponses;
490 /** Tota number of memory ordering violations. */
491 Stats::Scalar lsqMemOrderViolation;
493 /** Total number of squashed stores. */
494 Stats::Scalar lsqSquashedStores;
496 /** Total number of software prefetches ignored due to invalid addresses. */
497 Stats::Scalar invAddrSwpfs;
499 /** Ready loads blocked due to partial store-forwarding. */
500 Stats::Scalar lsqBlockedLoads;
502 /** Number of loads that were rescheduled. */
503 Stats::Scalar lsqRescheduledLoads;
505 /** Number of times the LSQ is blocked due to the cache. */
506 Stats::Scalar lsqCacheBlocked;
509 /** Executes the load at the given index. */
510 Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
511 uint8_t *data, int load_idx);
513 /** Executes the store at the given index. */
514 Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
515 uint8_t *data, int store_idx);
517 /** Returns the index of the head load instruction. */
518 int getLoadHead() { return loadHead; }
519 /** Returns the sequence number of the head load instruction. */
520 InstSeqNum getLoadHeadSeqNum()
522 if (loadQueue[loadHead]) {
523 return loadQueue[loadHead]->seqNum;
530 /** Returns the index of the head store instruction. */
531 int getStoreHead() { return storeHead; }
532 /** Returns the sequence number of the head store instruction. */
533 InstSeqNum getStoreHeadSeqNum()
535 if (storeQueue[storeHead].inst) {
536 return storeQueue[storeHead].inst->seqNum;
543 /** Returns whether or not the LSQ unit is stalled. */
544 bool isStalled() { return stalled; }
547 template <class Impl>
549 LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
550 uint8_t *data, int load_idx)
552 DynInstPtr load_inst = loadQueue[load_idx];
556 assert(!load_inst->isExecuted());
558 // Make sure this isn't an uncacheable access
559 // A bit of a hackish way to get uncached accesses to work only if they're
560 // at the head of the LSQ and are ready to commit (at the head of the ROB
562 if (req->isUncacheable() &&
563 (load_idx != loadHead || !load_inst->isAtCommit())) {
564 iewStage->rescheduleMemInst(load_inst);
565 ++lsqRescheduledLoads;
566 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
567 load_inst->seqNum, load_inst->pcState());
569 // Must delete request now that it wasn't handed off to
570 // memory. This is quite ugly. @todo: Figure out the proper
571 // place to really handle request deletes.
573 if (TheISA::HasUnalignedMemAcc && sreqLow) {
577 return new GenericISA::M5PanicFault(
578 "Uncachable load [sn:%llx] PC %s\n",
579 load_inst->seqNum, load_inst->pcState());
582 // Check the SQ for any previous stores that might lead to forwarding
583 int store_idx = load_inst->sqIdx;
587 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
588 "storeHead: %i addr: %#x%s\n",
589 load_idx, store_idx, storeHead, req->getPaddr(),
590 sreqLow ? " split" : "");
594 // Disable recording the result temporarily. Writing to misc
595 // regs normally updates the result, but this is not the
596 // desired behavior when handling store conditionals.
597 load_inst->recordResult = false;
598 TheISA::handleLockedRead(load_inst.get(), req);
599 load_inst->recordResult = true;
602 if (req->isMmappedIpr()) {
603 assert(!load_inst->memData);
604 load_inst->memData = new uint8_t[64];
606 ThreadContext *thread = cpu->tcBase(lsqID);
609 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
611 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
612 data_pkt->dataStatic(load_inst->memData);
613 delay = TheISA::handleIprRead(thread, data_pkt);
615 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
616 PacketPtr fst_data_pkt =
617 new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
618 PacketPtr snd_data_pkt =
619 new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
621 fst_data_pkt->dataStatic(load_inst->memData);
622 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
624 delay = TheISA::handleIprRead(thread, fst_data_pkt);
625 unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
634 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
635 cpu->schedule(wb, curTick() + delay);
639 while (store_idx != -1) {
640 // End once we've reached the top of the LSQ
641 if (store_idx == storeWBIdx) {
645 // Move the index to one younger
647 store_idx += SQEntries;
649 assert(storeQueue[store_idx].inst);
651 store_size = storeQueue[store_idx].size;
655 else if (storeQueue[store_idx].inst->uncacheable())
658 assert(storeQueue[store_idx].inst->effAddrValid);
660 // Check if the store data is within the lower and upper bounds of
661 // addresses that the request needs.
662 bool store_has_lower_limit =
663 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
664 bool store_has_upper_limit =
665 (req->getVaddr() + req->getSize()) <=
666 (storeQueue[store_idx].inst->effAddr + store_size);
667 bool lower_load_has_store_part =
668 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
670 bool upper_load_has_store_part =
671 (req->getVaddr() + req->getSize()) >
672 storeQueue[store_idx].inst->effAddr;
674 // If the store's data has all of the data needed, we can forward.
675 if ((store_has_lower_limit && store_has_upper_limit)) {
676 // Get shift amount for offset into the store's data.
677 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
679 memcpy(data, storeQueue[store_idx].data + shift_amt,
682 assert(!load_inst->memData);
683 load_inst->memData = new uint8_t[64];
685 memcpy(load_inst->memData,
686 storeQueue[store_idx].data + shift_amt, req->getSize());
688 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
689 "addr %#x, data %#x\n",
690 store_idx, req->getVaddr(), data);
692 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
694 data_pkt->dataStatic(load_inst->memData);
696 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
698 // We'll say this has a 1 cycle load-store forwarding latency
700 // @todo: Need to make this a parameter.
701 cpu->schedule(wb, curTick());
703 // Don't need to do anything special for split loads.
704 if (TheISA::HasUnalignedMemAcc && sreqLow) {
711 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
712 (store_has_upper_limit && upper_load_has_store_part) ||
713 (lower_load_has_store_part && upper_load_has_store_part)) {
714 // This is the partial store-load forwarding case where a store
715 // has only part of the load's data.
717 // If it's already been written back, then don't worry about
719 if (storeQueue[store_idx].completed) {
720 panic("Should not check one of these");
724 // Must stall load and force it to retry, so long as it's the oldest
725 // load that needs to do so.
729 loadQueue[stallingLoadIdx]->seqNum)) {
731 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
732 stallingLoadIdx = load_idx;
735 // Tell IQ/mem dep unit that this instruction will need to be
736 // rescheduled eventually
737 iewStage->rescheduleMemInst(load_inst);
738 iewStage->decrWb(load_inst->seqNum);
739 load_inst->clearIssued();
740 ++lsqRescheduledLoads;
742 // Do not generate a writeback event as this instruction is not
744 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
745 "Store idx %i to load addr %#x\n",
746 store_idx, req->getVaddr());
748 // Must delete request now that it wasn't handed off to
749 // memory. This is quite ugly. @todo: Figure out the
750 // proper place to really handle request deletes.
752 if (TheISA::HasUnalignedMemAcc && sreqLow) {
761 // If there's no forwarding case, then go access memory
762 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
763 load_inst->seqNum, load_inst->pcState());
765 assert(!load_inst->memData);
766 load_inst->memData = new uint8_t[64];
770 // if we the cache is not blocked, do cache access
771 bool completedFirst = false;
772 if (!lsq->cacheBlocked()) {
774 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
775 PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
776 PacketPtr fst_data_pkt = NULL;
777 PacketPtr snd_data_pkt = NULL;
779 data_pkt->dataStatic(load_inst->memData);
781 LSQSenderState *state = new LSQSenderState;
782 state->isLoad = true;
783 state->idx = load_idx;
784 state->inst = load_inst;
785 data_pkt->senderState = state;
787 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
789 // Point the first packet at the main data packet.
790 fst_data_pkt = data_pkt;
793 // Create the split packets.
794 fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
795 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
797 fst_data_pkt->dataStatic(load_inst->memData);
798 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
800 fst_data_pkt->senderState = state;
801 snd_data_pkt->senderState = state;
803 state->isSplit = true;
804 state->outstanding = 2;
805 state->mainPkt = data_pkt;
808 if (!dcachePort->sendTiming(fst_data_pkt)) {
809 // Delete state and data packet because a load retry
810 // initiates a pipeline restart; it does not retry.
812 delete data_pkt->req;
814 if (TheISA::HasUnalignedMemAcc && sreqLow) {
815 delete fst_data_pkt->req;
817 delete snd_data_pkt->req;
825 // If the access didn't succeed, tell the LSQ by setting
826 // the retry thread id.
827 lsq->setRetryTid(lsqID);
828 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
829 completedFirst = true;
831 // The first packet was sent without problems, so send this one
832 // too. If there is a problem with this packet then the whole
833 // load will be squashed, so indicate this to the state object.
834 // The first packet will return in completeDataAccess and be
837 if (!dcachePort->sendTiming(snd_data_pkt)) {
839 // The main packet will be deleted in completeDataAccess.
840 delete snd_data_pkt->req;
848 lsq->setRetryTid(lsqID);
853 // If the cache was blocked, or has become blocked due to the access,
855 if (lsq->cacheBlocked()) {
858 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) {
865 // If the first part of a split access succeeds, then let the LSQ
866 // handle the decrWb when completeDataAccess is called upon return
867 // of the requested first part of data
869 iewStage->decrWb(load_inst->seqNum);
871 // There's an older load that's already going to squash.
872 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
875 // Record that the load was blocked due to memory. This
876 // load will squash all instructions after it, be
877 // refetched, and re-executed.
878 isLoadBlocked = true;
879 loadBlockedHandled = false;
880 blockedLoadSeqNum = load_inst->seqNum;
881 // No fault occurred, even though the interface is blocked.
888 template <class Impl>
890 LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
891 uint8_t *data, int store_idx)
893 assert(storeQueue[store_idx].inst);
895 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
896 " | storeHead:%i [sn:%i]\n",
897 store_idx, req->getPaddr(), data, storeHead,
898 storeQueue[store_idx].inst->seqNum);
900 storeQueue[store_idx].req = req;
901 storeQueue[store_idx].sreqLow = sreqLow;
902 storeQueue[store_idx].sreqHigh = sreqHigh;
903 unsigned size = req->getSize();
904 storeQueue[store_idx].size = size;
905 assert(size <= sizeof(storeQueue[store_idx].data));
907 // Split stores can only occur in ISAs with unaligned memory accesses. If
908 // a store request has been split, sreqLow and sreqHigh will be non-null.
909 if (TheISA::HasUnalignedMemAcc && sreqLow) {
910 storeQueue[store_idx].isSplit = true;
913 memcpy(storeQueue[store_idx].data, data, size);
915 // This function only writes the data to the store queue, so no fault
920 #endif // __CPU_O3_LSQ_UNIT_HH__