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32 #ifndef __CPU_O3_LSQ_UNIT_HH__
33 #define __CPU_O3_LSQ_UNIT_HH__
40 #include "arch/generic/debugfaults.hh"
41 #include "arch/isa_traits.hh"
42 #include "arch/locked_mem.hh"
43 #include "arch/mmapped_ipr.hh"
44 #include "base/hashmap.hh"
45 #include "config/the_isa.hh"
46 #include "cpu/inst_seq.hh"
47 #include "cpu/timebuf.hh"
48 #include "debug/LSQUnit.hh"
49 #include "mem/packet.hh"
50 #include "mem/port.hh"
51 #include "sim/fault_fwd.hh"
53 struct DerivO3CPUParams;
56 * Class that implements the actual LQ and SQ for each specific
57 * thread. Both are circular queues; load entries are freed upon
58 * committing, while store entries are freed once they writeback. The
59 * LSQUnit tracks if there are memory ordering violations, and also
60 * detects partial load to store forwarding cases (a store only has
61 * part of a load's data) that requires the load to wait until the
62 * store writes back. In the former case it holds onto the instruction
63 * until the dependence unit looks at it, and in the latter it stalls
64 * the LSQ until the store writes back. At that point the load is
70 typedef typename Impl::O3CPU O3CPU;
71 typedef typename Impl::DynInstPtr DynInstPtr;
72 typedef typename Impl::CPUPol::IEW IEW;
73 typedef typename Impl::CPUPol::LSQ LSQ;
74 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
77 /** Constructs an LSQ unit. init() must be called prior to use. */
80 /** Initializes the LSQ unit with the specified number of entries. */
81 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
82 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
85 /** Returns the name of the LSQ unit. */
86 std::string name() const;
88 /** Registers statistics. */
91 /** Sets the pointer to the dcache port. */
92 void setDcachePort(MasterPort *dcache_port);
94 /** Switches out LSQ unit. */
97 /** Takes over from another CPU's thread. */
100 /** Returns if the LSQ is switched out. */
101 bool isSwitchedOut() { return switchedOut; }
103 /** Ticks the LSQ unit, which in this case only resets the number of
105 * @todo: Move the number of used ports up to the LSQ level so it can
106 * be shared by all LSQ units.
108 void tick() { usedPorts = 0; }
110 /** Inserts an instruction. */
111 void insert(DynInstPtr &inst);
112 /** Inserts a load instruction. */
113 void insertLoad(DynInstPtr &load_inst);
114 /** Inserts a store instruction. */
115 void insertStore(DynInstPtr &store_inst);
117 /** Check for ordering violations in the LSQ. For a store squash if we
118 * ever find a conflicting load. For a load, only squash if we
119 * an external snoop invalidate has been seen for that load address
120 * @param load_idx index to start checking at
121 * @param inst the instruction to check
123 Fault checkViolations(int load_idx, DynInstPtr &inst);
125 /** Check if an incoming invalidate hits in the lsq on a load
126 * that might have issued out of order wrt another load beacuse
127 * of the intermediate invalidate.
129 void checkSnoop(PacketPtr pkt);
131 /** Executes a load instruction. */
132 Fault executeLoad(DynInstPtr &inst);
134 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
135 /** Executes a store instruction. */
136 Fault executeStore(DynInstPtr &inst);
138 /** Commits the head load. */
140 /** Commits loads older than a specific sequence number. */
141 void commitLoads(InstSeqNum &youngest_inst);
143 /** Commits stores older than a specific sequence number. */
144 void commitStores(InstSeqNum &youngest_inst);
146 /** Writes back stores. */
147 void writebackStores();
149 /** Completes the data access that has been returned from the
151 void completeDataAccess(PacketPtr pkt);
153 /** Clears all the entries in the LQ. */
156 /** Clears all the entries in the SQ. */
159 /** Resizes the LQ to a given size. */
160 void resizeLQ(unsigned size);
162 /** Resizes the SQ to a given size. */
163 void resizeSQ(unsigned size);
165 /** Squashes all instructions younger than a specific sequence number. */
166 void squash(const InstSeqNum &squashed_num);
168 /** Returns if there is a memory ordering violation. Value is reset upon
169 * call to getMemDepViolator().
171 bool violation() { return memDepViolator; }
173 /** Returns the memory ordering violator. */
174 DynInstPtr getMemDepViolator();
176 /** Returns if a load became blocked due to the memory system. */
178 { return isLoadBlocked; }
180 /** Clears the signal that a load became blocked. */
181 void clearLoadBlocked()
182 { isLoadBlocked = false; }
184 /** Returns if the blocked load was handled. */
185 bool isLoadBlockedHandled()
186 { return loadBlockedHandled; }
188 /** Records the blocked load as being handled. */
189 void setLoadBlockedHandled()
190 { loadBlockedHandled = true; }
192 /** Returns the number of free entries (min of free LQ and SQ entries). */
193 unsigned numFreeEntries();
195 /** Returns the number of loads ready to execute. */
198 /** Returns the number of loads in the LQ. */
199 int numLoads() { return loads; }
201 /** Returns the number of stores in the SQ. */
202 int numStores() { return stores; }
204 /** Returns if either the LQ or SQ is full. */
205 bool isFull() { return lqFull() || sqFull(); }
207 /** Returns if the LQ is full. */
208 bool lqFull() { return loads >= (LQEntries - 1); }
210 /** Returns if the SQ is full. */
211 bool sqFull() { return stores >= (SQEntries - 1); }
213 /** Returns the number of instructions in the LSQ. */
214 unsigned getCount() { return loads + stores; }
216 /** Returns if there are any stores to writeback. */
217 bool hasStoresToWB() { return storesToWB; }
219 /** Returns the number of stores to writeback. */
220 int numStoresToWB() { return storesToWB; }
222 /** Returns if the LSQ unit will writeback on this cycle. */
223 bool willWB() { return storeQueue[storeWBIdx].canWB &&
224 !storeQueue[storeWBIdx].completed &&
227 /** Handles doing the retry. */
231 /** Writes back the instruction, sending it to IEW. */
232 void writeback(DynInstPtr &inst, PacketPtr pkt);
234 /** Writes back a store that couldn't be completed the previous cycle. */
235 void writebackPendingStore();
237 /** Handles completing the send of a store to memory. */
238 void storePostSend(PacketPtr pkt);
240 /** Completes the store at the specified index. */
241 void completeStore(int store_idx);
243 /** Attempts to send a store to the cache. */
244 bool sendStore(PacketPtr data_pkt);
246 /** Increments the given store index (circular queue). */
247 inline void incrStIdx(int &store_idx);
248 /** Decrements the given store index (circular queue). */
249 inline void decrStIdx(int &store_idx);
250 /** Increments the given load index (circular queue). */
251 inline void incrLdIdx(int &load_idx);
252 /** Decrements the given load index (circular queue). */
253 inline void decrLdIdx(int &load_idx);
256 /** Debugging function to dump instructions in the LSQ. */
260 /** Pointer to the CPU. */
263 /** Pointer to the IEW stage. */
266 /** Pointer to the LSQ. */
269 /** Pointer to the dcache port. Used only for sending. */
270 MasterPort *dcachePort;
272 /** Derived class to hold any sender state the LSQ needs. */
273 class LSQSenderState : public Packet::SenderState
276 /** Default constructor. */
278 : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
279 noWB(false), isSplit(false), pktToSend(false)
282 /** Instruction who initiated the access to memory. */
284 /** The main packet from a split load, used during writeback. */
286 /** A second packet from a split store that needs sending. */
287 PacketPtr pendingPacket;
288 /** The LQ/SQ index of the instruction. */
290 /** Number of outstanding packets to complete. */
292 /** Whether or not it is a load. */
294 /** Whether or not the instruction will need to writeback. */
296 /** Whether or not this access is split in two. */
298 /** Whether or not there is a packet that needs sending. */
301 /** Completes a packet and returns whether the access is finished. */
302 inline bool complete() { return --outstanding == 0; }
305 /** Writeback event, specifically for when stores forward data to loads. */
306 class WritebackEvent : public Event {
308 /** Constructs a writeback event. */
309 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
311 /** Processes the writeback event. */
314 /** Returns the description of this event. */
315 const char *description() const;
318 /** Instruction whose results are being written back. */
321 /** The packet that would have been sent to memory. */
324 /** The pointer to the LSQ unit that issued the store. */
325 LSQUnit<Impl> *lsqPtr;
330 /** Constructs an empty store queue entry. */
332 : inst(NULL), req(NULL), size(0),
333 canWB(0), committed(0), completed(0)
335 std::memset(data, 0, sizeof(data));
343 /** Constructs a store queue entry for a given instruction. */
344 SQEntry(DynInstPtr &_inst)
345 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
346 isSplit(0), canWB(0), committed(0), completed(0)
348 std::memset(data, 0, sizeof(data));
350 /** The store data. */
352 /** The store instruction. */
354 /** The request for the store. */
356 /** The split requests for the store. */
359 /** The size of the store. */
361 /** Whether or not the store is split into two requests. */
363 /** Whether or not the store can writeback. */
365 /** Whether or not the store is committed. */
367 /** Whether or not the store is completed. */
372 /** The LSQUnit thread id. */
375 /** The store queue. */
376 std::vector<SQEntry> storeQueue;
378 /** The load queue. */
379 std::vector<DynInstPtr> loadQueue;
381 /** The number of LQ entries, plus a sentinel entry (circular queue).
382 * @todo: Consider having var that records the true number of LQ entries.
385 /** The number of SQ entries, plus a sentinel entry (circular queue).
386 * @todo: Consider having var that records the true number of SQ entries.
390 /** The number of places to shift addresses in the LSQ before checking
391 * for dependency violations
393 unsigned depCheckShift;
395 /** Should loads be checked for dependency issues */
398 /** The number of load instructions in the LQ. */
400 /** The number of store instructions in the SQ. */
402 /** The number of store instructions in the SQ waiting to writeback. */
405 /** The index of the head instruction in the LQ. */
407 /** The index of the tail instruction in the LQ. */
410 /** The index of the head instruction in the SQ. */
412 /** The index of the first instruction that may be ready to be
413 * written back, and has not yet been written back.
416 /** The index of the tail instruction in the SQ. */
419 /// @todo Consider moving to a more advanced model with write vs read ports
420 /** The number of cache ports available each cycle. */
423 /** The number of used cache ports in this cycle. */
426 /** Is the LSQ switched out. */
429 //list<InstSeqNum> mshrSeqNums;
431 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
434 /** Wire to read information from the issue stage time queue. */
435 typename TimeBuffer<IssueStruct>::wire fromIssue;
437 /** Whether or not the LSQ is stalled. */
439 /** The store that causes the stall due to partial store to load
442 InstSeqNum stallingStoreIsn;
443 /** The index of the above store. */
446 /** The packet that needs to be retried. */
449 /** Whehter or not a store is blocked due to the memory system. */
452 /** Whether or not a load is blocked due to the memory system. */
455 /** Has the blocked load been handled. */
456 bool loadBlockedHandled;
458 /** Whether or not a store is in flight. */
461 /** The sequence number of the blocked load. */
462 InstSeqNum blockedLoadSeqNum;
464 /** The oldest load that caused a memory ordering violation. */
465 DynInstPtr memDepViolator;
467 /** Whether or not there is a packet that couldn't be sent because of
468 * a lack of cache ports. */
471 /** The packet that is pending free cache ports. */
472 PacketPtr pendingPkt;
474 /** Flag for memory model. */
477 // Will also need how many read/write ports the Dcache has. Or keep track
478 // of that in stage that is one level up, and only call executeLoad/Store
479 // the appropriate number of times.
480 /** Total number of loads forwaded from LSQ stores. */
481 Stats::Scalar lsqForwLoads;
483 /** Total number of loads ignored due to invalid addresses. */
484 Stats::Scalar invAddrLoads;
486 /** Total number of squashed loads. */
487 Stats::Scalar lsqSquashedLoads;
489 /** Total number of responses from the memory system that are
490 * ignored due to the instruction already being squashed. */
491 Stats::Scalar lsqIgnoredResponses;
493 /** Tota number of memory ordering violations. */
494 Stats::Scalar lsqMemOrderViolation;
496 /** Total number of squashed stores. */
497 Stats::Scalar lsqSquashedStores;
499 /** Total number of software prefetches ignored due to invalid addresses. */
500 Stats::Scalar invAddrSwpfs;
502 /** Ready loads blocked due to partial store-forwarding. */
503 Stats::Scalar lsqBlockedLoads;
505 /** Number of loads that were rescheduled. */
506 Stats::Scalar lsqRescheduledLoads;
508 /** Number of times the LSQ is blocked due to the cache. */
509 Stats::Scalar lsqCacheBlocked;
512 /** Executes the load at the given index. */
513 Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
514 uint8_t *data, int load_idx);
516 /** Executes the store at the given index. */
517 Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
518 uint8_t *data, int store_idx);
520 /** Returns the index of the head load instruction. */
521 int getLoadHead() { return loadHead; }
522 /** Returns the sequence number of the head load instruction. */
523 InstSeqNum getLoadHeadSeqNum()
525 if (loadQueue[loadHead]) {
526 return loadQueue[loadHead]->seqNum;
533 /** Returns the index of the head store instruction. */
534 int getStoreHead() { return storeHead; }
535 /** Returns the sequence number of the head store instruction. */
536 InstSeqNum getStoreHeadSeqNum()
538 if (storeQueue[storeHead].inst) {
539 return storeQueue[storeHead].inst->seqNum;
546 /** Returns whether or not the LSQ unit is stalled. */
547 bool isStalled() { return stalled; }
550 template <class Impl>
552 LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
553 uint8_t *data, int load_idx)
555 DynInstPtr load_inst = loadQueue[load_idx];
559 assert(!load_inst->isExecuted());
561 // Make sure this isn't an uncacheable access
562 // A bit of a hackish way to get uncached accesses to work only if they're
563 // at the head of the LSQ and are ready to commit (at the head of the ROB
565 if (req->isUncacheable() &&
566 (load_idx != loadHead || !load_inst->isAtCommit())) {
567 iewStage->rescheduleMemInst(load_inst);
568 ++lsqRescheduledLoads;
569 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
570 load_inst->seqNum, load_inst->pcState());
572 // Must delete request now that it wasn't handed off to
573 // memory. This is quite ugly. @todo: Figure out the proper
574 // place to really handle request deletes.
576 if (TheISA::HasUnalignedMemAcc && sreqLow) {
580 return new GenericISA::M5PanicFault(
581 "Uncachable load [sn:%llx] PC %s\n",
582 load_inst->seqNum, load_inst->pcState());
585 // Check the SQ for any previous stores that might lead to forwarding
586 int store_idx = load_inst->sqIdx;
590 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
591 "storeHead: %i addr: %#x%s\n",
592 load_idx, store_idx, storeHead, req->getPaddr(),
593 sreqLow ? " split" : "");
597 // Disable recording the result temporarily. Writing to misc
598 // regs normally updates the result, but this is not the
599 // desired behavior when handling store conditionals.
600 load_inst->recordResult(false);
601 TheISA::handleLockedRead(load_inst.get(), req);
602 load_inst->recordResult(true);
605 if (req->isMmappedIpr()) {
606 assert(!load_inst->memData);
607 load_inst->memData = new uint8_t[64];
609 ThreadContext *thread = cpu->tcBase(lsqID);
611 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
613 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
614 data_pkt->dataStatic(load_inst->memData);
615 delay = TheISA::handleIprRead(thread, data_pkt);
617 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
618 PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
619 PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
621 fst_data_pkt->dataStatic(load_inst->memData);
622 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
624 delay = TheISA::handleIprRead(thread, fst_data_pkt);
625 unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
634 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
635 cpu->schedule(wb, curTick() + delay);
639 while (store_idx != -1) {
640 // End once we've reached the top of the LSQ
641 if (store_idx == storeWBIdx) {
645 // Move the index to one younger
647 store_idx += SQEntries;
649 assert(storeQueue[store_idx].inst);
651 store_size = storeQueue[store_idx].size;
655 else if (storeQueue[store_idx].inst->uncacheable())
658 assert(storeQueue[store_idx].inst->effAddrValid());
660 // Check if the store data is within the lower and upper bounds of
661 // addresses that the request needs.
662 bool store_has_lower_limit =
663 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
664 bool store_has_upper_limit =
665 (req->getVaddr() + req->getSize()) <=
666 (storeQueue[store_idx].inst->effAddr + store_size);
667 bool lower_load_has_store_part =
668 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
670 bool upper_load_has_store_part =
671 (req->getVaddr() + req->getSize()) >
672 storeQueue[store_idx].inst->effAddr;
674 // If the store's data has all of the data needed, we can forward.
675 if ((store_has_lower_limit && store_has_upper_limit)) {
676 // Get shift amount for offset into the store's data.
677 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
679 memcpy(data, storeQueue[store_idx].data + shift_amt,
682 assert(!load_inst->memData);
683 load_inst->memData = new uint8_t[64];
685 memcpy(load_inst->memData,
686 storeQueue[store_idx].data + shift_amt, req->getSize());
688 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
689 "addr %#x, data %#x\n",
690 store_idx, req->getVaddr(), data);
692 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
693 data_pkt->dataStatic(load_inst->memData);
695 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
697 // We'll say this has a 1 cycle load-store forwarding latency
699 // @todo: Need to make this a parameter.
700 cpu->schedule(wb, curTick());
702 // Don't need to do anything special for split loads.
703 if (TheISA::HasUnalignedMemAcc && sreqLow) {
710 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
711 (store_has_upper_limit && upper_load_has_store_part) ||
712 (lower_load_has_store_part && upper_load_has_store_part)) {
713 // This is the partial store-load forwarding case where a store
714 // has only part of the load's data.
716 // If it's already been written back, then don't worry about
718 if (storeQueue[store_idx].completed) {
719 panic("Should not check one of these");
723 // Must stall load and force it to retry, so long as it's the oldest
724 // load that needs to do so.
728 loadQueue[stallingLoadIdx]->seqNum)) {
730 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
731 stallingLoadIdx = load_idx;
734 // Tell IQ/mem dep unit that this instruction will need to be
735 // rescheduled eventually
736 iewStage->rescheduleMemInst(load_inst);
737 iewStage->decrWb(load_inst->seqNum);
738 load_inst->clearIssued();
739 ++lsqRescheduledLoads;
741 // Do not generate a writeback event as this instruction is not
743 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
744 "Store idx %i to load addr %#x\n",
745 store_idx, req->getVaddr());
747 // Must delete request now that it wasn't handed off to
748 // memory. This is quite ugly. @todo: Figure out the
749 // proper place to really handle request deletes.
751 if (TheISA::HasUnalignedMemAcc && sreqLow) {
760 // If there's no forwarding case, then go access memory
761 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
762 load_inst->seqNum, load_inst->pcState());
764 assert(!load_inst->memData);
765 load_inst->memData = new uint8_t[64];
769 // if we the cache is not blocked, do cache access
770 bool completedFirst = false;
771 if (!lsq->cacheBlocked()) {
773 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
774 PacketPtr data_pkt = new Packet(req, command);
775 PacketPtr fst_data_pkt = NULL;
776 PacketPtr snd_data_pkt = NULL;
778 data_pkt->dataStatic(load_inst->memData);
780 LSQSenderState *state = new LSQSenderState;
781 state->isLoad = true;
782 state->idx = load_idx;
783 state->inst = load_inst;
784 data_pkt->senderState = state;
786 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
788 // Point the first packet at the main data packet.
789 fst_data_pkt = data_pkt;
792 // Create the split packets.
793 fst_data_pkt = new Packet(sreqLow, command);
794 snd_data_pkt = new Packet(sreqHigh, command);
796 fst_data_pkt->dataStatic(load_inst->memData);
797 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
799 fst_data_pkt->senderState = state;
800 snd_data_pkt->senderState = state;
802 state->isSplit = true;
803 state->outstanding = 2;
804 state->mainPkt = data_pkt;
807 if (!dcachePort->sendTimingReq(fst_data_pkt)) {
808 // Delete state and data packet because a load retry
809 // initiates a pipeline restart; it does not retry.
811 delete data_pkt->req;
813 if (TheISA::HasUnalignedMemAcc && sreqLow) {
814 delete fst_data_pkt->req;
816 delete snd_data_pkt->req;
824 // If the access didn't succeed, tell the LSQ by setting
825 // the retry thread id.
826 lsq->setRetryTid(lsqID);
827 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
828 completedFirst = true;
830 // The first packet was sent without problems, so send this one
831 // too. If there is a problem with this packet then the whole
832 // load will be squashed, so indicate this to the state object.
833 // The first packet will return in completeDataAccess and be
836 if (!dcachePort->sendTimingReq(snd_data_pkt)) {
838 // The main packet will be deleted in completeDataAccess.
839 delete snd_data_pkt->req;
847 lsq->setRetryTid(lsqID);
852 // If the cache was blocked, or has become blocked due to the access,
854 if (lsq->cacheBlocked()) {
857 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) {
864 // If the first part of a split access succeeds, then let the LSQ
865 // handle the decrWb when completeDataAccess is called upon return
866 // of the requested first part of data
868 iewStage->decrWb(load_inst->seqNum);
870 // There's an older load that's already going to squash.
871 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
874 // Record that the load was blocked due to memory. This
875 // load will squash all instructions after it, be
876 // refetched, and re-executed.
877 isLoadBlocked = true;
878 loadBlockedHandled = false;
879 blockedLoadSeqNum = load_inst->seqNum;
880 // No fault occurred, even though the interface is blocked.
887 template <class Impl>
889 LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
890 uint8_t *data, int store_idx)
892 assert(storeQueue[store_idx].inst);
894 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
895 " | storeHead:%i [sn:%i]\n",
896 store_idx, req->getPaddr(), data, storeHead,
897 storeQueue[store_idx].inst->seqNum);
899 storeQueue[store_idx].req = req;
900 storeQueue[store_idx].sreqLow = sreqLow;
901 storeQueue[store_idx].sreqHigh = sreqHigh;
902 unsigned size = req->getSize();
903 storeQueue[store_idx].size = size;
904 assert(size <= sizeof(storeQueue[store_idx].data));
906 // Split stores can only occur in ISAs with unaligned memory accesses. If
907 // a store request has been split, sreqLow and sreqHigh will be non-null.
908 if (TheISA::HasUnalignedMemAcc && sreqLow) {
909 storeQueue[store_idx].isSplit = true;
912 memcpy(storeQueue[store_idx].data, data, size);
914 // This function only writes the data to the store queue, so no fault
919 #endif // __CPU_O3_LSQ_UNIT_HH__