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32 #ifndef __CPU_O3_LSQ_UNIT_HH__
33 #define __CPU_O3_LSQ_UNIT_HH__
40 #include "arch/faults.hh"
41 #include "arch/locked_mem.hh"
42 #include "config/full_system.hh"
43 #include "config/the_isa.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/hashmap.hh"
46 #include "cpu/inst_seq.hh"
47 #include "mem/packet.hh"
48 #include "mem/port.hh"
50 class DerivO3CPUParams;
53 * Class that implements the actual LQ and SQ for each specific
54 * thread. Both are circular queues; load entries are freed upon
55 * committing, while store entries are freed once they writeback. The
56 * LSQUnit tracks if there are memory ordering violations, and also
57 * detects partial load to store forwarding cases (a store only has
58 * part of a load's data) that requires the load to wait until the
59 * store writes back. In the former case it holds onto the instruction
60 * until the dependence unit looks at it, and in the latter it stalls
61 * the LSQ until the store writes back. At that point the load is
67 typedef TheISA::IntReg IntReg;
69 typedef typename Impl::O3CPU O3CPU;
70 typedef typename Impl::DynInstPtr DynInstPtr;
71 typedef typename Impl::CPUPol::IEW IEW;
72 typedef typename Impl::CPUPol::LSQ LSQ;
73 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
76 /** Constructs an LSQ unit. init() must be called prior to use. */
79 /** Initializes the LSQ unit with the specified number of entries. */
80 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
81 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
84 /** Returns the name of the LSQ unit. */
85 std::string name() const;
87 /** Registers statistics. */
90 /** Sets the pointer to the dcache port. */
91 void setDcachePort(Port *dcache_port);
93 /** Switches out LSQ unit. */
96 /** Takes over from another CPU's thread. */
99 /** Returns if the LSQ is switched out. */
100 bool isSwitchedOut() { return switchedOut; }
102 /** Ticks the LSQ unit, which in this case only resets the number of
104 * @todo: Move the number of used ports up to the LSQ level so it can
105 * be shared by all LSQ units.
107 void tick() { usedPorts = 0; }
109 /** Inserts an instruction. */
110 void insert(DynInstPtr &inst);
111 /** Inserts a load instruction. */
112 void insertLoad(DynInstPtr &load_inst);
113 /** Inserts a store instruction. */
114 void insertStore(DynInstPtr &store_inst);
116 /** Executes a load instruction. */
117 Fault executeLoad(DynInstPtr &inst);
119 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
120 /** Executes a store instruction. */
121 Fault executeStore(DynInstPtr &inst);
123 /** Commits the head load. */
125 /** Commits loads older than a specific sequence number. */
126 void commitLoads(InstSeqNum &youngest_inst);
128 /** Commits stores older than a specific sequence number. */
129 void commitStores(InstSeqNum &youngest_inst);
131 /** Writes back stores. */
132 void writebackStores();
134 /** Completes the data access that has been returned from the
136 void completeDataAccess(PacketPtr pkt);
138 /** Clears all the entries in the LQ. */
141 /** Clears all the entries in the SQ. */
144 /** Resizes the LQ to a given size. */
145 void resizeLQ(unsigned size);
147 /** Resizes the SQ to a given size. */
148 void resizeSQ(unsigned size);
150 /** Squashes all instructions younger than a specific sequence number. */
151 void squash(const InstSeqNum &squashed_num);
153 /** Returns if there is a memory ordering violation. Value is reset upon
154 * call to getMemDepViolator().
156 bool violation() { return memDepViolator; }
158 /** Returns the memory ordering violator. */
159 DynInstPtr getMemDepViolator();
161 /** Returns if a load became blocked due to the memory system. */
163 { return isLoadBlocked; }
165 /** Clears the signal that a load became blocked. */
166 void clearLoadBlocked()
167 { isLoadBlocked = false; }
169 /** Returns if the blocked load was handled. */
170 bool isLoadBlockedHandled()
171 { return loadBlockedHandled; }
173 /** Records the blocked load as being handled. */
174 void setLoadBlockedHandled()
175 { loadBlockedHandled = true; }
177 /** Returns the number of free entries (min of free LQ and SQ entries). */
178 unsigned numFreeEntries();
180 /** Returns the number of loads ready to execute. */
183 /** Returns the number of loads in the LQ. */
184 int numLoads() { return loads; }
186 /** Returns the number of stores in the SQ. */
187 int numStores() { return stores; }
189 /** Returns if either the LQ or SQ is full. */
190 bool isFull() { return lqFull() || sqFull(); }
192 /** Returns if the LQ is full. */
193 bool lqFull() { return loads >= (LQEntries - 1); }
195 /** Returns if the SQ is full. */
196 bool sqFull() { return stores >= (SQEntries - 1); }
198 /** Returns the number of instructions in the LSQ. */
199 unsigned getCount() { return loads + stores; }
201 /** Returns if there are any stores to writeback. */
202 bool hasStoresToWB() { return storesToWB; }
204 /** Returns the number of stores to writeback. */
205 int numStoresToWB() { return storesToWB; }
207 /** Returns if the LSQ unit will writeback on this cycle. */
208 bool willWB() { return storeQueue[storeWBIdx].canWB &&
209 !storeQueue[storeWBIdx].completed &&
212 /** Handles doing the retry. */
216 /** Writes back the instruction, sending it to IEW. */
217 void writeback(DynInstPtr &inst, PacketPtr pkt);
219 /** Writes back a store that couldn't be completed the previous cycle. */
220 void writebackPendingStore();
222 /** Handles completing the send of a store to memory. */
223 void storePostSend(PacketPtr pkt);
225 /** Completes the store at the specified index. */
226 void completeStore(int store_idx);
228 /** Attempts to send a store to the cache. */
229 bool sendStore(PacketPtr data_pkt);
231 /** Increments the given store index (circular queue). */
232 inline void incrStIdx(int &store_idx);
233 /** Decrements the given store index (circular queue). */
234 inline void decrStIdx(int &store_idx);
235 /** Increments the given load index (circular queue). */
236 inline void incrLdIdx(int &load_idx);
237 /** Decrements the given load index (circular queue). */
238 inline void decrLdIdx(int &load_idx);
241 /** Debugging function to dump instructions in the LSQ. */
245 /** Pointer to the CPU. */
248 /** Pointer to the IEW stage. */
251 /** Pointer to the LSQ. */
254 /** Pointer to the dcache port. Used only for sending. */
257 /** Derived class to hold any sender state the LSQ needs. */
258 class LSQSenderState : public Packet::SenderState, public FastAlloc
261 /** Default constructor. */
263 : noWB(false), isSplit(false), pktToSend(false), outstanding(1),
264 mainPkt(NULL), pendingPacket(NULL)
267 /** Instruction who initiated the access to memory. */
269 /** Whether or not it is a load. */
271 /** The LQ/SQ index of the instruction. */
273 /** Whether or not the instruction will need to writeback. */
275 /** Whether or not this access is split in two. */
277 /** Whether or not there is a packet that needs sending. */
279 /** Number of outstanding packets to complete. */
281 /** The main packet from a split load, used during writeback. */
283 /** A second packet from a split store that needs sending. */
284 PacketPtr pendingPacket;
286 /** Completes a packet and returns whether the access is finished. */
287 inline bool complete() { return --outstanding == 0; }
290 /** Writeback event, specifically for when stores forward data to loads. */
291 class WritebackEvent : public Event {
293 /** Constructs a writeback event. */
294 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
296 /** Processes the writeback event. */
299 /** Returns the description of this event. */
300 const char *description() const;
303 /** Instruction whose results are being written back. */
306 /** The packet that would have been sent to memory. */
309 /** The pointer to the LSQ unit that issued the store. */
310 LSQUnit<Impl> *lsqPtr;
315 /** Constructs an empty store queue entry. */
317 : inst(NULL), req(NULL), size(0),
318 canWB(0), committed(0), completed(0)
320 std::memset(data, 0, sizeof(data));
323 /** Constructs a store queue entry for a given instruction. */
324 SQEntry(DynInstPtr &_inst)
325 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
326 isSplit(0), canWB(0), committed(0), completed(0)
328 std::memset(data, 0, sizeof(data));
331 /** The store instruction. */
333 /** The request for the store. */
335 /** The split requests for the store. */
338 /** The size of the store. */
340 /** The store data. */
341 char data[sizeof(IntReg)];
342 /** Whether or not the store is split into two requests. */
344 /** Whether or not the store can writeback. */
346 /** Whether or not the store is committed. */
348 /** Whether or not the store is completed. */
353 /** The LSQUnit thread id. */
356 /** The store queue. */
357 std::vector<SQEntry> storeQueue;
359 /** The load queue. */
360 std::vector<DynInstPtr> loadQueue;
362 /** The number of LQ entries, plus a sentinel entry (circular queue).
363 * @todo: Consider having var that records the true number of LQ entries.
366 /** The number of SQ entries, plus a sentinel entry (circular queue).
367 * @todo: Consider having var that records the true number of SQ entries.
371 /** The number of load instructions in the LQ. */
373 /** The number of store instructions in the SQ. */
375 /** The number of store instructions in the SQ waiting to writeback. */
378 /** The index of the head instruction in the LQ. */
380 /** The index of the tail instruction in the LQ. */
383 /** The index of the head instruction in the SQ. */
385 /** The index of the first instruction that may be ready to be
386 * written back, and has not yet been written back.
389 /** The index of the tail instruction in the SQ. */
392 /// @todo Consider moving to a more advanced model with write vs read ports
393 /** The number of cache ports available each cycle. */
396 /** The number of used cache ports in this cycle. */
399 /** Is the LSQ switched out. */
402 //list<InstSeqNum> mshrSeqNums;
404 /** Wire to read information from the issue stage time queue. */
405 typename TimeBuffer<IssueStruct>::wire fromIssue;
407 /** Whether or not the LSQ is stalled. */
409 /** The store that causes the stall due to partial store to load
412 InstSeqNum stallingStoreIsn;
413 /** The index of the above store. */
416 /** The packet that needs to be retried. */
419 /** Whehter or not a store is blocked due to the memory system. */
422 /** Whether or not a load is blocked due to the memory system. */
425 /** Has the blocked load been handled. */
426 bool loadBlockedHandled;
428 /** The sequence number of the blocked load. */
429 InstSeqNum blockedLoadSeqNum;
431 /** The oldest load that caused a memory ordering violation. */
432 DynInstPtr memDepViolator;
434 /** Whether or not there is a packet that couldn't be sent because of
435 * a lack of cache ports. */
438 /** The packet that is pending free cache ports. */
439 PacketPtr pendingPkt;
441 // Will also need how many read/write ports the Dcache has. Or keep track
442 // of that in stage that is one level up, and only call executeLoad/Store
443 // the appropriate number of times.
444 /** Total number of loads forwaded from LSQ stores. */
445 Stats::Scalar lsqForwLoads;
447 /** Total number of loads ignored due to invalid addresses. */
448 Stats::Scalar invAddrLoads;
450 /** Total number of squashed loads. */
451 Stats::Scalar lsqSquashedLoads;
453 /** Total number of responses from the memory system that are
454 * ignored due to the instruction already being squashed. */
455 Stats::Scalar lsqIgnoredResponses;
457 /** Tota number of memory ordering violations. */
458 Stats::Scalar lsqMemOrderViolation;
460 /** Total number of squashed stores. */
461 Stats::Scalar lsqSquashedStores;
463 /** Total number of software prefetches ignored due to invalid addresses. */
464 Stats::Scalar invAddrSwpfs;
466 /** Ready loads blocked due to partial store-forwarding. */
467 Stats::Scalar lsqBlockedLoads;
469 /** Number of loads that were rescheduled. */
470 Stats::Scalar lsqRescheduledLoads;
472 /** Number of times the LSQ is blocked due to the cache. */
473 Stats::Scalar lsqCacheBlocked;
476 /** Executes the load at the given index. */
478 Fault read(Request *req, Request *sreqLow, Request *sreqHigh, T &data,
481 /** Executes the store at the given index. */
483 Fault write(Request *req, Request *sreqLow, Request *sreqHigh, T &data,
486 /** Returns the index of the head load instruction. */
487 int getLoadHead() { return loadHead; }
488 /** Returns the sequence number of the head load instruction. */
489 InstSeqNum getLoadHeadSeqNum()
491 if (loadQueue[loadHead]) {
492 return loadQueue[loadHead]->seqNum;
499 /** Returns the index of the head store instruction. */
500 int getStoreHead() { return storeHead; }
501 /** Returns the sequence number of the head store instruction. */
502 InstSeqNum getStoreHeadSeqNum()
504 if (storeQueue[storeHead].inst) {
505 return storeQueue[storeHead].inst->seqNum;
512 /** Returns whether or not the LSQ unit is stalled. */
513 bool isStalled() { return stalled; }
516 template <class Impl>
519 LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
520 T &data, int load_idx)
522 DynInstPtr load_inst = loadQueue[load_idx];
526 assert(!load_inst->isExecuted());
528 // Make sure this isn't an uncacheable access
529 // A bit of a hackish way to get uncached accesses to work only if they're
530 // at the head of the LSQ and are ready to commit (at the head of the ROB
532 if (req->isUncacheable() &&
533 (load_idx != loadHead || !load_inst->isAtCommit())) {
534 iewStage->rescheduleMemInst(load_inst);
535 ++lsqRescheduledLoads;
537 // Must delete request now that it wasn't handed off to
538 // memory. This is quite ugly. @todo: Figure out the proper
539 // place to really handle request deletes.
541 if (TheISA::HasUnalignedMemAcc && sreqLow) {
545 return TheISA::genMachineCheckFault();
548 // Check the SQ for any previous stores that might lead to forwarding
549 int store_idx = load_inst->sqIdx;
553 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
554 "storeHead: %i addr: %#x%s\n",
555 load_idx, store_idx, storeHead, req->getPaddr(),
556 sreqLow ? " split" : "");
560 // Disable recording the result temporarily. Writing to misc
561 // regs normally updates the result, but this is not the
562 // desired behavior when handling store conditionals.
563 load_inst->recordResult = false;
564 TheISA::handleLockedRead(load_inst.get(), req);
565 load_inst->recordResult = true;
568 while (store_idx != -1) {
569 // End once we've reached the top of the LSQ
570 if (store_idx == storeWBIdx) {
574 // Move the index to one younger
576 store_idx += SQEntries;
578 assert(storeQueue[store_idx].inst);
580 store_size = storeQueue[store_idx].size;
584 else if (storeQueue[store_idx].inst->uncacheable())
587 assert(storeQueue[store_idx].inst->effAddrValid);
589 // Check if the store data is within the lower and upper bounds of
590 // addresses that the request needs.
591 bool store_has_lower_limit =
592 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
593 bool store_has_upper_limit =
594 (req->getVaddr() + req->getSize()) <=
595 (storeQueue[store_idx].inst->effAddr + store_size);
596 bool lower_load_has_store_part =
597 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
599 bool upper_load_has_store_part =
600 (req->getVaddr() + req->getSize()) >
601 storeQueue[store_idx].inst->effAddr;
603 // If the store's data has all of the data needed, we can forward.
604 if ((store_has_lower_limit && store_has_upper_limit)) {
605 // Get shift amount for offset into the store's data.
606 int shift_amt = req->getVaddr() & (store_size - 1);
608 memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
610 assert(!load_inst->memData);
611 load_inst->memData = new uint8_t[64];
613 memcpy(load_inst->memData,
614 storeQueue[store_idx].data + shift_amt, req->getSize());
616 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
617 "addr %#x, data %#x\n",
618 store_idx, req->getVaddr(), data);
620 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
622 data_pkt->dataStatic(load_inst->memData);
624 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
626 // We'll say this has a 1 cycle load-store forwarding latency
628 // @todo: Need to make this a parameter.
629 cpu->schedule(wb, curTick);
631 // Don't need to do anything special for split loads.
632 if (TheISA::HasUnalignedMemAcc && sreqLow) {
639 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
640 (store_has_upper_limit && upper_load_has_store_part) ||
641 (lower_load_has_store_part && upper_load_has_store_part)) {
642 // This is the partial store-load forwarding case where a store
643 // has only part of the load's data.
645 // If it's already been written back, then don't worry about
647 if (storeQueue[store_idx].completed) {
648 panic("Should not check one of these");
652 // Must stall load and force it to retry, so long as it's the oldest
653 // load that needs to do so.
657 loadQueue[stallingLoadIdx]->seqNum)) {
659 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
660 stallingLoadIdx = load_idx;
663 // Tell IQ/mem dep unit that this instruction will need to be
664 // rescheduled eventually
665 iewStage->rescheduleMemInst(load_inst);
666 iewStage->decrWb(load_inst->seqNum);
667 load_inst->clearIssued();
668 ++lsqRescheduledLoads;
670 // Do not generate a writeback event as this instruction is not
672 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
673 "Store idx %i to load addr %#x\n",
674 store_idx, req->getVaddr());
676 // Must delete request now that it wasn't handed off to
677 // memory. This is quite ugly. @todo: Figure out the
678 // proper place to really handle request deletes.
680 if (TheISA::HasUnalignedMemAcc && sreqLow) {
689 // If there's no forwarding case, then go access memory
690 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
691 load_inst->seqNum, load_inst->readPC());
693 assert(!load_inst->memData);
694 load_inst->memData = new uint8_t[64];
698 // if we the cache is not blocked, do cache access
699 bool completedFirst = false;
700 if (!lsq->cacheBlocked()) {
702 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
703 PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
704 PacketPtr fst_data_pkt = NULL;
705 PacketPtr snd_data_pkt = NULL;
707 data_pkt->dataStatic(load_inst->memData);
709 LSQSenderState *state = new LSQSenderState;
710 state->isLoad = true;
711 state->idx = load_idx;
712 state->inst = load_inst;
713 data_pkt->senderState = state;
715 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
717 // Point the first packet at the main data packet.
718 fst_data_pkt = data_pkt;
721 // Create the split packets.
722 fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
723 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
725 fst_data_pkt->dataStatic(load_inst->memData);
726 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
728 fst_data_pkt->senderState = state;
729 snd_data_pkt->senderState = state;
731 state->isSplit = true;
732 state->outstanding = 2;
733 state->mainPkt = data_pkt;
736 if (!dcachePort->sendTiming(fst_data_pkt)) {
737 // Delete state and data packet because a load retry
738 // initiates a pipeline restart; it does not retry.
740 delete data_pkt->req;
742 if (TheISA::HasUnalignedMemAcc && sreqLow) {
743 delete fst_data_pkt->req;
745 delete snd_data_pkt->req;
753 // If the access didn't succeed, tell the LSQ by setting
754 // the retry thread id.
755 lsq->setRetryTid(lsqID);
756 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
757 completedFirst = true;
759 // The first packet was sent without problems, so send this one
760 // too. If there is a problem with this packet then the whole
761 // load will be squashed, so indicate this to the state object.
762 // The first packet will return in completeDataAccess and be
765 if (!dcachePort->sendTiming(snd_data_pkt)) {
767 // The main packet will be deleted in completeDataAccess.
768 delete snd_data_pkt->req;
776 lsq->setRetryTid(lsqID);
781 // If the cache was blocked, or has become blocked due to the access,
783 if (lsq->cacheBlocked()) {
786 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) {
793 iewStage->decrWb(load_inst->seqNum);
794 // There's an older load that's already going to squash.
795 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
798 // Record that the load was blocked due to memory. This
799 // load will squash all instructions after it, be
800 // refetched, and re-executed.
801 isLoadBlocked = true;
802 loadBlockedHandled = false;
803 blockedLoadSeqNum = load_inst->seqNum;
804 // No fault occurred, even though the interface is blocked.
811 template <class Impl>
814 LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
815 T &data, int store_idx)
817 assert(storeQueue[store_idx].inst);
819 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
820 " | storeHead:%i [sn:%i]\n",
821 store_idx, req->getPaddr(), data, storeHead,
822 storeQueue[store_idx].inst->seqNum);
824 storeQueue[store_idx].req = req;
825 storeQueue[store_idx].sreqLow = sreqLow;
826 storeQueue[store_idx].sreqHigh = sreqHigh;
827 storeQueue[store_idx].size = sizeof(T);
829 // Split stores can only occur in ISAs with unaligned memory accesses. If
830 // a store request has been split, sreqLow and sreqHigh will be non-null.
831 if (TheISA::HasUnalignedMemAcc && sreqLow) {
832 storeQueue[store_idx].isSplit = true;
834 assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
836 T gData = htog(data);
837 memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
839 // This function only writes the data to the store queue, so no fault
844 #endif // __CPU_O3_LSQ_UNIT_HH__