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45 #ifndef __CPU_O3_LSQ_UNIT_HH__
46 #define __CPU_O3_LSQ_UNIT_HH__
53 #include "arch/generic/debugfaults.hh"
54 #include "arch/isa_traits.hh"
55 #include "arch/locked_mem.hh"
56 #include "arch/mmapped_ipr.hh"
57 #include "base/hashmap.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/inst_seq.hh"
60 #include "cpu/timebuf.hh"
61 #include "debug/LSQUnit.hh"
62 #include "mem/packet.hh"
63 #include "mem/port.hh"
64 #include "sim/fault_fwd.hh"
66 struct DerivO3CPUParams;
69 * Class that implements the actual LQ and SQ for each specific
70 * thread. Both are circular queues; load entries are freed upon
71 * committing, while store entries are freed once they writeback. The
72 * LSQUnit tracks if there are memory ordering violations, and also
73 * detects partial load to store forwarding cases (a store only has
74 * part of a load's data) that requires the load to wait until the
75 * store writes back. In the former case it holds onto the instruction
76 * until the dependence unit looks at it, and in the latter it stalls
77 * the LSQ until the store writes back. At that point the load is
83 typedef typename Impl::O3CPU O3CPU;
84 typedef typename Impl::DynInstPtr DynInstPtr;
85 typedef typename Impl::CPUPol::IEW IEW;
86 typedef typename Impl::CPUPol::LSQ LSQ;
87 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
90 /** Constructs an LSQ unit. init() must be called prior to use. */
93 /** Initializes the LSQ unit with the specified number of entries. */
94 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
95 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
98 /** Returns the name of the LSQ unit. */
99 std::string name() const;
101 /** Registers statistics. */
104 /** Sets the pointer to the dcache port. */
105 void setDcachePort(MasterPort *dcache_port);
107 /** Perform sanity checks after a drain. */
108 void drainSanityCheck() const;
110 /** Takes over from another CPU's thread. */
113 /** Ticks the LSQ unit, which in this case only resets the number of
115 * @todo: Move the number of used ports up to the LSQ level so it can
116 * be shared by all LSQ units.
118 void tick() { usedPorts = 0; }
120 /** Inserts an instruction. */
121 void insert(DynInstPtr &inst);
122 /** Inserts a load instruction. */
123 void insertLoad(DynInstPtr &load_inst);
124 /** Inserts a store instruction. */
125 void insertStore(DynInstPtr &store_inst);
127 /** Check for ordering violations in the LSQ. For a store squash if we
128 * ever find a conflicting load. For a load, only squash if we
129 * an external snoop invalidate has been seen for that load address
130 * @param load_idx index to start checking at
131 * @param inst the instruction to check
133 Fault checkViolations(int load_idx, DynInstPtr &inst);
135 /** Check if an incoming invalidate hits in the lsq on a load
136 * that might have issued out of order wrt another load beacuse
137 * of the intermediate invalidate.
139 void checkSnoop(PacketPtr pkt);
141 /** Executes a load instruction. */
142 Fault executeLoad(DynInstPtr &inst);
144 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
145 /** Executes a store instruction. */
146 Fault executeStore(DynInstPtr &inst);
148 /** Commits the head load. */
150 /** Commits loads older than a specific sequence number. */
151 void commitLoads(InstSeqNum &youngest_inst);
153 /** Commits stores older than a specific sequence number. */
154 void commitStores(InstSeqNum &youngest_inst);
156 /** Writes back stores. */
157 void writebackStores();
159 /** Completes the data access that has been returned from the
161 void completeDataAccess(PacketPtr pkt);
163 /** Clears all the entries in the LQ. */
166 /** Clears all the entries in the SQ. */
169 /** Resizes the LQ to a given size. */
170 void resizeLQ(unsigned size);
172 /** Resizes the SQ to a given size. */
173 void resizeSQ(unsigned size);
175 /** Squashes all instructions younger than a specific sequence number. */
176 void squash(const InstSeqNum &squashed_num);
178 /** Returns if there is a memory ordering violation. Value is reset upon
179 * call to getMemDepViolator().
181 bool violation() { return memDepViolator; }
183 /** Returns the memory ordering violator. */
184 DynInstPtr getMemDepViolator();
186 /** Returns the number of free LQ entries. */
187 unsigned numFreeLoadEntries();
189 /** Returns the number of free SQ entries. */
190 unsigned numFreeStoreEntries();
192 /** Returns the number of loads in the LQ. */
193 int numLoads() { return loads; }
195 /** Returns the number of stores in the SQ. */
196 int numStores() { return stores; }
198 /** Returns if either the LQ or SQ is full. */
199 bool isFull() { return lqFull() || sqFull(); }
201 /** Returns if both the LQ and SQ are empty. */
202 bool isEmpty() const { return lqEmpty() && sqEmpty(); }
204 /** Returns if the LQ is full. */
205 bool lqFull() { return loads >= (LQEntries - 1); }
207 /** Returns if the SQ is full. */
208 bool sqFull() { return stores >= (SQEntries - 1); }
210 /** Returns if the LQ is empty. */
211 bool lqEmpty() const { return loads == 0; }
213 /** Returns if the SQ is empty. */
214 bool sqEmpty() const { return stores == 0; }
216 /** Returns the number of instructions in the LSQ. */
217 unsigned getCount() { return loads + stores; }
219 /** Returns if there are any stores to writeback. */
220 bool hasStoresToWB() { return storesToWB; }
222 /** Returns the number of stores to writeback. */
223 int numStoresToWB() { return storesToWB; }
225 /** Returns if the LSQ unit will writeback on this cycle. */
226 bool willWB() { return storeQueue[storeWBIdx].canWB &&
227 !storeQueue[storeWBIdx].completed &&
230 /** Handles doing the retry. */
234 /** Reset the LSQ state */
237 /** Writes back the instruction, sending it to IEW. */
238 void writeback(DynInstPtr &inst, PacketPtr pkt);
240 /** Writes back a store that couldn't be completed the previous cycle. */
241 void writebackPendingStore();
243 /** Handles completing the send of a store to memory. */
244 void storePostSend(PacketPtr pkt);
246 /** Completes the store at the specified index. */
247 void completeStore(int store_idx);
249 /** Attempts to send a store to the cache. */
250 bool sendStore(PacketPtr data_pkt);
252 /** Increments the given store index (circular queue). */
253 inline void incrStIdx(int &store_idx) const;
254 /** Decrements the given store index (circular queue). */
255 inline void decrStIdx(int &store_idx) const;
256 /** Increments the given load index (circular queue). */
257 inline void incrLdIdx(int &load_idx) const;
258 /** Decrements the given load index (circular queue). */
259 inline void decrLdIdx(int &load_idx) const;
262 /** Debugging function to dump instructions in the LSQ. */
263 void dumpInsts() const;
266 /** Pointer to the CPU. */
269 /** Pointer to the IEW stage. */
272 /** Pointer to the LSQ. */
275 /** Pointer to the dcache port. Used only for sending. */
276 MasterPort *dcachePort;
278 /** Derived class to hold any sender state the LSQ needs. */
279 class LSQSenderState : public Packet::SenderState
282 /** Default constructor. */
284 : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
285 noWB(false), isSplit(false), pktToSend(false), cacheBlocked(false)
288 /** Instruction who initiated the access to memory. */
290 /** The main packet from a split load, used during writeback. */
292 /** A second packet from a split store that needs sending. */
293 PacketPtr pendingPacket;
294 /** The LQ/SQ index of the instruction. */
296 /** Number of outstanding packets to complete. */
298 /** Whether or not it is a load. */
300 /** Whether or not the instruction will need to writeback. */
302 /** Whether or not this access is split in two. */
304 /** Whether or not there is a packet that needs sending. */
306 /** Whether or not the second packet of this split load was blocked */
309 /** Completes a packet and returns whether the access is finished. */
310 inline bool complete() { return --outstanding == 0; }
313 /** Writeback event, specifically for when stores forward data to loads. */
314 class WritebackEvent : public Event {
316 /** Constructs a writeback event. */
317 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
319 /** Processes the writeback event. */
322 /** Returns the description of this event. */
323 const char *description() const;
326 /** Instruction whose results are being written back. */
329 /** The packet that would have been sent to memory. */
332 /** The pointer to the LSQ unit that issued the store. */
333 LSQUnit<Impl> *lsqPtr;
338 /** Constructs an empty store queue entry. */
340 : inst(NULL), req(NULL), size(0),
341 canWB(0), committed(0), completed(0)
343 std::memset(data, 0, sizeof(data));
351 /** Constructs a store queue entry for a given instruction. */
352 SQEntry(DynInstPtr &_inst)
353 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
354 isSplit(0), canWB(0), committed(0), completed(0), isAllZeros(0)
356 std::memset(data, 0, sizeof(data));
358 /** The store data. */
360 /** The store instruction. */
362 /** The request for the store. */
364 /** The split requests for the store. */
367 /** The size of the store. */
369 /** Whether or not the store is split into two requests. */
371 /** Whether or not the store can writeback. */
373 /** Whether or not the store is committed. */
375 /** Whether or not the store is completed. */
377 /** Does this request write all zeros and thus doesn't
378 * have any data attached to it. Used for cache block zero
379 * style instructs (ARM DC ZVA; ALPHA WH64)
385 /** The LSQUnit thread id. */
388 /** The store queue. */
389 std::vector<SQEntry> storeQueue;
391 /** The load queue. */
392 std::vector<DynInstPtr> loadQueue;
394 /** The number of LQ entries, plus a sentinel entry (circular queue).
395 * @todo: Consider having var that records the true number of LQ entries.
398 /** The number of SQ entries, plus a sentinel entry (circular queue).
399 * @todo: Consider having var that records the true number of SQ entries.
403 /** The number of places to shift addresses in the LSQ before checking
404 * for dependency violations
406 unsigned depCheckShift;
408 /** Should loads be checked for dependency issues */
411 /** The number of load instructions in the LQ. */
413 /** The number of store instructions in the SQ. */
415 /** The number of store instructions in the SQ waiting to writeback. */
418 /** The index of the head instruction in the LQ. */
420 /** The index of the tail instruction in the LQ. */
423 /** The index of the head instruction in the SQ. */
425 /** The index of the first instruction that may be ready to be
426 * written back, and has not yet been written back.
429 /** The index of the tail instruction in the SQ. */
432 /// @todo Consider moving to a more advanced model with write vs read ports
433 /** The number of cache ports available each cycle. */
436 /** The number of used cache ports in this cycle. */
439 //list<InstSeqNum> mshrSeqNums;
441 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
444 /** Wire to read information from the issue stage time queue. */
445 typename TimeBuffer<IssueStruct>::wire fromIssue;
447 /** Whether or not the LSQ is stalled. */
449 /** The store that causes the stall due to partial store to load
452 InstSeqNum stallingStoreIsn;
453 /** The index of the above store. */
456 /** The packet that needs to be retried. */
459 /** Whehter or not a store is blocked due to the memory system. */
462 /** Whether or not a store is in flight. */
465 /** The oldest load that caused a memory ordering violation. */
466 DynInstPtr memDepViolator;
468 /** Whether or not there is a packet that couldn't be sent because of
469 * a lack of cache ports. */
472 /** The packet that is pending free cache ports. */
473 PacketPtr pendingPkt;
475 /** Flag for memory model. */
478 // Will also need how many read/write ports the Dcache has. Or keep track
479 // of that in stage that is one level up, and only call executeLoad/Store
480 // the appropriate number of times.
481 /** Total number of loads forwaded from LSQ stores. */
482 Stats::Scalar lsqForwLoads;
484 /** Total number of loads ignored due to invalid addresses. */
485 Stats::Scalar invAddrLoads;
487 /** Total number of squashed loads. */
488 Stats::Scalar lsqSquashedLoads;
490 /** Total number of responses from the memory system that are
491 * ignored due to the instruction already being squashed. */
492 Stats::Scalar lsqIgnoredResponses;
494 /** Tota number of memory ordering violations. */
495 Stats::Scalar lsqMemOrderViolation;
497 /** Total number of squashed stores. */
498 Stats::Scalar lsqSquashedStores;
500 /** Total number of software prefetches ignored due to invalid addresses. */
501 Stats::Scalar invAddrSwpfs;
503 /** Ready loads blocked due to partial store-forwarding. */
504 Stats::Scalar lsqBlockedLoads;
506 /** Number of loads that were rescheduled. */
507 Stats::Scalar lsqRescheduledLoads;
509 /** Number of times the LSQ is blocked due to the cache. */
510 Stats::Scalar lsqCacheBlocked;
513 /** Executes the load at the given index. */
514 Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
515 uint8_t *data, int load_idx);
517 /** Executes the store at the given index. */
518 Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
519 uint8_t *data, int store_idx);
521 /** Returns the index of the head load instruction. */
522 int getLoadHead() { return loadHead; }
523 /** Returns the sequence number of the head load instruction. */
524 InstSeqNum getLoadHeadSeqNum()
526 if (loadQueue[loadHead]) {
527 return loadQueue[loadHead]->seqNum;
534 /** Returns the index of the head store instruction. */
535 int getStoreHead() { return storeHead; }
536 /** Returns the sequence number of the head store instruction. */
537 InstSeqNum getStoreHeadSeqNum()
539 if (storeQueue[storeHead].inst) {
540 return storeQueue[storeHead].inst->seqNum;
547 /** Returns whether or not the LSQ unit is stalled. */
548 bool isStalled() { return stalled; }
551 template <class Impl>
553 LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
554 uint8_t *data, int load_idx)
556 DynInstPtr load_inst = loadQueue[load_idx];
560 assert(!load_inst->isExecuted());
562 // Make sure this isn't an uncacheable access
563 // A bit of a hackish way to get uncached accesses to work only if they're
564 // at the head of the LSQ and are ready to commit (at the head of the ROB
566 if (req->isUncacheable() &&
567 (load_idx != loadHead || !load_inst->isAtCommit())) {
568 iewStage->rescheduleMemInst(load_inst);
569 ++lsqRescheduledLoads;
570 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
571 load_inst->seqNum, load_inst->pcState());
573 // Must delete request now that it wasn't handed off to
574 // memory. This is quite ugly. @todo: Figure out the proper
575 // place to really handle request deletes.
577 if (TheISA::HasUnalignedMemAcc && sreqLow) {
581 return new GenericISA::M5PanicFault(
582 "Uncachable load [sn:%llx] PC %s\n",
583 load_inst->seqNum, load_inst->pcState());
586 // Check the SQ for any previous stores that might lead to forwarding
587 int store_idx = load_inst->sqIdx;
591 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
592 "storeHead: %i addr: %#x%s\n",
593 load_idx, store_idx, storeHead, req->getPaddr(),
594 sreqLow ? " split" : "");
598 // Disable recording the result temporarily. Writing to misc
599 // regs normally updates the result, but this is not the
600 // desired behavior when handling store conditionals.
601 load_inst->recordResult(false);
602 TheISA::handleLockedRead(load_inst.get(), req);
603 load_inst->recordResult(true);
606 if (req->isMmappedIpr()) {
607 assert(!load_inst->memData);
608 load_inst->memData = new uint8_t[64];
610 ThreadContext *thread = cpu->tcBase(lsqID);
612 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
614 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
615 data_pkt->dataStatic(load_inst->memData);
616 delay = TheISA::handleIprRead(thread, data_pkt);
618 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
619 PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
620 PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
622 fst_data_pkt->dataStatic(load_inst->memData);
623 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
625 delay = TheISA::handleIprRead(thread, fst_data_pkt);
626 Cycles delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
635 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
636 cpu->schedule(wb, cpu->clockEdge(delay));
640 while (store_idx != -1) {
641 // End once we've reached the top of the LSQ
642 if (store_idx == storeWBIdx) {
646 // Move the index to one younger
648 store_idx += SQEntries;
650 assert(storeQueue[store_idx].inst);
652 store_size = storeQueue[store_idx].size;
656 else if (storeQueue[store_idx].inst->uncacheable())
659 assert(storeQueue[store_idx].inst->effAddrValid());
661 // Check if the store data is within the lower and upper bounds of
662 // addresses that the request needs.
663 bool store_has_lower_limit =
664 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
665 bool store_has_upper_limit =
666 (req->getVaddr() + req->getSize()) <=
667 (storeQueue[store_idx].inst->effAddr + store_size);
668 bool lower_load_has_store_part =
669 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
671 bool upper_load_has_store_part =
672 (req->getVaddr() + req->getSize()) >
673 storeQueue[store_idx].inst->effAddr;
675 // If the store's data has all of the data needed, we can forward.
676 if ((store_has_lower_limit && store_has_upper_limit)) {
677 // Get shift amount for offset into the store's data.
678 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
680 if (storeQueue[store_idx].isAllZeros)
681 memset(data, 0, req->getSize());
683 memcpy(data, storeQueue[store_idx].data + shift_amt,
686 // Allocate memory if this is the first time a load is issued.
687 if (!load_inst->memData) {
688 load_inst->memData = new uint8_t[req->getSize()];
690 if (storeQueue[store_idx].isAllZeros)
691 memset(load_inst->memData, 0, req->getSize());
693 memcpy(load_inst->memData,
694 storeQueue[store_idx].data + shift_amt, req->getSize());
696 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
697 "addr %#x\n", store_idx, req->getVaddr());
699 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
700 data_pkt->dataStatic(load_inst->memData);
702 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
704 // We'll say this has a 1 cycle load-store forwarding latency
706 // @todo: Need to make this a parameter.
707 cpu->schedule(wb, curTick());
709 // Don't need to do anything special for split loads.
710 if (TheISA::HasUnalignedMemAcc && sreqLow) {
717 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
718 (store_has_upper_limit && upper_load_has_store_part) ||
719 (lower_load_has_store_part && upper_load_has_store_part)) {
720 // This is the partial store-load forwarding case where a store
721 // has only part of the load's data.
723 // If it's already been written back, then don't worry about
725 if (storeQueue[store_idx].completed) {
726 panic("Should not check one of these");
730 // Must stall load and force it to retry, so long as it's the oldest
731 // load that needs to do so.
735 loadQueue[stallingLoadIdx]->seqNum)) {
737 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
738 stallingLoadIdx = load_idx;
741 // Tell IQ/mem dep unit that this instruction will need to be
742 // rescheduled eventually
743 iewStage->rescheduleMemInst(load_inst);
744 load_inst->clearIssued();
745 ++lsqRescheduledLoads;
747 // Do not generate a writeback event as this instruction is not
749 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
750 "Store idx %i to load addr %#x\n",
751 store_idx, req->getVaddr());
753 // Must delete request now that it wasn't handed off to
754 // memory. This is quite ugly. @todo: Figure out the
755 // proper place to really handle request deletes.
757 if (TheISA::HasUnalignedMemAcc && sreqLow) {
766 // If there's no forwarding case, then go access memory
767 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
768 load_inst->seqNum, load_inst->pcState());
770 // Allocate memory if this is the first time a load is issued.
771 if (!load_inst->memData) {
772 load_inst->memData = new uint8_t[req->getSize()];
777 // if we the cache is not blocked, do cache access
778 bool completedFirst = false;
779 PacketPtr data_pkt = Packet::createRead(req);
780 PacketPtr fst_data_pkt = NULL;
781 PacketPtr snd_data_pkt = NULL;
783 data_pkt->dataStatic(load_inst->memData);
785 LSQSenderState *state = new LSQSenderState;
786 state->isLoad = true;
787 state->idx = load_idx;
788 state->inst = load_inst;
789 data_pkt->senderState = state;
791 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
792 // Point the first packet at the main data packet.
793 fst_data_pkt = data_pkt;
795 // Create the split packets.
796 fst_data_pkt = Packet::createRead(sreqLow);
797 snd_data_pkt = Packet::createRead(sreqHigh);
799 fst_data_pkt->dataStatic(load_inst->memData);
800 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
802 fst_data_pkt->senderState = state;
803 snd_data_pkt->senderState = state;
805 state->isSplit = true;
806 state->outstanding = 2;
807 state->mainPkt = data_pkt;
810 bool successful_load = true;
811 if (!dcachePort->sendTimingReq(fst_data_pkt)) {
812 successful_load = false;
813 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
814 completedFirst = true;
816 // The first packet was sent without problems, so send this one
817 // too. If there is a problem with this packet then the whole
818 // load will be squashed, so indicate this to the state object.
819 // The first packet will return in completeDataAccess and be
822 if (!dcachePort->sendTimingReq(snd_data_pkt)) {
823 // The main packet will be deleted in completeDataAccess.
825 // Signify to 1st half that the 2nd half was blocked via state
826 state->cacheBlocked = true;
827 successful_load = false;
831 // If the cache was blocked, or has become blocked due to the access,
833 if (!successful_load) {
835 // Packet wasn't split, just delete main packet info
841 if (TheISA::HasUnalignedMemAcc && sreqLow) {
842 if (!completedFirst) {
843 // Split packet, but first failed. Delete all state.
854 // Can't delete main packet data or state because first packet
855 // was sent to the memory system
866 iewStage->blockMemInst(load_inst);
868 // No fault occurred, even though the interface is blocked.
875 template <class Impl>
877 LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
878 uint8_t *data, int store_idx)
880 assert(storeQueue[store_idx].inst);
882 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x"
883 " | storeHead:%i [sn:%i]\n",
884 store_idx, req->getPaddr(), storeHead,
885 storeQueue[store_idx].inst->seqNum);
887 storeQueue[store_idx].req = req;
888 storeQueue[store_idx].sreqLow = sreqLow;
889 storeQueue[store_idx].sreqHigh = sreqHigh;
890 unsigned size = req->getSize();
891 storeQueue[store_idx].size = size;
892 storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO;
893 assert(size <= sizeof(storeQueue[store_idx].data) ||
894 (req->getFlags() & Request::CACHE_BLOCK_ZERO));
896 // Split stores can only occur in ISAs with unaligned memory accesses. If
897 // a store request has been split, sreqLow and sreqHigh will be non-null.
898 if (TheISA::HasUnalignedMemAcc && sreqLow) {
899 storeQueue[store_idx].isSplit = true;
902 if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO))
903 memcpy(storeQueue[store_idx].data, data, size);
905 // This function only writes the data to the store queue, so no fault
910 #endif // __CPU_O3_LSQ_UNIT_HH__