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32 #include "arch/locked_mem.hh"
33 #include "config/use_checker.hh"
35 #include "cpu/o3/lsq.hh"
36 #include "cpu/o3/lsq_unit.hh"
37 #include "base/str.hh"
38 #include "mem/packet.hh"
39 #include "mem/request.hh"
42 #include "cpu/checker/cpu.hh"
46 LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
50 this->setFlags(Event::AutoDelete);
55 LSQUnit<Impl>::WritebackEvent::process()
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
65 LSQUnit<Impl>::WritebackEvent::description()
67 return "Store writeback event";
72 LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
74 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
75 DynInstPtr inst = state->inst;
76 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
77 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
79 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
81 if (isSwitchedOut() || inst->isSquashed()) {
82 iewStage->decrWb(inst->seqNum);
91 if (inst->isStore()) {
92 completeStore(state->idx);
100 template <class Impl>
101 LSQUnit<Impl>::LSQUnit()
102 : loads(0), stores(0), storesToWB(0), stalled(false),
103 isStoreBlocked(false), isLoadBlocked(false),
104 loadBlockedHandled(false)
110 LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
111 unsigned maxSQEntries, unsigned id)
113 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
121 // Add 1 for the sentinel entry (they are circular queues).
122 LQEntries = maxLQEntries + 1;
123 SQEntries = maxSQEntries + 1;
125 loadQueue.resize(LQEntries);
126 storeQueue.resize(SQEntries);
128 loadHead = loadTail = 0;
130 storeHead = storeWBIdx = storeTail = 0;
133 cachePorts = params->cachePorts;
136 memDepViolator = NULL;
138 blockedLoadSeqNum = 0;
143 LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
149 cpu->checker->setDcachePort(dcachePort);
156 LSQUnit<Impl>::name() const
158 if (Impl::MaxThreads == 1) {
159 return iewStage->name() + ".lsq";
161 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
167 LSQUnit<Impl>::regStats()
170 .name(name() + ".forwLoads")
171 .desc("Number of loads that had data forwarded from stores");
174 .name(name() + ".invAddrLoads")
175 .desc("Number of loads ignored due to an invalid address");
178 .name(name() + ".squashedLoads")
179 .desc("Number of loads squashed");
182 .name(name() + ".ignoredResponses")
183 .desc("Number of memory responses ignored because the instruction is squashed");
186 .name(name() + ".memOrderViolation")
187 .desc("Number of memory ordering violations");
190 .name(name() + ".squashedStores")
191 .desc("Number of stores squashed");
194 .name(name() + ".invAddrSwpfs")
195 .desc("Number of software prefetches ignored due to an invalid address");
198 .name(name() + ".blockedLoads")
199 .desc("Number of blocked loads due to partial load-store forwarding");
202 .name(name() + ".rescheduledLoads")
203 .desc("Number of loads that were rescheduled");
206 .name(name() + ".cacheBlocked")
207 .desc("Number of times an access to memory failed due to the cache being blocked");
212 LSQUnit<Impl>::clearLQ()
219 LSQUnit<Impl>::clearSQ()
226 LSQUnit<Impl>::switchOut()
229 for (int i = 0; i < loadQueue.size(); ++i) {
230 assert(!loadQueue[i]);
234 assert(storesToWB == 0);
239 LSQUnit<Impl>::takeOverFrom()
242 loads = stores = storesToWB = 0;
244 loadHead = loadTail = 0;
246 storeHead = storeWBIdx = storeTail = 0;
250 memDepViolator = NULL;
252 blockedLoadSeqNum = 0;
255 isLoadBlocked = false;
256 loadBlockedHandled = false;
261 LSQUnit<Impl>::resizeLQ(unsigned size)
263 unsigned size_plus_sentinel = size + 1;
264 assert(size_plus_sentinel >= LQEntries);
266 if (size_plus_sentinel > LQEntries) {
267 while (size_plus_sentinel > loadQueue.size()) {
269 loadQueue.push_back(dummy);
273 LQEntries = size_plus_sentinel;
280 LSQUnit<Impl>::resizeSQ(unsigned size)
282 unsigned size_plus_sentinel = size + 1;
283 if (size_plus_sentinel > SQEntries) {
284 while (size_plus_sentinel > storeQueue.size()) {
286 storeQueue.push_back(dummy);
290 SQEntries = size_plus_sentinel;
294 template <class Impl>
296 LSQUnit<Impl>::insert(DynInstPtr &inst)
298 assert(inst->isMemRef());
300 assert(inst->isLoad() || inst->isStore());
302 if (inst->isLoad()) {
311 template <class Impl>
313 LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
315 assert((loadTail + 1) % LQEntries != loadHead);
316 assert(loads < LQEntries);
318 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
319 load_inst->readPC(), loadTail, load_inst->seqNum);
321 load_inst->lqIdx = loadTail;
324 load_inst->sqIdx = -1;
326 load_inst->sqIdx = storeTail;
329 loadQueue[loadTail] = load_inst;
336 template <class Impl>
338 LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
340 // Make sure it is not full before inserting an instruction.
341 assert((storeTail + 1) % SQEntries != storeHead);
342 assert(stores < SQEntries);
344 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
345 store_inst->readPC(), storeTail, store_inst->seqNum);
347 store_inst->sqIdx = storeTail;
348 store_inst->lqIdx = loadTail;
350 storeQueue[storeTail] = SQEntry(store_inst);
352 incrStIdx(storeTail);
357 template <class Impl>
358 typename Impl::DynInstPtr
359 LSQUnit<Impl>::getMemDepViolator()
361 DynInstPtr temp = memDepViolator;
363 memDepViolator = NULL;
368 template <class Impl>
370 LSQUnit<Impl>::numFreeEntries()
372 unsigned free_lq_entries = LQEntries - loads;
373 unsigned free_sq_entries = SQEntries - stores;
375 // Both the LQ and SQ entries have an extra dummy entry to differentiate
376 // empty/full conditions. Subtract 1 from the free entries.
377 if (free_lq_entries < free_sq_entries) {
378 return free_lq_entries - 1;
380 return free_sq_entries - 1;
384 template <class Impl>
386 LSQUnit<Impl>::numLoadsReady()
388 int load_idx = loadHead;
391 while (load_idx != loadTail) {
392 assert(loadQueue[load_idx]);
394 if (loadQueue[load_idx]->readyToIssue()) {
402 template <class Impl>
404 LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
406 // Execute a specific load.
407 Fault load_fault = NoFault;
409 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
410 inst->readPC(),inst->seqNum);
412 load_fault = inst->initiateAcc();
414 // If the instruction faulted, then we need to send it along to commit
415 // without the instruction completing.
416 if (load_fault != NoFault) {
417 // Send this instruction to commit, also make sure iew stage
418 // realizes there is activity.
419 // Mark it as executed unless it is an uncached load that
420 // needs to hit the head of commit.
421 if (!(inst->req && inst->req->isUncacheable()) ||
422 inst->isAtCommit()) {
425 iewStage->instToCommit(inst);
426 iewStage->activityThisCycle();
432 template <class Impl>
434 LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
436 using namespace TheISA;
437 // Make sure that a store exists.
440 int store_idx = store_inst->sqIdx;
442 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
443 store_inst->readPC(), store_inst->seqNum);
445 // Check the recently completed loads to see if any match this store's
446 // address. If so, then we have a memory ordering violation.
447 int load_idx = store_inst->lqIdx;
449 Fault store_fault = store_inst->initiateAcc();
451 if (storeQueue[store_idx].size == 0) {
452 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
453 store_inst->readPC(),store_inst->seqNum);
458 assert(store_fault == NoFault);
460 if (store_inst->isStoreConditional()) {
461 // Store conditionals need to set themselves as able to
462 // writeback if we haven't had a fault by here.
463 storeQueue[store_idx].canWB = true;
468 if (!memDepViolator) {
469 while (load_idx != loadTail) {
470 // Really only need to check loads that have actually executed
471 // It's safe to check all loads because effAddr is set to
472 // InvalAddr when the dyn inst is created.
474 // @todo: For now this is extra conservative, detecting a
475 // violation if the addresses match assuming all accesses
476 // are quad word accesses.
478 // @todo: Fix this, magic number being used here
479 if ((loadQueue[load_idx]->effAddr >> 8) ==
480 (store_inst->effAddr >> 8)) {
481 // A load incorrectly passed this store. Squash and refetch.
482 // For now return a fault to show that it was unsuccessful.
483 memDepViolator = loadQueue[load_idx];
484 ++lsqMemOrderViolation;
486 return genMachineCheckFault();
492 // If we've reached this point, there was no violation.
493 memDepViolator = NULL;
499 template <class Impl>
501 LSQUnit<Impl>::commitLoad()
503 assert(loadQueue[loadHead]);
505 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
506 loadQueue[loadHead]->readPC());
508 loadQueue[loadHead] = NULL;
515 template <class Impl>
517 LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
519 assert(loads == 0 || loadQueue[loadHead]);
521 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
526 template <class Impl>
528 LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
530 assert(stores == 0 || storeQueue[storeHead].inst);
532 int store_idx = storeHead;
534 while (store_idx != storeTail) {
535 assert(storeQueue[store_idx].inst);
536 // Mark any stores that are now committed and have not yet
537 // been marked as able to write back.
538 if (!storeQueue[store_idx].canWB) {
539 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
542 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
544 storeQueue[store_idx].inst->readPC(),
545 storeQueue[store_idx].inst->seqNum);
547 storeQueue[store_idx].canWB = true;
552 incrStIdx(store_idx);
556 template <class Impl>
558 LSQUnit<Impl>::writebackStores()
560 while (storesToWB > 0 &&
561 storeWBIdx != storeTail &&
562 storeQueue[storeWBIdx].inst &&
563 storeQueue[storeWBIdx].canWB &&
564 usedPorts < cachePorts) {
566 if (isStoreBlocked || lsq->cacheBlocked()) {
567 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
572 // Store didn't write any data so no need to write it back to
574 if (storeQueue[storeWBIdx].size == 0) {
575 completeStore(storeWBIdx);
577 incrStIdx(storeWBIdx);
584 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
585 incrStIdx(storeWBIdx);
590 assert(storeQueue[storeWBIdx].req);
591 assert(!storeQueue[storeWBIdx].committed);
593 DynInstPtr inst = storeQueue[storeWBIdx].inst;
595 Request *req = storeQueue[storeWBIdx].req;
596 storeQueue[storeWBIdx].committed = true;
598 assert(!inst->memData);
599 inst->memData = new uint8_t[64];
601 TheISA::IntReg convertedData =
602 TheISA::htog(storeQueue[storeWBIdx].data);
604 //FIXME This is a hack to get SPARC working. It, along with endianness
605 //in the memory system in general, need to be straightened out more
606 //formally. The problem is that the data's endianness is swapped when
607 //it's in the 64 bit data field in the store queue. The data that you
608 //want won't start at the beginning of the field anymore unless it was
610 memcpy(inst->memData,
611 (uint8_t *)&convertedData +
612 (TheISA::ByteOrderDiffers ?
613 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
616 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
617 data_pkt->dataStatic(inst->memData);
619 LSQSenderState *state = new LSQSenderState;
620 state->isLoad = false;
621 state->idx = storeWBIdx;
623 data_pkt->senderState = state;
625 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
626 "to Addr:%#x, data:%#x [sn:%lli]\n",
627 storeWBIdx, inst->readPC(),
628 req->getPaddr(), (int)*(inst->memData),
631 // @todo: Remove this SC hack once the memory system handles it.
632 if (req->isLocked()) {
633 // Disable recording the result temporarily. Writing to
634 // misc regs normally updates the result, but this is not
635 // the desired behavior when handling store conditionals.
636 inst->recordResult = false;
637 bool success = TheISA::handleLockedWrite(inst.get(), req);
638 inst->recordResult = true;
641 // Instantly complete this store.
642 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
643 "Instantly completing it.\n",
645 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
646 wb->schedule(curTick + 1);
648 completeStore(storeWBIdx);
649 incrStIdx(storeWBIdx);
653 // Non-store conditionals do not need a writeback.
657 if (!dcachePort->sendTiming(data_pkt)) {
658 if (data_pkt->result == Packet::BadAddress) {
659 panic("LSQ sent out a bad address for a completed store!");
661 // Need to handle becoming blocked on a store.
662 DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will"
665 isStoreBlocked = true;
667 assert(retryPkt == NULL);
669 lsq->setRetryTid(lsqID);
671 storePostSend(data_pkt);
675 // Not sure this should set it to 0.
678 assert(stores >= 0 && storesToWB >= 0);
681 /*template <class Impl>
683 LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
685 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
689 if (mshr_it != mshrSeqNums.end()) {
690 mshrSeqNums.erase(mshr_it);
691 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
695 template <class Impl>
697 LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
699 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
700 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
702 int load_idx = loadTail;
705 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
706 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
708 loadQueue[load_idx]->readPC(),
709 loadQueue[load_idx]->seqNum);
711 if (isStalled() && load_idx == stallingLoadIdx) {
713 stallingStoreIsn = 0;
717 // Clear the smart pointer to make sure it is decremented.
718 loadQueue[load_idx]->setSquashed();
719 loadQueue[load_idx] = NULL;
730 if (squashed_num < blockedLoadSeqNum) {
731 isLoadBlocked = false;
732 loadBlockedHandled = false;
733 blockedLoadSeqNum = 0;
737 int store_idx = storeTail;
738 decrStIdx(store_idx);
740 while (stores != 0 &&
741 storeQueue[store_idx].inst->seqNum > squashed_num) {
742 // Instructions marked as can WB are already committed.
743 if (storeQueue[store_idx].canWB) {
747 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
748 "idx:%i [sn:%lli]\n",
749 storeQueue[store_idx].inst->readPC(),
750 store_idx, storeQueue[store_idx].inst->seqNum);
752 // I don't think this can happen. It should have been cleared
753 // by the stalling load.
755 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
756 panic("Is stalled should have been cleared by stalling load!\n");
758 stallingStoreIsn = 0;
761 // Clear the smart pointer to make sure it is decremented.
762 storeQueue[store_idx].inst->setSquashed();
763 storeQueue[store_idx].inst = NULL;
764 storeQueue[store_idx].canWB = 0;
766 storeQueue[store_idx].req = NULL;
770 storeTail = store_idx;
772 decrStIdx(store_idx);
777 template <class Impl>
779 LSQUnit<Impl>::storePostSend(PacketPtr pkt)
782 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
783 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
785 stallingStoreIsn, stallingLoadIdx);
787 stallingStoreIsn = 0;
788 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
791 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
792 // The store is basically completed at this time. This
793 // only works so long as the checker doesn't try to
794 // verify the value in memory for stores.
795 storeQueue[storeWBIdx].inst->setCompleted();
798 cpu->checker->verify(storeQueue[storeWBIdx].inst);
803 if (pkt->result != Packet::Success) {
804 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
807 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
808 storeQueue[storeWBIdx].inst->seqNum);
810 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
812 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
814 // @todo: Increment stat here.
816 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
819 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
820 storeQueue[storeWBIdx].inst->seqNum);
823 incrStIdx(storeWBIdx);
826 template <class Impl>
828 LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
832 // Squashed instructions do not need to complete their access.
833 if (inst->isSquashed()) {
834 iewStage->decrWb(inst->seqNum);
835 assert(!inst->isStore());
836 ++lsqIgnoredResponses;
840 if (!inst->isExecuted()) {
843 // Complete access to copy data to proper place.
844 inst->completeAcc(pkt);
847 // Need to insert instruction into queue to commit
848 iewStage->instToCommit(inst);
850 iewStage->activityThisCycle();
853 template <class Impl>
855 LSQUnit<Impl>::completeStore(int store_idx)
857 assert(storeQueue[store_idx].inst);
858 storeQueue[store_idx].completed = true;
860 // A bit conservative because a store completion may not free up entries,
861 // but hopefully avoids two store completions in one cycle from making
862 // the CPU tick twice.
864 cpu->activityThisCycle();
866 if (store_idx == storeHead) {
868 incrStIdx(storeHead);
871 } while (storeQueue[storeHead].completed &&
872 storeHead != storeTail);
874 iewStage->updateLSQNextCycle = true;
877 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
879 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
882 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
883 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
885 stallingStoreIsn, stallingLoadIdx);
887 stallingStoreIsn = 0;
888 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
891 storeQueue[store_idx].inst->setCompleted();
893 // Tell the checker we've completed this instruction. Some stores
894 // may get reported twice to the checker, but the checker can
898 cpu->checker->verify(storeQueue[store_idx].inst);
903 template <class Impl>
905 LSQUnit<Impl>::recvRetry()
907 if (isStoreBlocked) {
908 assert(retryPkt != NULL);
910 if (dcachePort->sendTiming(retryPkt)) {
911 if (retryPkt->result == Packet::BadAddress) {
912 panic("LSQ sent out a bad address for a completed store!");
914 storePostSend(retryPkt);
916 isStoreBlocked = false;
917 lsq->setRetryTid(-1);
921 lsq->setRetryTid(lsqID);
923 } else if (isLoadBlocked) {
924 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
925 "no need to resend packet.\n");
927 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
931 template <class Impl>
933 LSQUnit<Impl>::incrStIdx(int &store_idx)
935 if (++store_idx >= SQEntries)
939 template <class Impl>
941 LSQUnit<Impl>::decrStIdx(int &store_idx)
944 store_idx += SQEntries;
947 template <class Impl>
949 LSQUnit<Impl>::incrLdIdx(int &load_idx)
951 if (++load_idx >= LQEntries)
955 template <class Impl>
957 LSQUnit<Impl>::decrLdIdx(int &load_idx)
960 load_idx += LQEntries;
963 template <class Impl>
965 LSQUnit<Impl>::dumpInsts()
967 cprintf("Load store queue: Dumping instructions.\n");
968 cprintf("Load queue size: %i\n", loads);
969 cprintf("Load queue: ");
971 int load_idx = loadHead;
973 while (load_idx != loadTail && loadQueue[load_idx]) {
974 cprintf("%#x ", loadQueue[load_idx]->readPC());
979 cprintf("Store queue size: %i\n", stores);
980 cprintf("Store queue: ");
982 int store_idx = storeHead;
984 while (store_idx != storeTail && storeQueue[store_idx].inst) {
985 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
987 incrStIdx(store_idx);