2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include "arch/locked_mem.hh"
45 #include "config/the_isa.hh"
46 #include "config/use_checker.hh"
47 #include "cpu/o3/lsq.hh"
48 #include "cpu/o3/lsq_unit.hh"
49 #include "base/str.hh"
50 #include "mem/packet.hh"
51 #include "mem/request.hh"
54 #include "cpu/checker/cpu.hh"
58 LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
60 : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
62 this->setFlags(Event::AutoDelete);
67 LSQUnit<Impl>::WritebackEvent::process()
69 if (!lsqPtr->isSwitchedOut()) {
70 lsqPtr->writeback(inst, pkt);
74 delete pkt->senderState;
82 LSQUnit<Impl>::WritebackEvent::description() const
84 return "Store writeback";
89 LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
92 DynInstPtr inst = state->inst;
93 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
94 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
98 assert(!pkt->wasNacked());
100 // If this is a split access, wait until all packets are received.
101 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
107 if (isSwitchedOut() || inst->isSquashed()) {
108 iewStage->decrWb(inst->seqNum);
111 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
113 writeback(inst, pkt);
115 writeback(inst, state->mainPkt);
119 if (inst->isStore()) {
120 completeStore(state->idx);
124 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
125 delete state->mainPkt->req;
126 delete state->mainPkt;
133 template <class Impl>
134 LSQUnit<Impl>::LSQUnit()
135 : loads(0), stores(0), storesToWB(0), stalled(false),
136 isStoreBlocked(false), isLoadBlocked(false),
137 loadBlockedHandled(false), hasPendingPkt(false)
143 LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
144 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
150 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
158 // Add 1 for the sentinel entry (they are circular queues).
159 LQEntries = maxLQEntries + 1;
160 SQEntries = maxSQEntries + 1;
162 loadQueue.resize(LQEntries);
163 storeQueue.resize(SQEntries);
165 loadHead = loadTail = 0;
167 storeHead = storeWBIdx = storeTail = 0;
170 cachePorts = params->cachePorts;
173 memDepViolator = NULL;
175 blockedLoadSeqNum = 0;
180 LSQUnit<Impl>::name() const
182 if (Impl::MaxThreads == 1) {
183 return iewStage->name() + ".lsq";
185 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
191 LSQUnit<Impl>::regStats()
194 .name(name() + ".forwLoads")
195 .desc("Number of loads that had data forwarded from stores");
198 .name(name() + ".invAddrLoads")
199 .desc("Number of loads ignored due to an invalid address");
202 .name(name() + ".squashedLoads")
203 .desc("Number of loads squashed");
206 .name(name() + ".ignoredResponses")
207 .desc("Number of memory responses ignored because the instruction is squashed");
210 .name(name() + ".memOrderViolation")
211 .desc("Number of memory ordering violations");
214 .name(name() + ".squashedStores")
215 .desc("Number of stores squashed");
218 .name(name() + ".invAddrSwpfs")
219 .desc("Number of software prefetches ignored due to an invalid address");
222 .name(name() + ".blockedLoads")
223 .desc("Number of blocked loads due to partial load-store forwarding");
226 .name(name() + ".rescheduledLoads")
227 .desc("Number of loads that were rescheduled");
230 .name(name() + ".cacheBlocked")
231 .desc("Number of times an access to memory failed due to the cache being blocked");
236 LSQUnit<Impl>::setDcachePort(Port *dcache_port)
238 dcachePort = dcache_port;
242 cpu->checker->setDcachePort(dcachePort);
249 LSQUnit<Impl>::clearLQ()
256 LSQUnit<Impl>::clearSQ()
263 LSQUnit<Impl>::switchOut()
266 for (int i = 0; i < loadQueue.size(); ++i) {
267 assert(!loadQueue[i]);
271 assert(storesToWB == 0);
276 LSQUnit<Impl>::takeOverFrom()
279 loads = stores = storesToWB = 0;
281 loadHead = loadTail = 0;
283 storeHead = storeWBIdx = storeTail = 0;
287 memDepViolator = NULL;
289 blockedLoadSeqNum = 0;
292 isLoadBlocked = false;
293 loadBlockedHandled = false;
298 LSQUnit<Impl>::resizeLQ(unsigned size)
300 unsigned size_plus_sentinel = size + 1;
301 assert(size_plus_sentinel >= LQEntries);
303 if (size_plus_sentinel > LQEntries) {
304 while (size_plus_sentinel > loadQueue.size()) {
306 loadQueue.push_back(dummy);
310 LQEntries = size_plus_sentinel;
317 LSQUnit<Impl>::resizeSQ(unsigned size)
319 unsigned size_plus_sentinel = size + 1;
320 if (size_plus_sentinel > SQEntries) {
321 while (size_plus_sentinel > storeQueue.size()) {
323 storeQueue.push_back(dummy);
327 SQEntries = size_plus_sentinel;
331 template <class Impl>
333 LSQUnit<Impl>::insert(DynInstPtr &inst)
335 assert(inst->isMemRef());
337 assert(inst->isLoad() || inst->isStore());
339 if (inst->isLoad()) {
348 template <class Impl>
350 LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
352 assert((loadTail + 1) % LQEntries != loadHead);
353 assert(loads < LQEntries);
355 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
356 load_inst->pcState(), loadTail, load_inst->seqNum);
358 load_inst->lqIdx = loadTail;
361 load_inst->sqIdx = -1;
363 load_inst->sqIdx = storeTail;
366 loadQueue[loadTail] = load_inst;
373 template <class Impl>
375 LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
377 // Make sure it is not full before inserting an instruction.
378 assert((storeTail + 1) % SQEntries != storeHead);
379 assert(stores < SQEntries);
381 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
382 store_inst->pcState(), storeTail, store_inst->seqNum);
384 store_inst->sqIdx = storeTail;
385 store_inst->lqIdx = loadTail;
387 storeQueue[storeTail] = SQEntry(store_inst);
389 incrStIdx(storeTail);
394 template <class Impl>
395 typename Impl::DynInstPtr
396 LSQUnit<Impl>::getMemDepViolator()
398 DynInstPtr temp = memDepViolator;
400 memDepViolator = NULL;
405 template <class Impl>
407 LSQUnit<Impl>::numFreeEntries()
409 unsigned free_lq_entries = LQEntries - loads;
410 unsigned free_sq_entries = SQEntries - stores;
412 // Both the LQ and SQ entries have an extra dummy entry to differentiate
413 // empty/full conditions. Subtract 1 from the free entries.
414 if (free_lq_entries < free_sq_entries) {
415 return free_lq_entries - 1;
417 return free_sq_entries - 1;
421 template <class Impl>
423 LSQUnit<Impl>::numLoadsReady()
425 int load_idx = loadHead;
428 while (load_idx != loadTail) {
429 assert(loadQueue[load_idx]);
431 if (loadQueue[load_idx]->readyToIssue()) {
439 template <class Impl>
441 LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
443 using namespace TheISA;
444 // Execute a specific load.
445 Fault load_fault = NoFault;
447 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
448 inst->pcState(),inst->seqNum);
450 assert(!inst->isSquashed());
452 load_fault = inst->initiateAcc();
454 // If the instruction faulted or predicated false, then we need to send it
455 // along to commit without the instruction completing.
456 if (load_fault != NoFault || inst->readPredicate() == false) {
457 // Send this instruction to commit, also make sure iew stage
458 // realizes there is activity.
459 // Mark it as executed unless it is an uncached load that
460 // needs to hit the head of commit.
461 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
463 (load_fault != NoFault ? "fault" : "predication"));
464 if (!(inst->hasRequest() && inst->uncacheable()) ||
465 inst->isAtCommit()) {
468 iewStage->instToCommit(inst);
469 iewStage->activityThisCycle();
470 } else if (!loadBlocked()) {
471 assert(inst->effAddrValid);
472 int load_idx = inst->lqIdx;
474 while (load_idx != loadTail) {
475 // Really only need to check loads that have actually executed
477 // @todo: For now this is extra conservative, detecting a
478 // violation if the addresses match assuming all accesses
479 // are quad word accesses.
481 // @todo: Fix this, magic number being used here
483 // @todo: Uncachable load is not executed until it reaches
484 // the head of the ROB. Once this if checks only the executed
485 // loads(as noted above), this check can be removed
486 if (loadQueue[load_idx]->effAddrValid &&
487 ((loadQueue[load_idx]->effAddr >> 8)
488 == (inst->effAddr >> 8)) &&
489 !loadQueue[load_idx]->uncacheable()) {
490 // A load incorrectly passed this load. Squash and refetch.
491 // For now return a fault to show that it was unsuccessful.
492 DynInstPtr violator = loadQueue[load_idx];
493 if (!memDepViolator ||
494 (violator->seqNum < memDepViolator->seqNum)) {
495 memDepViolator = violator;
500 ++lsqMemOrderViolation;
502 return genMachineCheckFault();
512 template <class Impl>
514 LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
516 using namespace TheISA;
517 // Make sure that a store exists.
520 int store_idx = store_inst->sqIdx;
522 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
523 store_inst->pcState(), store_inst->seqNum);
525 assert(!store_inst->isSquashed());
527 // Check the recently completed loads to see if any match this store's
528 // address. If so, then we have a memory ordering violation.
529 int load_idx = store_inst->lqIdx;
531 Fault store_fault = store_inst->initiateAcc();
533 if (storeQueue[store_idx].size == 0) {
534 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
535 store_inst->pcState(), store_inst->seqNum);
538 } else if (store_inst->readPredicate() == false) {
539 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
544 assert(store_fault == NoFault);
546 if (store_inst->isStoreConditional()) {
547 // Store conditionals need to set themselves as able to
548 // writeback if we haven't had a fault by here.
549 storeQueue[store_idx].canWB = true;
554 assert(store_inst->effAddrValid);
555 while (load_idx != loadTail) {
556 // Really only need to check loads that have actually executed
557 // It's safe to check all loads because effAddr is set to
558 // InvalAddr when the dyn inst is created.
560 // @todo: For now this is extra conservative, detecting a
561 // violation if the addresses match assuming all accesses
562 // are quad word accesses.
564 // @todo: Fix this, magic number being used here
566 // @todo: Uncachable load is not executed until it reaches
567 // the head of the ROB. Once this if checks only the executed
568 // loads(as noted above), this check can be removed
569 if (loadQueue[load_idx]->effAddrValid &&
570 ((loadQueue[load_idx]->effAddr >> 8)
571 == (store_inst->effAddr >> 8)) &&
572 !loadQueue[load_idx]->uncacheable()) {
573 // A load incorrectly passed this store. Squash and refetch.
574 // For now return a fault to show that it was unsuccessful.
575 DynInstPtr violator = loadQueue[load_idx];
576 if (!memDepViolator ||
577 (violator->seqNum < memDepViolator->seqNum)) {
578 memDepViolator = violator;
583 ++lsqMemOrderViolation;
585 return genMachineCheckFault();
594 template <class Impl>
596 LSQUnit<Impl>::commitLoad()
598 assert(loadQueue[loadHead]);
600 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
601 loadQueue[loadHead]->pcState());
603 loadQueue[loadHead] = NULL;
610 template <class Impl>
612 LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
614 assert(loads == 0 || loadQueue[loadHead]);
616 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
621 template <class Impl>
623 LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
625 assert(stores == 0 || storeQueue[storeHead].inst);
627 int store_idx = storeHead;
629 while (store_idx != storeTail) {
630 assert(storeQueue[store_idx].inst);
631 // Mark any stores that are now committed and have not yet
632 // been marked as able to write back.
633 if (!storeQueue[store_idx].canWB) {
634 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
637 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
639 storeQueue[store_idx].inst->pcState(),
640 storeQueue[store_idx].inst->seqNum);
642 storeQueue[store_idx].canWB = true;
647 incrStIdx(store_idx);
651 template <class Impl>
653 LSQUnit<Impl>::writebackPendingStore()
656 assert(pendingPkt != NULL);
658 // If the cache is blocked, this will store the packet for retry.
659 if (sendStore(pendingPkt)) {
660 storePostSend(pendingPkt);
663 hasPendingPkt = false;
667 template <class Impl>
669 LSQUnit<Impl>::writebackStores()
671 // First writeback the second packet from any split store that didn't
672 // complete last cycle because there weren't enough cache ports available.
673 if (TheISA::HasUnalignedMemAcc) {
674 writebackPendingStore();
677 while (storesToWB > 0 &&
678 storeWBIdx != storeTail &&
679 storeQueue[storeWBIdx].inst &&
680 storeQueue[storeWBIdx].canWB &&
681 usedPorts < cachePorts) {
683 if (isStoreBlocked || lsq->cacheBlocked()) {
684 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
689 // Store didn't write any data so no need to write it back to
691 if (storeQueue[storeWBIdx].size == 0) {
692 completeStore(storeWBIdx);
694 incrStIdx(storeWBIdx);
701 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
702 incrStIdx(storeWBIdx);
707 assert(storeQueue[storeWBIdx].req);
708 assert(!storeQueue[storeWBIdx].committed);
710 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
711 assert(storeQueue[storeWBIdx].sreqLow);
712 assert(storeQueue[storeWBIdx].sreqHigh);
715 DynInstPtr inst = storeQueue[storeWBIdx].inst;
717 Request *req = storeQueue[storeWBIdx].req;
718 storeQueue[storeWBIdx].committed = true;
720 assert(!inst->memData);
721 inst->memData = new uint8_t[64];
723 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
726 req->isSwap() ? MemCmd::SwapReq :
727 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
729 PacketPtr snd_data_pkt = NULL;
731 LSQSenderState *state = new LSQSenderState;
732 state->isLoad = false;
733 state->idx = storeWBIdx;
736 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
738 // Build a single data packet if the store isn't split.
739 data_pkt = new Packet(req, command, Packet::Broadcast);
740 data_pkt->dataStatic(inst->memData);
741 data_pkt->senderState = state;
743 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
744 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
746 // Create two packets if the store is split in two.
747 data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
748 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
750 data_pkt->dataStatic(inst->memData);
751 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
753 data_pkt->senderState = state;
754 snd_data_pkt->senderState = state;
756 state->isSplit = true;
757 state->outstanding = 2;
759 // Can delete the main request now.
764 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
765 "to Addr:%#x, data:%#x [sn:%lli]\n",
766 storeWBIdx, inst->pcState(),
767 req->getPaddr(), (int)*(inst->memData),
770 // @todo: Remove this SC hack once the memory system handles it.
771 if (inst->isStoreConditional()) {
772 assert(!storeQueue[storeWBIdx].isSplit);
773 // Disable recording the result temporarily. Writing to
774 // misc regs normally updates the result, but this is not
775 // the desired behavior when handling store conditionals.
776 inst->recordResult = false;
777 bool success = TheISA::handleLockedWrite(inst.get(), req);
778 inst->recordResult = true;
781 // Instantly complete this store.
782 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
783 "Instantly completing it.\n",
785 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
786 cpu->schedule(wb, curTick + 1);
787 completeStore(storeWBIdx);
788 incrStIdx(storeWBIdx);
792 // Non-store conditionals do not need a writeback.
796 if (!sendStore(data_pkt)) {
797 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
801 // Need to store the second packet, if split.
802 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
803 state->pktToSend = true;
804 state->pendingPacket = snd_data_pkt;
808 // If split, try to send the second packet too
809 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
810 assert(snd_data_pkt);
812 // Ensure there are enough ports to use.
813 if (usedPorts < cachePorts) {
815 if (sendStore(snd_data_pkt)) {
816 storePostSend(snd_data_pkt);
818 DPRINTF(IEW, "D-Cache became blocked when writing"
819 " [sn:%lli] second packet, will retry later\n",
824 // Store the packet for when there's free ports.
825 assert(pendingPkt == NULL);
826 pendingPkt = snd_data_pkt;
827 hasPendingPkt = true;
831 // Not a split store.
832 storePostSend(data_pkt);
837 // Not sure this should set it to 0.
840 assert(stores >= 0 && storesToWB >= 0);
843 /*template <class Impl>
845 LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
847 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
851 if (mshr_it != mshrSeqNums.end()) {
852 mshrSeqNums.erase(mshr_it);
853 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
857 template <class Impl>
859 LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
861 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
862 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
864 int load_idx = loadTail;
867 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
868 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
870 loadQueue[load_idx]->pcState(),
871 loadQueue[load_idx]->seqNum);
873 if (isStalled() && load_idx == stallingLoadIdx) {
875 stallingStoreIsn = 0;
879 // Clear the smart pointer to make sure it is decremented.
880 loadQueue[load_idx]->setSquashed();
881 loadQueue[load_idx] = NULL;
892 if (squashed_num < blockedLoadSeqNum) {
893 isLoadBlocked = false;
894 loadBlockedHandled = false;
895 blockedLoadSeqNum = 0;
899 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
900 memDepViolator = NULL;
903 int store_idx = storeTail;
904 decrStIdx(store_idx);
906 while (stores != 0 &&
907 storeQueue[store_idx].inst->seqNum > squashed_num) {
908 // Instructions marked as can WB are already committed.
909 if (storeQueue[store_idx].canWB) {
913 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
914 "idx:%i [sn:%lli]\n",
915 storeQueue[store_idx].inst->pcState(),
916 store_idx, storeQueue[store_idx].inst->seqNum);
918 // I don't think this can happen. It should have been cleared
919 // by the stalling load.
921 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
922 panic("Is stalled should have been cleared by stalling load!\n");
924 stallingStoreIsn = 0;
927 // Clear the smart pointer to make sure it is decremented.
928 storeQueue[store_idx].inst->setSquashed();
929 storeQueue[store_idx].inst = NULL;
930 storeQueue[store_idx].canWB = 0;
932 // Must delete request now that it wasn't handed off to
933 // memory. This is quite ugly. @todo: Figure out the proper
934 // place to really handle request deletes.
935 delete storeQueue[store_idx].req;
936 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
937 delete storeQueue[store_idx].sreqLow;
938 delete storeQueue[store_idx].sreqHigh;
940 storeQueue[store_idx].sreqLow = NULL;
941 storeQueue[store_idx].sreqHigh = NULL;
944 storeQueue[store_idx].req = NULL;
948 storeTail = store_idx;
950 decrStIdx(store_idx);
955 template <class Impl>
957 LSQUnit<Impl>::storePostSend(PacketPtr pkt)
960 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
961 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
963 stallingStoreIsn, stallingLoadIdx);
965 stallingStoreIsn = 0;
966 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
969 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
970 // The store is basically completed at this time. This
971 // only works so long as the checker doesn't try to
972 // verify the value in memory for stores.
973 storeQueue[storeWBIdx].inst->setCompleted();
976 cpu->checker->verify(storeQueue[storeWBIdx].inst);
981 incrStIdx(storeWBIdx);
984 template <class Impl>
986 LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
990 // Squashed instructions do not need to complete their access.
991 if (inst->isSquashed()) {
992 iewStage->decrWb(inst->seqNum);
993 assert(!inst->isStore());
994 ++lsqIgnoredResponses;
998 if (!inst->isExecuted()) {
1001 // Complete access to copy data to proper place.
1002 inst->completeAcc(pkt);
1005 // Need to insert instruction into queue to commit
1006 iewStage->instToCommit(inst);
1008 iewStage->activityThisCycle();
1010 // see if this load changed the PC
1011 iewStage->checkMisprediction(inst);
1014 template <class Impl>
1016 LSQUnit<Impl>::completeStore(int store_idx)
1018 assert(storeQueue[store_idx].inst);
1019 storeQueue[store_idx].completed = true;
1021 // A bit conservative because a store completion may not free up entries,
1022 // but hopefully avoids two store completions in one cycle from making
1023 // the CPU tick twice.
1025 cpu->activityThisCycle();
1027 if (store_idx == storeHead) {
1029 incrStIdx(storeHead);
1032 } while (storeQueue[storeHead].completed &&
1033 storeHead != storeTail);
1035 iewStage->updateLSQNextCycle = true;
1038 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1040 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1043 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1044 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1046 stallingStoreIsn, stallingLoadIdx);
1048 stallingStoreIsn = 0;
1049 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1052 storeQueue[store_idx].inst->setCompleted();
1054 // Tell the checker we've completed this instruction. Some stores
1055 // may get reported twice to the checker, but the checker can
1056 // handle that case.
1059 cpu->checker->verify(storeQueue[store_idx].inst);
1064 template <class Impl>
1066 LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1068 if (!dcachePort->sendTiming(data_pkt)) {
1069 // Need to handle becoming blocked on a store.
1070 isStoreBlocked = true;
1072 assert(retryPkt == NULL);
1073 retryPkt = data_pkt;
1074 lsq->setRetryTid(lsqID);
1080 template <class Impl>
1082 LSQUnit<Impl>::recvRetry()
1084 if (isStoreBlocked) {
1085 DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
1086 assert(retryPkt != NULL);
1088 if (dcachePort->sendTiming(retryPkt)) {
1089 LSQSenderState *state =
1090 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
1092 // Don't finish the store unless this is the last packet.
1093 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
1094 storePostSend(retryPkt);
1097 isStoreBlocked = false;
1098 lsq->setRetryTid(InvalidThreadID);
1100 // Send any outstanding packet.
1101 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1102 assert(state->pendingPacket);
1103 if (sendStore(state->pendingPacket)) {
1104 storePostSend(state->pendingPacket);
1110 lsq->setRetryTid(lsqID);
1112 } else if (isLoadBlocked) {
1113 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
1114 "no need to resend packet.\n");
1116 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
1120 template <class Impl>
1122 LSQUnit<Impl>::incrStIdx(int &store_idx)
1124 if (++store_idx >= SQEntries)
1128 template <class Impl>
1130 LSQUnit<Impl>::decrStIdx(int &store_idx)
1132 if (--store_idx < 0)
1133 store_idx += SQEntries;
1136 template <class Impl>
1138 LSQUnit<Impl>::incrLdIdx(int &load_idx)
1140 if (++load_idx >= LQEntries)
1144 template <class Impl>
1146 LSQUnit<Impl>::decrLdIdx(int &load_idx)
1149 load_idx += LQEntries;
1152 template <class Impl>
1154 LSQUnit<Impl>::dumpInsts()
1156 cprintf("Load store queue: Dumping instructions.\n");
1157 cprintf("Load queue size: %i\n", loads);
1158 cprintf("Load queue: ");
1160 int load_idx = loadHead;
1162 while (load_idx != loadTail && loadQueue[load_idx]) {
1163 cprintf("%s ", loadQueue[load_idx]->pcState());
1165 incrLdIdx(load_idx);
1168 cprintf("Store queue size: %i\n", stores);
1169 cprintf("Store queue: ");
1171 int store_idx = storeHead;
1173 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1174 cprintf("%s ", storeQueue[store_idx].inst->pcState());
1176 incrStIdx(store_idx);