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32 #include "arch/locked_mem.hh"
33 #include "config/use_checker.hh"
35 #include "cpu/o3/lsq.hh"
36 #include "cpu/o3/lsq_unit.hh"
37 #include "base/str.hh"
38 #include "mem/packet.hh"
39 #include "mem/request.hh"
42 #include "cpu/checker/cpu.hh"
46 LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
48 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
50 this->setFlags(Event::AutoDelete);
55 LSQUnit<Impl>::WritebackEvent::process()
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
62 delete pkt->senderState;
70 LSQUnit<Impl>::WritebackEvent::description()
72 return "Store writeback event";
77 LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
79 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
80 DynInstPtr inst = state->inst;
81 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
82 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
84 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
86 if (isSwitchedOut() || inst->isSquashed()) {
87 iewStage->decrWb(inst->seqNum);
93 if (inst->isStore()) {
94 completeStore(state->idx);
103 template <class Impl>
104 LSQUnit<Impl>::LSQUnit()
105 : loads(0), stores(0), storesToWB(0), stalled(false),
106 isStoreBlocked(false), isLoadBlocked(false),
107 loadBlockedHandled(false)
113 LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
114 unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
119 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
127 // Add 1 for the sentinel entry (they are circular queues).
128 LQEntries = maxLQEntries + 1;
129 SQEntries = maxSQEntries + 1;
131 loadQueue.resize(LQEntries);
132 storeQueue.resize(SQEntries);
134 loadHead = loadTail = 0;
136 storeHead = storeWBIdx = storeTail = 0;
139 cachePorts = params->cachePorts;
142 memDepViolator = NULL;
144 blockedLoadSeqNum = 0;
149 LSQUnit<Impl>::name() const
151 if (Impl::MaxThreads == 1) {
152 return iewStage->name() + ".lsq";
154 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
160 LSQUnit<Impl>::regStats()
163 .name(name() + ".forwLoads")
164 .desc("Number of loads that had data forwarded from stores");
167 .name(name() + ".invAddrLoads")
168 .desc("Number of loads ignored due to an invalid address");
171 .name(name() + ".squashedLoads")
172 .desc("Number of loads squashed");
175 .name(name() + ".ignoredResponses")
176 .desc("Number of memory responses ignored because the instruction is squashed");
179 .name(name() + ".memOrderViolation")
180 .desc("Number of memory ordering violations");
183 .name(name() + ".squashedStores")
184 .desc("Number of stores squashed");
187 .name(name() + ".invAddrSwpfs")
188 .desc("Number of software prefetches ignored due to an invalid address");
191 .name(name() + ".blockedLoads")
192 .desc("Number of blocked loads due to partial load-store forwarding");
195 .name(name() + ".rescheduledLoads")
196 .desc("Number of loads that were rescheduled");
199 .name(name() + ".cacheBlocked")
200 .desc("Number of times an access to memory failed due to the cache being blocked");
205 LSQUnit<Impl>::setDcachePort(Port *dcache_port)
207 dcachePort = dcache_port;
211 cpu->checker->setDcachePort(dcachePort);
218 LSQUnit<Impl>::clearLQ()
225 LSQUnit<Impl>::clearSQ()
232 LSQUnit<Impl>::switchOut()
235 for (int i = 0; i < loadQueue.size(); ++i) {
236 assert(!loadQueue[i]);
240 assert(storesToWB == 0);
245 LSQUnit<Impl>::takeOverFrom()
248 loads = stores = storesToWB = 0;
250 loadHead = loadTail = 0;
252 storeHead = storeWBIdx = storeTail = 0;
256 memDepViolator = NULL;
258 blockedLoadSeqNum = 0;
261 isLoadBlocked = false;
262 loadBlockedHandled = false;
267 LSQUnit<Impl>::resizeLQ(unsigned size)
269 unsigned size_plus_sentinel = size + 1;
270 assert(size_plus_sentinel >= LQEntries);
272 if (size_plus_sentinel > LQEntries) {
273 while (size_plus_sentinel > loadQueue.size()) {
275 loadQueue.push_back(dummy);
279 LQEntries = size_plus_sentinel;
286 LSQUnit<Impl>::resizeSQ(unsigned size)
288 unsigned size_plus_sentinel = size + 1;
289 if (size_plus_sentinel > SQEntries) {
290 while (size_plus_sentinel > storeQueue.size()) {
292 storeQueue.push_back(dummy);
296 SQEntries = size_plus_sentinel;
300 template <class Impl>
302 LSQUnit<Impl>::insert(DynInstPtr &inst)
304 assert(inst->isMemRef());
306 assert(inst->isLoad() || inst->isStore());
308 if (inst->isLoad()) {
317 template <class Impl>
319 LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
321 assert((loadTail + 1) % LQEntries != loadHead);
322 assert(loads < LQEntries);
324 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
325 load_inst->readPC(), loadTail, load_inst->seqNum);
327 load_inst->lqIdx = loadTail;
330 load_inst->sqIdx = -1;
332 load_inst->sqIdx = storeTail;
335 loadQueue[loadTail] = load_inst;
342 template <class Impl>
344 LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
346 // Make sure it is not full before inserting an instruction.
347 assert((storeTail + 1) % SQEntries != storeHead);
348 assert(stores < SQEntries);
350 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
351 store_inst->readPC(), storeTail, store_inst->seqNum);
353 store_inst->sqIdx = storeTail;
354 store_inst->lqIdx = loadTail;
356 storeQueue[storeTail] = SQEntry(store_inst);
358 incrStIdx(storeTail);
363 template <class Impl>
364 typename Impl::DynInstPtr
365 LSQUnit<Impl>::getMemDepViolator()
367 DynInstPtr temp = memDepViolator;
369 memDepViolator = NULL;
374 template <class Impl>
376 LSQUnit<Impl>::numFreeEntries()
378 unsigned free_lq_entries = LQEntries - loads;
379 unsigned free_sq_entries = SQEntries - stores;
381 // Both the LQ and SQ entries have an extra dummy entry to differentiate
382 // empty/full conditions. Subtract 1 from the free entries.
383 if (free_lq_entries < free_sq_entries) {
384 return free_lq_entries - 1;
386 return free_sq_entries - 1;
390 template <class Impl>
392 LSQUnit<Impl>::numLoadsReady()
394 int load_idx = loadHead;
397 while (load_idx != loadTail) {
398 assert(loadQueue[load_idx]);
400 if (loadQueue[load_idx]->readyToIssue()) {
408 template <class Impl>
410 LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
412 using namespace TheISA;
413 // Execute a specific load.
414 Fault load_fault = NoFault;
416 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
417 inst->readPC(),inst->seqNum);
419 assert(!inst->isSquashed());
421 load_fault = inst->initiateAcc();
423 // If the instruction faulted, then we need to send it along to commit
424 // without the instruction completing.
425 if (load_fault != NoFault) {
426 // Send this instruction to commit, also make sure iew stage
427 // realizes there is activity.
428 // Mark it as executed unless it is an uncached load that
429 // needs to hit the head of commit.
430 if (!(inst->hasRequest() && inst->uncacheable()) ||
431 inst->isAtCommit()) {
434 iewStage->instToCommit(inst);
435 iewStage->activityThisCycle();
436 } else if (!loadBlocked()) {
437 assert(inst->effAddrValid);
438 int load_idx = inst->lqIdx;
440 while (load_idx != loadTail) {
441 // Really only need to check loads that have actually executed
443 // @todo: For now this is extra conservative, detecting a
444 // violation if the addresses match assuming all accesses
445 // are quad word accesses.
447 // @todo: Fix this, magic number being used here
448 if (loadQueue[load_idx]->effAddrValid &&
449 (loadQueue[load_idx]->effAddr >> 8) ==
450 (inst->effAddr >> 8)) {
451 // A load incorrectly passed this load. Squash and refetch.
452 // For now return a fault to show that it was unsuccessful.
453 DynInstPtr violator = loadQueue[load_idx];
454 if (!memDepViolator ||
455 (violator->seqNum < memDepViolator->seqNum)) {
456 memDepViolator = violator;
461 ++lsqMemOrderViolation;
463 return genMachineCheckFault();
473 template <class Impl>
475 LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
477 using namespace TheISA;
478 // Make sure that a store exists.
481 int store_idx = store_inst->sqIdx;
483 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
484 store_inst->readPC(), store_inst->seqNum);
486 assert(!store_inst->isSquashed());
488 // Check the recently completed loads to see if any match this store's
489 // address. If so, then we have a memory ordering violation.
490 int load_idx = store_inst->lqIdx;
492 Fault store_fault = store_inst->initiateAcc();
494 if (storeQueue[store_idx].size == 0) {
495 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
496 store_inst->readPC(),store_inst->seqNum);
501 assert(store_fault == NoFault);
503 if (store_inst->isStoreConditional()) {
504 // Store conditionals need to set themselves as able to
505 // writeback if we haven't had a fault by here.
506 storeQueue[store_idx].canWB = true;
511 assert(store_inst->effAddrValid);
512 while (load_idx != loadTail) {
513 // Really only need to check loads that have actually executed
514 // It's safe to check all loads because effAddr is set to
515 // InvalAddr when the dyn inst is created.
517 // @todo: For now this is extra conservative, detecting a
518 // violation if the addresses match assuming all accesses
519 // are quad word accesses.
521 // @todo: Fix this, magic number being used here
522 if (loadQueue[load_idx]->effAddrValid &&
523 (loadQueue[load_idx]->effAddr >> 8) ==
524 (store_inst->effAddr >> 8)) {
525 // A load incorrectly passed this store. Squash and refetch.
526 // For now return a fault to show that it was unsuccessful.
527 DynInstPtr violator = loadQueue[load_idx];
528 if (!memDepViolator ||
529 (violator->seqNum < memDepViolator->seqNum)) {
530 memDepViolator = violator;
535 ++lsqMemOrderViolation;
537 return genMachineCheckFault();
546 template <class Impl>
548 LSQUnit<Impl>::commitLoad()
550 assert(loadQueue[loadHead]);
552 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
553 loadQueue[loadHead]->readPC());
555 loadQueue[loadHead] = NULL;
562 template <class Impl>
564 LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
566 assert(loads == 0 || loadQueue[loadHead]);
568 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
573 template <class Impl>
575 LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
577 assert(stores == 0 || storeQueue[storeHead].inst);
579 int store_idx = storeHead;
581 while (store_idx != storeTail) {
582 assert(storeQueue[store_idx].inst);
583 // Mark any stores that are now committed and have not yet
584 // been marked as able to write back.
585 if (!storeQueue[store_idx].canWB) {
586 if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
589 DPRINTF(LSQUnit, "Marking store as able to write back, PC "
591 storeQueue[store_idx].inst->readPC(),
592 storeQueue[store_idx].inst->seqNum);
594 storeQueue[store_idx].canWB = true;
599 incrStIdx(store_idx);
603 template <class Impl>
605 LSQUnit<Impl>::writebackStores()
607 while (storesToWB > 0 &&
608 storeWBIdx != storeTail &&
609 storeQueue[storeWBIdx].inst &&
610 storeQueue[storeWBIdx].canWB &&
611 usedPorts < cachePorts) {
613 if (isStoreBlocked || lsq->cacheBlocked()) {
614 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
619 // Store didn't write any data so no need to write it back to
621 if (storeQueue[storeWBIdx].size == 0) {
622 completeStore(storeWBIdx);
624 incrStIdx(storeWBIdx);
631 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
632 incrStIdx(storeWBIdx);
637 assert(storeQueue[storeWBIdx].req);
638 assert(!storeQueue[storeWBIdx].committed);
640 DynInstPtr inst = storeQueue[storeWBIdx].inst;
642 Request *req = storeQueue[storeWBIdx].req;
643 storeQueue[storeWBIdx].committed = true;
645 assert(!inst->memData);
646 inst->memData = new uint8_t[64];
648 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
650 MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq;
651 PacketPtr data_pkt = new Packet(req, command,
653 data_pkt->dataStatic(inst->memData);
655 LSQSenderState *state = new LSQSenderState;
656 state->isLoad = false;
657 state->idx = storeWBIdx;
659 data_pkt->senderState = state;
661 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
662 "to Addr:%#x, data:%#x [sn:%lli]\n",
663 storeWBIdx, inst->readPC(),
664 req->getPaddr(), (int)*(inst->memData),
667 // @todo: Remove this SC hack once the memory system handles it.
668 if (inst->isStoreConditional()) {
669 // Disable recording the result temporarily. Writing to
670 // misc regs normally updates the result, but this is not
671 // the desired behavior when handling store conditionals.
672 inst->recordResult = false;
673 bool success = TheISA::handleLockedWrite(inst.get(), req);
674 inst->recordResult = true;
677 // Instantly complete this store.
678 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
679 "Instantly completing it.\n",
681 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
682 wb->schedule(curTick + 1);
684 completeStore(storeWBIdx);
685 incrStIdx(storeWBIdx);
689 // Non-store conditionals do not need a writeback.
693 if (!dcachePort->sendTiming(data_pkt)) {
694 if (data_pkt->result == Packet::BadAddress) {
695 panic("LSQ sent out a bad address for a completed store!");
697 // Need to handle becoming blocked on a store.
698 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
701 isStoreBlocked = true;
703 assert(retryPkt == NULL);
705 lsq->setRetryTid(lsqID);
707 storePostSend(data_pkt);
711 // Not sure this should set it to 0.
714 assert(stores >= 0 && storesToWB >= 0);
717 /*template <class Impl>
719 LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
721 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
725 if (mshr_it != mshrSeqNums.end()) {
726 mshrSeqNums.erase(mshr_it);
727 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
731 template <class Impl>
733 LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
735 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
736 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
738 int load_idx = loadTail;
741 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
742 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
744 loadQueue[load_idx]->readPC(),
745 loadQueue[load_idx]->seqNum);
747 if (isStalled() && load_idx == stallingLoadIdx) {
749 stallingStoreIsn = 0;
753 // Clear the smart pointer to make sure it is decremented.
754 loadQueue[load_idx]->setSquashed();
755 loadQueue[load_idx] = NULL;
766 if (squashed_num < blockedLoadSeqNum) {
767 isLoadBlocked = false;
768 loadBlockedHandled = false;
769 blockedLoadSeqNum = 0;
773 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
774 memDepViolator = NULL;
777 int store_idx = storeTail;
778 decrStIdx(store_idx);
780 while (stores != 0 &&
781 storeQueue[store_idx].inst->seqNum > squashed_num) {
782 // Instructions marked as can WB are already committed.
783 if (storeQueue[store_idx].canWB) {
787 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
788 "idx:%i [sn:%lli]\n",
789 storeQueue[store_idx].inst->readPC(),
790 store_idx, storeQueue[store_idx].inst->seqNum);
792 // I don't think this can happen. It should have been cleared
793 // by the stalling load.
795 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
796 panic("Is stalled should have been cleared by stalling load!\n");
798 stallingStoreIsn = 0;
801 // Clear the smart pointer to make sure it is decremented.
802 storeQueue[store_idx].inst->setSquashed();
803 storeQueue[store_idx].inst = NULL;
804 storeQueue[store_idx].canWB = 0;
806 // Must delete request now that it wasn't handed off to
807 // memory. This is quite ugly. @todo: Figure out the proper
808 // place to really handle request deletes.
809 delete storeQueue[store_idx].req;
811 storeQueue[store_idx].req = NULL;
815 storeTail = store_idx;
817 decrStIdx(store_idx);
822 template <class Impl>
824 LSQUnit<Impl>::storePostSend(PacketPtr pkt)
827 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
828 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
830 stallingStoreIsn, stallingLoadIdx);
832 stallingStoreIsn = 0;
833 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
836 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
837 // The store is basically completed at this time. This
838 // only works so long as the checker doesn't try to
839 // verify the value in memory for stores.
840 storeQueue[storeWBIdx].inst->setCompleted();
843 cpu->checker->verify(storeQueue[storeWBIdx].inst);
848 if (pkt->result != Packet::Success) {
849 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
852 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
853 storeQueue[storeWBIdx].inst->seqNum);
855 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
857 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
859 // @todo: Increment stat here.
861 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
864 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
865 storeQueue[storeWBIdx].inst->seqNum);
868 incrStIdx(storeWBIdx);
871 template <class Impl>
873 LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
877 // Squashed instructions do not need to complete their access.
878 if (inst->isSquashed()) {
879 iewStage->decrWb(inst->seqNum);
880 assert(!inst->isStore());
881 ++lsqIgnoredResponses;
885 if (!inst->isExecuted()) {
888 // Complete access to copy data to proper place.
889 inst->completeAcc(pkt);
892 // Need to insert instruction into queue to commit
893 iewStage->instToCommit(inst);
895 iewStage->activityThisCycle();
898 template <class Impl>
900 LSQUnit<Impl>::completeStore(int store_idx)
902 assert(storeQueue[store_idx].inst);
903 storeQueue[store_idx].completed = true;
905 // A bit conservative because a store completion may not free up entries,
906 // but hopefully avoids two store completions in one cycle from making
907 // the CPU tick twice.
909 cpu->activityThisCycle();
911 if (store_idx == storeHead) {
913 incrStIdx(storeHead);
916 } while (storeQueue[storeHead].completed &&
917 storeHead != storeTail);
919 iewStage->updateLSQNextCycle = true;
922 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
924 storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
927 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
928 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
930 stallingStoreIsn, stallingLoadIdx);
932 stallingStoreIsn = 0;
933 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
936 storeQueue[store_idx].inst->setCompleted();
938 // Tell the checker we've completed this instruction. Some stores
939 // may get reported twice to the checker, but the checker can
943 cpu->checker->verify(storeQueue[store_idx].inst);
948 template <class Impl>
950 LSQUnit<Impl>::recvRetry()
952 if (isStoreBlocked) {
953 assert(retryPkt != NULL);
955 if (dcachePort->sendTiming(retryPkt)) {
956 if (retryPkt->result == Packet::BadAddress) {
957 panic("LSQ sent out a bad address for a completed store!");
959 storePostSend(retryPkt);
961 isStoreBlocked = false;
962 lsq->setRetryTid(-1);
966 lsq->setRetryTid(lsqID);
968 } else if (isLoadBlocked) {
969 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
970 "no need to resend packet.\n");
972 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
976 template <class Impl>
978 LSQUnit<Impl>::incrStIdx(int &store_idx)
980 if (++store_idx >= SQEntries)
984 template <class Impl>
986 LSQUnit<Impl>::decrStIdx(int &store_idx)
989 store_idx += SQEntries;
992 template <class Impl>
994 LSQUnit<Impl>::incrLdIdx(int &load_idx)
996 if (++load_idx >= LQEntries)
1000 template <class Impl>
1002 LSQUnit<Impl>::decrLdIdx(int &load_idx)
1005 load_idx += LQEntries;
1008 template <class Impl>
1010 LSQUnit<Impl>::dumpInsts()
1012 cprintf("Load store queue: Dumping instructions.\n");
1013 cprintf("Load queue size: %i\n", loads);
1014 cprintf("Load queue: ");
1016 int load_idx = loadHead;
1018 while (load_idx != loadTail && loadQueue[load_idx]) {
1019 cprintf("%#x ", loadQueue[load_idx]->readPC());
1021 incrLdIdx(load_idx);
1024 cprintf("Store queue size: %i\n", stores);
1025 cprintf("Store queue: ");
1027 int store_idx = storeHead;
1029 while (store_idx != storeTail && storeQueue[store_idx].inst) {
1030 cprintf("%#x ", storeQueue[store_idx].inst->readPC());
1032 incrStIdx(store_idx);