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33 #include "cpu/o3/inst_queue.hh"
34 #include "cpu/o3/mem_dep_unit.hh"
36 #include "params/DerivO3CPU.hh"
38 template <class MemDepPred, class Impl>
39 MemDepUnit<MemDepPred, Impl>::MemDepUnit()
40 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
41 storeBarrierSN(0), iqPtr(NULL)
45 template <class MemDepPred, class Impl>
46 MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
47 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
48 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
50 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
53 template <class MemDepPred, class Impl>
54 MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
56 for (int tid=0; tid < Impl::MaxThreads; tid++) {
58 ListIt inst_list_it = instList[tid].begin();
62 while (!instList[tid].empty()) {
63 hash_it = memDepHash.find((*inst_list_it)->seqNum);
65 assert(hash_it != memDepHash.end());
67 memDepHash.erase(hash_it);
69 instList[tid].erase(inst_list_it++);
74 assert(MemDepEntry::memdep_count == 0);
78 template <class MemDepPred, class Impl>
80 MemDepUnit<MemDepPred, Impl>::name() const
85 template <class MemDepPred, class Impl>
87 MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, int tid)
89 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
93 depPred.init(params->SSITSize, params->LFSTSize);
96 template <class MemDepPred, class Impl>
98 MemDepUnit<MemDepPred, Impl>::regStats()
101 .name(name() + ".memDep.insertedLoads")
102 .desc("Number of loads inserted to the mem dependence unit.");
105 .name(name() + ".memDep.insertedStores")
106 .desc("Number of stores inserted to the mem dependence unit.");
109 .name(name() + ".memDep.conflictingLoads")
110 .desc("Number of conflicting loads.");
113 .name(name() + ".memDep.conflictingStores")
114 .desc("Number of conflicting stores.");
117 template <class MemDepPred, class Impl>
119 MemDepUnit<MemDepPred, Impl>::switchOut()
121 assert(instList[0].empty());
122 assert(instsToReplay.empty());
123 assert(memDepHash.empty());
125 for (int i = 0; i < Impl::MaxThreads; ++i) {
128 instsToReplay.clear();
132 template <class MemDepPred, class Impl>
134 MemDepUnit<MemDepPred, Impl>::takeOverFrom()
136 // Be sure to reset all state.
137 loadBarrier = storeBarrier = false;
138 loadBarrierSN = storeBarrierSN = 0;
142 template <class MemDepPred, class Impl>
144 MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
149 template <class MemDepPred, class Impl>
151 MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
153 unsigned tid = inst->threadNumber;
155 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
157 // Add the MemDepEntry to the hash.
159 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
161 MemDepEntry::memdep_insert++;
164 instList[tid].push_back(inst);
166 inst_entry->listIt = --(instList[tid].end());
168 // Check any barriers and the dependence predictor for any
169 // producing memrefs/stores.
170 InstSeqNum producing_store;
171 if (inst->isLoad() && loadBarrier) {
172 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
174 producing_store = loadBarrierSN;
175 } else if (inst->isStore() && storeBarrier) {
176 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
178 producing_store = storeBarrierSN;
180 producing_store = depPred.checkInst(inst->readPC());
183 MemDepEntryPtr store_entry = NULL;
185 // If there is a producing store, try to find the entry.
186 if (producing_store != 0) {
187 DPRINTF(MemDepUnit, "Searching for producer\n");
188 MemDepHashIt hash_it = memDepHash.find(producing_store);
190 if (hash_it != memDepHash.end()) {
191 store_entry = (*hash_it).second;
192 DPRINTF(MemDepUnit, "Proucer found\n");
196 // If no store entry, then instruction can issue as soon as the registers
199 DPRINTF(MemDepUnit, "No dependency for inst PC "
200 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
202 inst_entry->memDepReady = true;
204 if (inst->readyToIssue()) {
205 inst_entry->regsReady = true;
207 moveToReady(inst_entry);
210 // Otherwise make the instruction dependent on the store/barrier.
211 DPRINTF(MemDepUnit, "Adding to dependency list; "
212 "inst PC %#x is dependent on [sn:%lli].\n",
213 inst->readPC(), producing_store);
215 if (inst->readyToIssue()) {
216 inst_entry->regsReady = true;
219 // Clear the bit saying this instruction can issue.
220 inst->clearCanIssue();
222 // Add this instruction to the list of dependents.
223 store_entry->dependInsts.push_back(inst_entry);
225 if (inst->isLoad()) {
232 if (inst->isStore()) {
233 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
234 inst->readPC(), inst->seqNum);
236 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
239 } else if (inst->isLoad()) {
242 panic("Unknown type! (most likely a barrier).");
246 template <class MemDepPred, class Impl>
248 MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
250 unsigned tid = inst->threadNumber;
252 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
254 // Insert the MemDepEntry into the hash.
256 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
258 MemDepEntry::memdep_insert++;
261 // Add the instruction to the list.
262 instList[tid].push_back(inst);
264 inst_entry->listIt = --(instList[tid].end());
266 // Might want to turn this part into an inline function or something.
267 // It's shared between both insert functions.
268 if (inst->isStore()) {
269 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
270 inst->readPC(), inst->seqNum);
272 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
275 } else if (inst->isLoad()) {
278 panic("Unknown type! (most likely a barrier).");
282 template <class MemDepPred, class Impl>
284 MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
286 InstSeqNum barr_sn = barr_inst->seqNum;
287 // Memory barriers block loads and stores, write barriers only stores.
288 if (barr_inst->isMemBarrier()) {
290 loadBarrierSN = barr_sn;
292 storeBarrierSN = barr_sn;
293 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
294 } else if (barr_inst->isWriteBarrier()) {
296 storeBarrierSN = barr_sn;
297 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
300 unsigned tid = barr_inst->threadNumber;
302 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
304 // Add the MemDepEntry to the hash.
306 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
308 MemDepEntry::memdep_insert++;
311 // Add the instruction to the instruction list.
312 instList[tid].push_back(barr_inst);
314 inst_entry->listIt = --(instList[tid].end());
317 template <class MemDepPred, class Impl>
319 MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
321 DPRINTF(MemDepUnit, "Marking registers as ready for "
322 "instruction PC %#x [sn:%lli].\n",
323 inst->readPC(), inst->seqNum);
325 MemDepEntryPtr inst_entry = findInHash(inst);
327 inst_entry->regsReady = true;
329 if (inst_entry->memDepReady) {
330 DPRINTF(MemDepUnit, "Instruction has its memory "
331 "dependencies resolved, adding it to the ready list.\n");
333 moveToReady(inst_entry);
335 DPRINTF(MemDepUnit, "Instruction still waiting on "
336 "memory dependency.\n");
340 template <class MemDepPred, class Impl>
342 MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
344 DPRINTF(MemDepUnit, "Marking non speculative "
345 "instruction PC %#x as ready [sn:%lli].\n",
346 inst->readPC(), inst->seqNum);
348 MemDepEntryPtr inst_entry = findInHash(inst);
350 moveToReady(inst_entry);
353 template <class MemDepPred, class Impl>
355 MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
357 instsToReplay.push_back(inst);
360 template <class MemDepPred, class Impl>
362 MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
364 DynInstPtr temp_inst;
366 // For now this replay function replays all waiting memory ops.
367 while (!instsToReplay.empty()) {
368 temp_inst = instsToReplay.front();
370 MemDepEntryPtr inst_entry = findInHash(temp_inst);
372 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
374 temp_inst->readPC(), temp_inst->seqNum);
376 moveToReady(inst_entry);
378 instsToReplay.pop_front();
382 template <class MemDepPred, class Impl>
384 MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
386 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
388 inst->readPC(), inst->seqNum);
390 unsigned tid = inst->threadNumber;
392 // Remove the instruction from the hash and the list.
393 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
395 assert(hash_it != memDepHash.end());
397 instList[tid].erase((*hash_it).second->listIt);
399 (*hash_it).second = NULL;
401 memDepHash.erase(hash_it);
403 MemDepEntry::memdep_erase++;
407 template <class MemDepPred, class Impl>
409 MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
411 wakeDependents(inst);
414 InstSeqNum barr_sn = inst->seqNum;
416 if (inst->isMemBarrier()) {
417 assert(loadBarrier && storeBarrier);
418 if (loadBarrierSN == barr_sn)
420 if (storeBarrierSN == barr_sn)
421 storeBarrier = false;
422 } else if (inst->isWriteBarrier()) {
423 assert(storeBarrier);
424 if (storeBarrierSN == barr_sn)
425 storeBarrier = false;
429 template <class MemDepPred, class Impl>
431 MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
433 // Only stores and barriers have dependents.
434 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
438 MemDepEntryPtr inst_entry = findInHash(inst);
440 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
441 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
443 if (!woken_inst->inst) {
444 // Potentially removed mem dep entries could be on this list
448 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
450 woken_inst->inst->seqNum);
452 if (woken_inst->regsReady && !woken_inst->squashed) {
453 moveToReady(woken_inst);
455 woken_inst->memDepReady = true;
459 inst_entry->dependInsts.clear();
462 template <class MemDepPred, class Impl>
464 MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
467 if (!instsToReplay.empty()) {
468 ListIt replay_it = instsToReplay.begin();
469 while (replay_it != instsToReplay.end()) {
470 if ((*replay_it)->threadNumber == tid &&
471 (*replay_it)->seqNum > squashed_num) {
472 instsToReplay.erase(replay_it++);
479 ListIt squash_it = instList[tid].end();
482 MemDepHashIt hash_it;
484 while (!instList[tid].empty() &&
485 (*squash_it)->seqNum > squashed_num) {
487 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
488 (*squash_it)->seqNum);
490 hash_it = memDepHash.find((*squash_it)->seqNum);
492 assert(hash_it != memDepHash.end());
494 (*hash_it).second->squashed = true;
496 (*hash_it).second = NULL;
498 memDepHash.erase(hash_it);
500 MemDepEntry::memdep_erase++;
503 instList[tid].erase(squash_it--);
506 // Tell the dependency predictor to squash as well.
507 depPred.squash(squashed_num, tid);
510 template <class MemDepPred, class Impl>
512 MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
513 DynInstPtr &violating_load)
515 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
516 " load: %#x, store: %#x\n", violating_load->readPC(),
517 store_inst->readPC());
518 // Tell the memory dependence unit of the violation.
519 depPred.violation(violating_load->readPC(), store_inst->readPC());
522 template <class MemDepPred, class Impl>
524 MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
526 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
527 inst->readPC(), inst->seqNum);
529 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
532 template <class MemDepPred, class Impl>
533 inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
534 MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
536 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
538 assert(hash_it != memDepHash.end());
540 return (*hash_it).second;
543 template <class MemDepPred, class Impl>
545 MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
547 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
548 "to the ready list.\n", woken_inst_entry->inst->seqNum);
550 assert(!woken_inst_entry->squashed);
552 iqPtr->addReadyMemInst(woken_inst_entry->inst);
556 template <class MemDepPred, class Impl>
558 MemDepUnit<MemDepPred, Impl>::dumpLists()
560 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
561 cprintf("Instruction list %i size: %i\n",
562 tid, instList[tid].size());
564 ListIt inst_list_it = instList[tid].begin();
567 while (inst_list_it != instList[tid].end()) {
568 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
570 num, (*inst_list_it)->readPC(),
571 (*inst_list_it)->seqNum,
572 (*inst_list_it)->threadNumber,
573 (*inst_list_it)->isIssued(),
574 (*inst_list_it)->isSquashed());
580 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
583 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);