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33 #include "cpu/o3/inst_queue.hh"
34 #include "cpu/o3/mem_dep_unit.hh"
36 template <class MemDepPred, class Impl>
37 MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
38 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
39 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
41 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
44 template <class MemDepPred, class Impl>
45 MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
47 for (int tid=0; tid < Impl::MaxThreads; tid++) {
49 ListIt inst_list_it = instList[tid].begin();
53 while (!instList[tid].empty()) {
54 hash_it = memDepHash.find((*inst_list_it)->seqNum);
56 assert(hash_it != memDepHash.end());
58 memDepHash.erase(hash_it);
60 instList[tid].erase(inst_list_it++);
65 assert(MemDepEntry::memdep_count == 0);
69 template <class MemDepPred, class Impl>
71 MemDepUnit<MemDepPred, Impl>::name() const
76 template <class MemDepPred, class Impl>
78 MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
80 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
84 depPred.init(params->SSITSize, params->LFSTSize);
87 template <class MemDepPred, class Impl>
89 MemDepUnit<MemDepPred, Impl>::regStats()
92 .name(name() + ".memDep.insertedLoads")
93 .desc("Number of loads inserted to the mem dependence unit.");
96 .name(name() + ".memDep.insertedStores")
97 .desc("Number of stores inserted to the mem dependence unit.");
100 .name(name() + ".memDep.conflictingLoads")
101 .desc("Number of conflicting loads.");
104 .name(name() + ".memDep.conflictingStores")
105 .desc("Number of conflicting stores.");
108 template <class MemDepPred, class Impl>
110 MemDepUnit<MemDepPred, Impl>::switchOut()
113 for (int i = 0; i < Impl::MaxThreads; ++i) {
116 instsToReplay.clear();
120 template <class MemDepPred, class Impl>
122 MemDepUnit<MemDepPred, Impl>::takeOverFrom()
124 // Be sure to reset all state.
125 loadBarrier = storeBarrier = false;
126 loadBarrierSN = storeBarrierSN = 0;
130 template <class MemDepPred, class Impl>
132 MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
137 template <class MemDepPred, class Impl>
139 MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
141 unsigned tid = inst->threadNumber;
143 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
145 // Add the MemDepEntry to the hash.
147 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
149 MemDepEntry::memdep_insert++;
152 instList[tid].push_back(inst);
154 inst_entry->listIt = --(instList[tid].end());
156 // Check any barriers and the dependence predictor for any
157 // producing memrefs/stores.
158 InstSeqNum producing_store;
159 if (inst->isLoad() && loadBarrier) {
160 producing_store = loadBarrierSN;
161 } else if (inst->isStore() && storeBarrier) {
162 producing_store = storeBarrierSN;
164 producing_store = depPred.checkInst(inst->readPC());
167 MemDepEntryPtr store_entry = NULL;
169 // If there is a producing store, try to find the entry.
170 if (producing_store != 0) {
171 MemDepHashIt hash_it = memDepHash.find(producing_store);
173 if (hash_it != memDepHash.end()) {
174 store_entry = (*hash_it).second;
178 // If no store entry, then instruction can issue as soon as the registers
181 DPRINTF(MemDepUnit, "No dependency for inst PC "
182 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
184 inst_entry->memDepReady = true;
186 if (inst->readyToIssue()) {
187 inst_entry->regsReady = true;
189 moveToReady(inst_entry);
192 // Otherwise make the instruction dependent on the store/barrier.
193 DPRINTF(MemDepUnit, "Adding to dependency list; "
194 "inst PC %#x is dependent on [sn:%lli].\n",
195 inst->readPC(), producing_store);
197 if (inst->readyToIssue()) {
198 inst_entry->regsReady = true;
201 // Add this instruction to the list of dependents.
202 store_entry->dependInsts.push_back(inst_entry);
204 if (inst->isLoad()) {
211 if (inst->isStore()) {
212 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
213 inst->readPC(), inst->seqNum);
215 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
218 } else if (inst->isLoad()) {
221 panic("Unknown type! (most likely a barrier).");
225 template <class MemDepPred, class Impl>
227 MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
229 unsigned tid = inst->threadNumber;
231 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
233 // Insert the MemDepEntry into the hash.
235 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
237 MemDepEntry::memdep_insert++;
240 // Add the instruction to the list.
241 instList[tid].push_back(inst);
243 inst_entry->listIt = --(instList[tid].end());
245 // Might want to turn this part into an inline function or something.
246 // It's shared between both insert functions.
247 if (inst->isStore()) {
248 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
249 inst->readPC(), inst->seqNum);
251 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
254 } else if (inst->isLoad()) {
257 panic("Unknown type! (most likely a barrier).");
261 template <class MemDepPred, class Impl>
263 MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
265 InstSeqNum barr_sn = barr_inst->seqNum;
266 // Memory barriers block loads and stores, write barriers only stores.
267 if (barr_inst->isMemBarrier()) {
269 loadBarrierSN = barr_sn;
271 storeBarrierSN = barr_sn;
272 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
273 } else if (barr_inst->isWriteBarrier()) {
275 storeBarrierSN = barr_sn;
276 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
279 unsigned tid = barr_inst->threadNumber;
281 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
283 // Add the MemDepEntry to the hash.
285 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
287 MemDepEntry::memdep_insert++;
290 // Add the instruction to the instruction list.
291 instList[tid].push_back(barr_inst);
293 inst_entry->listIt = --(instList[tid].end());
296 template <class MemDepPred, class Impl>
298 MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
300 DPRINTF(MemDepUnit, "Marking registers as ready for "
301 "instruction PC %#x [sn:%lli].\n",
302 inst->readPC(), inst->seqNum);
304 MemDepEntryPtr inst_entry = findInHash(inst);
306 inst_entry->regsReady = true;
308 if (inst_entry->memDepReady) {
309 DPRINTF(MemDepUnit, "Instruction has its memory "
310 "dependencies resolved, adding it to the ready list.\n");
312 moveToReady(inst_entry);
314 DPRINTF(MemDepUnit, "Instruction still waiting on "
315 "memory dependency.\n");
319 template <class MemDepPred, class Impl>
321 MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
323 DPRINTF(MemDepUnit, "Marking non speculative "
324 "instruction PC %#x as ready [sn:%lli].\n",
325 inst->readPC(), inst->seqNum);
327 MemDepEntryPtr inst_entry = findInHash(inst);
329 moveToReady(inst_entry);
332 template <class MemDepPred, class Impl>
334 MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
336 instsToReplay.push_back(inst);
339 template <class MemDepPred, class Impl>
341 MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
343 DynInstPtr temp_inst;
344 bool found_inst = false;
346 // For now this replay function replays all waiting memory ops.
347 while (!instsToReplay.empty()) {
348 temp_inst = instsToReplay.front();
350 MemDepEntryPtr inst_entry = findInHash(temp_inst);
352 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
354 temp_inst->readPC(), temp_inst->seqNum);
356 moveToReady(inst_entry);
358 if (temp_inst == inst) {
362 instsToReplay.pop_front();
368 template <class MemDepPred, class Impl>
370 MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
372 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
374 inst->readPC(), inst->seqNum);
376 unsigned tid = inst->threadNumber;
378 // Remove the instruction from the hash and the list.
379 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
381 assert(hash_it != memDepHash.end());
383 instList[tid].erase((*hash_it).second->listIt);
385 (*hash_it).second = NULL;
387 memDepHash.erase(hash_it);
389 MemDepEntry::memdep_erase++;
393 template <class MemDepPred, class Impl>
395 MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
397 wakeDependents(inst);
400 InstSeqNum barr_sn = inst->seqNum;
402 if (inst->isMemBarrier()) {
403 assert(loadBarrier && storeBarrier);
404 if (loadBarrierSN == barr_sn)
406 if (storeBarrierSN == barr_sn)
407 storeBarrier = false;
408 } else if (inst->isWriteBarrier()) {
409 assert(storeBarrier);
410 if (storeBarrierSN == barr_sn)
411 storeBarrier = false;
415 template <class MemDepPred, class Impl>
417 MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
419 // Only stores and barriers have dependents.
420 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
424 MemDepEntryPtr inst_entry = findInHash(inst);
426 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
427 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
429 if (!woken_inst->inst) {
430 // Potentially removed mem dep entries could be on this list
434 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
436 woken_inst->inst->seqNum);
438 if (woken_inst->regsReady && !woken_inst->squashed) {
439 moveToReady(woken_inst);
441 woken_inst->memDepReady = true;
445 inst_entry->dependInsts.clear();
448 template <class MemDepPred, class Impl>
450 MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
453 if (!instsToReplay.empty()) {
454 ListIt replay_it = instsToReplay.begin();
455 while (replay_it != instsToReplay.end()) {
456 if ((*replay_it)->threadNumber == tid &&
457 (*replay_it)->seqNum > squashed_num) {
458 instsToReplay.erase(replay_it++);
465 ListIt squash_it = instList[tid].end();
468 MemDepHashIt hash_it;
470 while (!instList[tid].empty() &&
471 (*squash_it)->seqNum > squashed_num) {
473 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
474 (*squash_it)->seqNum);
476 hash_it = memDepHash.find((*squash_it)->seqNum);
478 assert(hash_it != memDepHash.end());
480 (*hash_it).second->squashed = true;
482 (*hash_it).second = NULL;
484 memDepHash.erase(hash_it);
486 MemDepEntry::memdep_erase++;
489 instList[tid].erase(squash_it--);
492 // Tell the dependency predictor to squash as well.
493 depPred.squash(squashed_num, tid);
496 template <class MemDepPred, class Impl>
498 MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
499 DynInstPtr &violating_load)
501 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
502 " load: %#x, store: %#x\n", violating_load->readPC(),
503 store_inst->readPC());
504 // Tell the memory dependence unit of the violation.
505 depPred.violation(violating_load->readPC(), store_inst->readPC());
508 template <class MemDepPred, class Impl>
510 MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
512 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
513 inst->readPC(), inst->seqNum);
515 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
518 template <class MemDepPred, class Impl>
519 inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
520 MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
522 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
524 assert(hash_it != memDepHash.end());
526 return (*hash_it).second;
529 template <class MemDepPred, class Impl>
531 MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
533 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
534 "to the ready list.\n", woken_inst_entry->inst->seqNum);
536 assert(!woken_inst_entry->squashed);
538 iqPtr->addReadyMemInst(woken_inst_entry->inst);
542 template <class MemDepPred, class Impl>
544 MemDepUnit<MemDepPred, Impl>::dumpLists()
546 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
547 cprintf("Instruction list %i size: %i\n",
548 tid, instList[tid].size());
550 ListIt inst_list_it = instList[tid].begin();
553 while (inst_list_it != instList[tid].end()) {
554 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
556 num, (*inst_list_it)->readPC(),
557 (*inst_list_it)->seqNum,
558 (*inst_list_it)->threadNumber,
559 (*inst_list_it)->isIssued(),
560 (*inst_list_it)->isSquashed());
566 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
569 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);