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33 #include "cpu/o3/inst_queue.hh"
34 #include "cpu/o3/mem_dep_unit.hh"
36 template <class MemDepPred, class Impl>
37 MemDepUnit<MemDepPred, Impl>::MemDepUnit()
38 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
39 storeBarrierSN(0), iqPtr(NULL)
43 template <class MemDepPred, class Impl>
44 MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
45 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
46 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
48 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
51 template <class MemDepPred, class Impl>
52 MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
54 for (int tid=0; tid < Impl::MaxThreads; tid++) {
56 ListIt inst_list_it = instList[tid].begin();
60 while (!instList[tid].empty()) {
61 hash_it = memDepHash.find((*inst_list_it)->seqNum);
63 assert(hash_it != memDepHash.end());
65 memDepHash.erase(hash_it);
67 instList[tid].erase(inst_list_it++);
72 assert(MemDepEntry::memdep_count == 0);
76 template <class MemDepPred, class Impl>
78 MemDepUnit<MemDepPred, Impl>::name() const
83 template <class MemDepPred, class Impl>
85 MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
87 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
91 depPred.init(params->SSITSize, params->LFSTSize);
94 template <class MemDepPred, class Impl>
96 MemDepUnit<MemDepPred, Impl>::regStats()
99 .name(name() + ".memDep.insertedLoads")
100 .desc("Number of loads inserted to the mem dependence unit.");
103 .name(name() + ".memDep.insertedStores")
104 .desc("Number of stores inserted to the mem dependence unit.");
107 .name(name() + ".memDep.conflictingLoads")
108 .desc("Number of conflicting loads.");
111 .name(name() + ".memDep.conflictingStores")
112 .desc("Number of conflicting stores.");
115 template <class MemDepPred, class Impl>
117 MemDepUnit<MemDepPred, Impl>::switchOut()
119 assert(instList[0].empty());
120 assert(instsToReplay.empty());
121 assert(memDepHash.empty());
123 for (int i = 0; i < Impl::MaxThreads; ++i) {
126 instsToReplay.clear();
130 template <class MemDepPred, class Impl>
132 MemDepUnit<MemDepPred, Impl>::takeOverFrom()
134 // Be sure to reset all state.
135 loadBarrier = storeBarrier = false;
136 loadBarrierSN = storeBarrierSN = 0;
140 template <class MemDepPred, class Impl>
142 MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
147 template <class MemDepPred, class Impl>
149 MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
151 unsigned tid = inst->threadNumber;
153 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
155 // Add the MemDepEntry to the hash.
157 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
159 MemDepEntry::memdep_insert++;
162 instList[tid].push_back(inst);
164 inst_entry->listIt = --(instList[tid].end());
166 // Check any barriers and the dependence predictor for any
167 // producing memrefs/stores.
168 InstSeqNum producing_store;
169 if (inst->isLoad() && loadBarrier) {
170 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
172 producing_store = loadBarrierSN;
173 } else if (inst->isStore() && storeBarrier) {
174 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
176 producing_store = storeBarrierSN;
178 producing_store = depPred.checkInst(inst->readPC());
181 MemDepEntryPtr store_entry = NULL;
183 // If there is a producing store, try to find the entry.
184 if (producing_store != 0) {
185 DPRINTF(MemDepUnit, "Searching for producer\n");
186 MemDepHashIt hash_it = memDepHash.find(producing_store);
188 if (hash_it != memDepHash.end()) {
189 store_entry = (*hash_it).second;
190 DPRINTF(MemDepUnit, "Proucer found\n");
194 // If no store entry, then instruction can issue as soon as the registers
197 DPRINTF(MemDepUnit, "No dependency for inst PC "
198 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
200 inst_entry->memDepReady = true;
202 if (inst->readyToIssue()) {
203 inst_entry->regsReady = true;
205 moveToReady(inst_entry);
208 // Otherwise make the instruction dependent on the store/barrier.
209 DPRINTF(MemDepUnit, "Adding to dependency list; "
210 "inst PC %#x is dependent on [sn:%lli].\n",
211 inst->readPC(), producing_store);
213 if (inst->readyToIssue()) {
214 inst_entry->regsReady = true;
217 // Clear the bit saying this instruction can issue.
218 inst->clearCanIssue();
220 // Add this instruction to the list of dependents.
221 store_entry->dependInsts.push_back(inst_entry);
223 if (inst->isLoad()) {
230 if (inst->isStore()) {
231 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
232 inst->readPC(), inst->seqNum);
234 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
237 } else if (inst->isLoad()) {
240 panic("Unknown type! (most likely a barrier).");
244 template <class MemDepPred, class Impl>
246 MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
248 unsigned tid = inst->threadNumber;
250 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
252 // Insert the MemDepEntry into the hash.
254 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
256 MemDepEntry::memdep_insert++;
259 // Add the instruction to the list.
260 instList[tid].push_back(inst);
262 inst_entry->listIt = --(instList[tid].end());
264 // Might want to turn this part into an inline function or something.
265 // It's shared between both insert functions.
266 if (inst->isStore()) {
267 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
268 inst->readPC(), inst->seqNum);
270 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
273 } else if (inst->isLoad()) {
276 panic("Unknown type! (most likely a barrier).");
280 template <class MemDepPred, class Impl>
282 MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
284 InstSeqNum barr_sn = barr_inst->seqNum;
285 // Memory barriers block loads and stores, write barriers only stores.
286 if (barr_inst->isMemBarrier()) {
288 loadBarrierSN = barr_sn;
290 storeBarrierSN = barr_sn;
291 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
292 } else if (barr_inst->isWriteBarrier()) {
294 storeBarrierSN = barr_sn;
295 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
298 unsigned tid = barr_inst->threadNumber;
300 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
302 // Add the MemDepEntry to the hash.
304 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
306 MemDepEntry::memdep_insert++;
309 // Add the instruction to the instruction list.
310 instList[tid].push_back(barr_inst);
312 inst_entry->listIt = --(instList[tid].end());
315 template <class MemDepPred, class Impl>
317 MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
319 DPRINTF(MemDepUnit, "Marking registers as ready for "
320 "instruction PC %#x [sn:%lli].\n",
321 inst->readPC(), inst->seqNum);
323 MemDepEntryPtr inst_entry = findInHash(inst);
325 inst_entry->regsReady = true;
327 if (inst_entry->memDepReady) {
328 DPRINTF(MemDepUnit, "Instruction has its memory "
329 "dependencies resolved, adding it to the ready list.\n");
331 moveToReady(inst_entry);
333 DPRINTF(MemDepUnit, "Instruction still waiting on "
334 "memory dependency.\n");
338 template <class MemDepPred, class Impl>
340 MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
342 DPRINTF(MemDepUnit, "Marking non speculative "
343 "instruction PC %#x as ready [sn:%lli].\n",
344 inst->readPC(), inst->seqNum);
346 MemDepEntryPtr inst_entry = findInHash(inst);
348 moveToReady(inst_entry);
351 template <class MemDepPred, class Impl>
353 MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
355 instsToReplay.push_back(inst);
358 template <class MemDepPred, class Impl>
360 MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
362 DynInstPtr temp_inst;
364 // For now this replay function replays all waiting memory ops.
365 while (!instsToReplay.empty()) {
366 temp_inst = instsToReplay.front();
368 MemDepEntryPtr inst_entry = findInHash(temp_inst);
370 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
372 temp_inst->readPC(), temp_inst->seqNum);
374 moveToReady(inst_entry);
376 instsToReplay.pop_front();
380 template <class MemDepPred, class Impl>
382 MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
384 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
386 inst->readPC(), inst->seqNum);
388 unsigned tid = inst->threadNumber;
390 // Remove the instruction from the hash and the list.
391 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
393 assert(hash_it != memDepHash.end());
395 instList[tid].erase((*hash_it).second->listIt);
397 (*hash_it).second = NULL;
399 memDepHash.erase(hash_it);
401 MemDepEntry::memdep_erase++;
405 template <class MemDepPred, class Impl>
407 MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
409 wakeDependents(inst);
412 InstSeqNum barr_sn = inst->seqNum;
414 if (inst->isMemBarrier()) {
415 assert(loadBarrier && storeBarrier);
416 if (loadBarrierSN == barr_sn)
418 if (storeBarrierSN == barr_sn)
419 storeBarrier = false;
420 } else if (inst->isWriteBarrier()) {
421 assert(storeBarrier);
422 if (storeBarrierSN == barr_sn)
423 storeBarrier = false;
427 template <class MemDepPred, class Impl>
429 MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
431 // Only stores and barriers have dependents.
432 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
436 MemDepEntryPtr inst_entry = findInHash(inst);
438 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
439 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
441 if (!woken_inst->inst) {
442 // Potentially removed mem dep entries could be on this list
446 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
448 woken_inst->inst->seqNum);
450 if (woken_inst->regsReady && !woken_inst->squashed) {
451 moveToReady(woken_inst);
453 woken_inst->memDepReady = true;
457 inst_entry->dependInsts.clear();
460 template <class MemDepPred, class Impl>
462 MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
465 if (!instsToReplay.empty()) {
466 ListIt replay_it = instsToReplay.begin();
467 while (replay_it != instsToReplay.end()) {
468 if ((*replay_it)->threadNumber == tid &&
469 (*replay_it)->seqNum > squashed_num) {
470 instsToReplay.erase(replay_it++);
477 ListIt squash_it = instList[tid].end();
480 MemDepHashIt hash_it;
482 while (!instList[tid].empty() &&
483 (*squash_it)->seqNum > squashed_num) {
485 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
486 (*squash_it)->seqNum);
488 hash_it = memDepHash.find((*squash_it)->seqNum);
490 assert(hash_it != memDepHash.end());
492 (*hash_it).second->squashed = true;
494 (*hash_it).second = NULL;
496 memDepHash.erase(hash_it);
498 MemDepEntry::memdep_erase++;
501 instList[tid].erase(squash_it--);
504 // Tell the dependency predictor to squash as well.
505 depPred.squash(squashed_num, tid);
508 template <class MemDepPred, class Impl>
510 MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
511 DynInstPtr &violating_load)
513 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
514 " load: %#x, store: %#x\n", violating_load->readPC(),
515 store_inst->readPC());
516 // Tell the memory dependence unit of the violation.
517 depPred.violation(violating_load->readPC(), store_inst->readPC());
520 template <class MemDepPred, class Impl>
522 MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
524 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
525 inst->readPC(), inst->seqNum);
527 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
530 template <class MemDepPred, class Impl>
531 inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
532 MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
534 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
536 assert(hash_it != memDepHash.end());
538 return (*hash_it).second;
541 template <class MemDepPred, class Impl>
543 MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
545 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
546 "to the ready list.\n", woken_inst_entry->inst->seqNum);
548 assert(!woken_inst_entry->squashed);
550 iqPtr->addReadyMemInst(woken_inst_entry->inst);
554 template <class MemDepPred, class Impl>
556 MemDepUnit<MemDepPred, Impl>::dumpLists()
558 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
559 cprintf("Instruction list %i size: %i\n",
560 tid, instList[tid].size());
562 ListIt inst_list_it = instList[tid].begin();
565 while (inst_list_it != instList[tid].end()) {
566 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
568 num, (*inst_list_it)->readPC(),
569 (*inst_list_it)->seqNum,
570 (*inst_list_it)->threadNumber,
571 (*inst_list_it)->isIssued(),
572 (*inst_list_it)->isSquashed());
578 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
581 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);