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33 #include "cpu/o3/inst_queue.hh"
34 #include "cpu/o3/mem_dep_unit.hh"
35 #include "debug/MemDepUnit.hh"
36 #include "params/DerivO3CPU.hh"
38 template <class MemDepPred, class Impl>
39 MemDepUnit<MemDepPred, Impl>::MemDepUnit()
40 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
41 storeBarrierSN(0), iqPtr(NULL)
45 template <class MemDepPred, class Impl>
46 MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
47 : _name(params->name + ".memdepunit"),
48 depPred(params->store_set_clear_period, params->SSITSize,
50 loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
51 storeBarrierSN(0), iqPtr(NULL)
53 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
56 template <class MemDepPred, class Impl>
57 MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
59 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
61 ListIt inst_list_it = instList[tid].begin();
65 while (!instList[tid].empty()) {
66 hash_it = memDepHash.find((*inst_list_it)->seqNum);
68 assert(hash_it != memDepHash.end());
70 memDepHash.erase(hash_it);
72 instList[tid].erase(inst_list_it++);
77 assert(MemDepEntry::memdep_count == 0);
81 template <class MemDepPred, class Impl>
83 MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
85 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
87 _name = csprintf("%s.memDep%d", params->name, tid);
90 depPred.init(params->store_set_clear_period, params->SSITSize,
94 template <class MemDepPred, class Impl>
96 MemDepUnit<MemDepPred, Impl>::regStats()
99 .name(name() + ".insertedLoads")
100 .desc("Number of loads inserted to the mem dependence unit.");
103 .name(name() + ".insertedStores")
104 .desc("Number of stores inserted to the mem dependence unit.");
107 .name(name() + ".conflictingLoads")
108 .desc("Number of conflicting loads.");
111 .name(name() + ".conflictingStores")
112 .desc("Number of conflicting stores.");
115 template <class MemDepPred, class Impl>
117 MemDepUnit<MemDepPred, Impl>::switchOut()
119 assert(instList[0].empty());
120 assert(instsToReplay.empty());
121 assert(memDepHash.empty());
123 for (int i = 0; i < Impl::MaxThreads; ++i) {
126 instsToReplay.clear();
130 template <class MemDepPred, class Impl>
132 MemDepUnit<MemDepPred, Impl>::takeOverFrom()
134 // Be sure to reset all state.
135 loadBarrier = storeBarrier = false;
136 loadBarrierSN = storeBarrierSN = 0;
140 template <class MemDepPred, class Impl>
142 MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
147 template <class MemDepPred, class Impl>
149 MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
151 ThreadID tid = inst->threadNumber;
153 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
155 // Add the MemDepEntry to the hash.
157 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
159 MemDepEntry::memdep_insert++;
162 instList[tid].push_back(inst);
164 inst_entry->listIt = --(instList[tid].end());
166 // Check any barriers and the dependence predictor for any
167 // producing memrefs/stores.
168 InstSeqNum producing_store;
169 if (inst->isLoad() && loadBarrier) {
170 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
172 producing_store = loadBarrierSN;
173 } else if (inst->isStore() && storeBarrier) {
174 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
176 producing_store = storeBarrierSN;
178 producing_store = depPred.checkInst(inst->instAddr());
181 MemDepEntryPtr store_entry = NULL;
183 // If there is a producing store, try to find the entry.
184 if (producing_store != 0) {
185 DPRINTF(MemDepUnit, "Searching for producer\n");
186 MemDepHashIt hash_it = memDepHash.find(producing_store);
188 if (hash_it != memDepHash.end()) {
189 store_entry = (*hash_it).second;
190 DPRINTF(MemDepUnit, "Proucer found\n");
194 // If no store entry, then instruction can issue as soon as the registers
197 DPRINTF(MemDepUnit, "No dependency for inst PC "
198 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
200 inst_entry->memDepReady = true;
202 if (inst->readyToIssue()) {
203 inst_entry->regsReady = true;
205 moveToReady(inst_entry);
208 // Otherwise make the instruction dependent on the store/barrier.
209 DPRINTF(MemDepUnit, "Adding to dependency list; "
210 "inst PC %s is dependent on [sn:%lli].\n",
211 inst->pcState(), producing_store);
213 if (inst->readyToIssue()) {
214 inst_entry->regsReady = true;
217 // Clear the bit saying this instruction can issue.
218 inst->clearCanIssue();
220 // Add this instruction to the list of dependents.
221 store_entry->dependInsts.push_back(inst_entry);
223 if (inst->isLoad()) {
230 if (inst->isStore()) {
231 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
232 inst->pcState(), inst->seqNum);
234 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
237 } else if (inst->isLoad()) {
240 panic("Unknown type! (most likely a barrier).");
244 template <class MemDepPred, class Impl>
246 MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
248 ThreadID tid = inst->threadNumber;
250 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
252 // Insert the MemDepEntry into the hash.
254 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
256 MemDepEntry::memdep_insert++;
259 // Add the instruction to the list.
260 instList[tid].push_back(inst);
262 inst_entry->listIt = --(instList[tid].end());
264 // Might want to turn this part into an inline function or something.
265 // It's shared between both insert functions.
266 if (inst->isStore()) {
267 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
268 inst->pcState(), inst->seqNum);
270 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
273 } else if (inst->isLoad()) {
276 panic("Unknown type! (most likely a barrier).");
280 template <class MemDepPred, class Impl>
282 MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
284 InstSeqNum barr_sn = barr_inst->seqNum;
285 // Memory barriers block loads and stores, write barriers only stores.
286 if (barr_inst->isMemBarrier()) {
288 loadBarrierSN = barr_sn;
290 storeBarrierSN = barr_sn;
291 DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
292 barr_inst->pcState(),barr_sn);
293 } else if (barr_inst->isWriteBarrier()) {
295 storeBarrierSN = barr_sn;
296 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
299 ThreadID tid = barr_inst->threadNumber;
301 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
303 // Add the MemDepEntry to the hash.
305 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
307 MemDepEntry::memdep_insert++;
310 // Add the instruction to the instruction list.
311 instList[tid].push_back(barr_inst);
313 inst_entry->listIt = --(instList[tid].end());
316 template <class MemDepPred, class Impl>
318 MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
320 DPRINTF(MemDepUnit, "Marking registers as ready for "
321 "instruction PC %s [sn:%lli].\n",
322 inst->pcState(), inst->seqNum);
324 MemDepEntryPtr inst_entry = findInHash(inst);
326 inst_entry->regsReady = true;
328 if (inst_entry->memDepReady) {
329 DPRINTF(MemDepUnit, "Instruction has its memory "
330 "dependencies resolved, adding it to the ready list.\n");
332 moveToReady(inst_entry);
334 DPRINTF(MemDepUnit, "Instruction still waiting on "
335 "memory dependency.\n");
339 template <class MemDepPred, class Impl>
341 MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
343 DPRINTF(MemDepUnit, "Marking non speculative "
344 "instruction PC %s as ready [sn:%lli].\n",
345 inst->pcState(), inst->seqNum);
347 MemDepEntryPtr inst_entry = findInHash(inst);
349 moveToReady(inst_entry);
352 template <class MemDepPred, class Impl>
354 MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
356 instsToReplay.push_back(inst);
359 template <class MemDepPred, class Impl>
361 MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
363 DynInstPtr temp_inst;
365 // For now this replay function replays all waiting memory ops.
366 while (!instsToReplay.empty()) {
367 temp_inst = instsToReplay.front();
369 MemDepEntryPtr inst_entry = findInHash(temp_inst);
371 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
372 temp_inst->pcState(), temp_inst->seqNum);
374 moveToReady(inst_entry);
376 instsToReplay.pop_front();
380 template <class MemDepPred, class Impl>
382 MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
384 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
385 inst->pcState(), inst->seqNum);
387 ThreadID tid = inst->threadNumber;
389 // Remove the instruction from the hash and the list.
390 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
392 assert(hash_it != memDepHash.end());
394 instList[tid].erase((*hash_it).second->listIt);
396 (*hash_it).second = NULL;
398 memDepHash.erase(hash_it);
400 MemDepEntry::memdep_erase++;
404 template <class MemDepPred, class Impl>
406 MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
408 wakeDependents(inst);
411 InstSeqNum barr_sn = inst->seqNum;
412 DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
414 if (inst->isMemBarrier()) {
415 if (loadBarrierSN == barr_sn)
417 if (storeBarrierSN == barr_sn)
418 storeBarrier = false;
419 } else if (inst->isWriteBarrier()) {
420 if (storeBarrierSN == barr_sn)
421 storeBarrier = false;
425 template <class MemDepPred, class Impl>
427 MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
429 // Only stores and barriers have dependents.
430 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
434 MemDepEntryPtr inst_entry = findInHash(inst);
436 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
437 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
439 if (!woken_inst->inst) {
440 // Potentially removed mem dep entries could be on this list
444 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
446 woken_inst->inst->seqNum);
448 if (woken_inst->regsReady && !woken_inst->squashed) {
449 moveToReady(woken_inst);
451 woken_inst->memDepReady = true;
455 inst_entry->dependInsts.clear();
458 template <class MemDepPred, class Impl>
460 MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
463 if (!instsToReplay.empty()) {
464 ListIt replay_it = instsToReplay.begin();
465 while (replay_it != instsToReplay.end()) {
466 if ((*replay_it)->threadNumber == tid &&
467 (*replay_it)->seqNum > squashed_num) {
468 instsToReplay.erase(replay_it++);
475 ListIt squash_it = instList[tid].end();
478 MemDepHashIt hash_it;
480 while (!instList[tid].empty() &&
481 (*squash_it)->seqNum > squashed_num) {
483 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
484 (*squash_it)->seqNum);
486 if ((*squash_it)->seqNum == loadBarrierSN)
489 if ((*squash_it)->seqNum == storeBarrierSN)
490 storeBarrier = false;
492 hash_it = memDepHash.find((*squash_it)->seqNum);
494 assert(hash_it != memDepHash.end());
496 (*hash_it).second->squashed = true;
498 (*hash_it).second = NULL;
500 memDepHash.erase(hash_it);
502 MemDepEntry::memdep_erase++;
505 instList[tid].erase(squash_it--);
508 // Tell the dependency predictor to squash as well.
509 depPred.squash(squashed_num, tid);
512 template <class MemDepPred, class Impl>
514 MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
515 DynInstPtr &violating_load)
517 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
518 " load: %#x, store: %#x\n", violating_load->instAddr(),
519 store_inst->instAddr());
520 // Tell the memory dependence unit of the violation.
521 depPred.violation(store_inst->instAddr(), violating_load->instAddr());
524 template <class MemDepPred, class Impl>
526 MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
528 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
529 inst->instAddr(), inst->seqNum);
531 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
534 template <class MemDepPred, class Impl>
535 inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
536 MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
538 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
540 assert(hash_it != memDepHash.end());
542 return (*hash_it).second;
545 template <class MemDepPred, class Impl>
547 MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
549 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
550 "to the ready list.\n", woken_inst_entry->inst->seqNum);
552 assert(!woken_inst_entry->squashed);
554 iqPtr->addReadyMemInst(woken_inst_entry->inst);
558 template <class MemDepPred, class Impl>
560 MemDepUnit<MemDepPred, Impl>::dumpLists()
562 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
563 cprintf("Instruction list %i size: %i\n",
564 tid, instList[tid].size());
566 ListIt inst_list_it = instList[tid].begin();
569 while (inst_list_it != instList[tid].end()) {
570 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
572 num, (*inst_list_it)->pcState(),
573 (*inst_list_it)->seqNum,
574 (*inst_list_it)->threadNumber,
575 (*inst_list_it)->isIssued(),
576 (*inst_list_it)->isSquashed());
582 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
585 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);