src/cpu/o3/mips/cpu.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #ifndef __CPU_O3_MIPS_CPU_HH__
  33 #define __CPU_O3_MIPS_CPU_HH__
  34
  35 #include "arch/mips/regfile.hh"
  36 #include "arch/mips/syscallreturn.hh"
  37 #include "cpu/thread_context.hh"
  38 #include "cpu/o3/cpu.hh"
  39 #include "sim/byteswap.hh"
  40 #include "sim/faults.hh"
  41
  42 class EndQuiesceEvent;
  43 namespace Kernel {
  44     class Statistics;
  45 };
  46
  47 class TranslatingPort;
  48
  49 /**
  50  * MipsO3CPU class.  Derives from the FullO3CPU class, and
  51  * implements all ISA and implementation specific functions of the
  52  * CPU.  This is the CPU class that is used for the SimObjects, and is
  53  * what is given to the DynInsts.  Most of its state exists in the
  54  * FullO3CPU; the state is has is mainly for ISA specific
  55  * functionality.
  56  */
  57 template <class Impl>
  58 class MipsO3CPU : public FullO3CPU<Impl>
  59 {
  60   public:
  61     typedef O3ThreadState<Impl> ImplState;
  62     typedef O3ThreadState<Impl> Thread;
  63     typedef typename Impl::Params Params;
  64
  65     /** Constructs an MipsO3CPU with the given parameters. */
  66     MipsO3CPU(Params *params);
  67
  68     /** Registers statistics. */
  69     void regStats();
  70
  71     /** Translates instruction requestion in syscall emulation mode. */
  72     Fault translateInstReq(RequestPtr &req, Thread *thread)
  73     {
  74         return thread->getProcessPtr()->pTable->translate(req);
  75     }
  76
  77     /** Translates data read request in syscall emulation mode. */
  78     Fault translateDataReadReq(RequestPtr &req, Thread *thread)
  79     {
  80         return thread->getProcessPtr()->pTable->translate(req);
  81     }
  82
  83     /** Translates data write request in syscall emulation mode. */
  84     Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
  85     {
  86         return thread->getProcessPtr()->pTable->translate(req);
  87     }
  88
  89     /** Reads a miscellaneous register. */
  90     TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
  91
  92     /** Reads a misc. register, including any side effects the read
  93      * might have as defined by the architecture.
  94      */
  95     TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
  96
  97     /** Sets a miscellaneous register. */
  98     void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
  99
 100     /** Sets a misc. register, including any side effects the write
 101      * might have as defined by the architecture.
 102      */
 103     void setMiscRegWithEffect(int misc_reg,
 104             const TheISA::MiscReg &val, unsigned tid);
 105
 106     /** Initiates a squash of all in-flight instructions for a given
 107      * thread.  The source of the squash is an external update of
 108      * state through the TC.
 109      */
 110     void squashFromTC(unsigned tid);
 111
 112     /** Traps to handle given fault. */
 113     void trap(Fault fault, unsigned tid);
 114
 115     /** Executes a syscall.
 116      * @todo: Determine if this needs to be virtual.
 117      */
 118     void syscall(int64_t callnum, int tid);
 119     /** Gets a syscall argument. */
 120     TheISA::IntReg getSyscallArg(int i, int tid);
 121
 122     /** Used to shift args for indirect syscall. */
 123     void setSyscallArg(int i, TheISA::IntReg val, int tid);
 124
 125     /** Sets the return value of a syscall. */
 126     void setSyscallReturn(SyscallReturn return_value, int tid);
 127
 128     /** CPU read function, forwards read to LSQ. */
 129     template <class T>
 130     Fault read(RequestPtr &req, T &data, int load_idx)
 131     {
 132         return this->iew.ldstQueue.read(req, data, load_idx);
 133     }
 134
 135     /** CPU write function, forwards write to LSQ. */
 136     template <class T>
 137     Fault write(RequestPtr &req, T &data, int store_idx)
 138     {
 139         return this->iew.ldstQueue.write(req, data, store_idx);
 140     }
 141
 142     Addr lockAddr;
 143
 144     /** Temporary fix for the lock flag, works in the UP case. */
 145     bool lockFlag;
 146 };
 147
 148 #endif // __CPU_O3_MIPS_CPU_HH__