src/cpu/o3/mips/cpu_builder.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include <string>
  33
  34 #include "cpu/base.hh"
  35 #include "cpu/o3/mips/cpu.hh"
  36 #include "cpu/o3/mips/impl.hh"
  37 #include "cpu/o3/mips/params.hh"
  38 #include "cpu/o3/fu_pool.hh"
  39 #include "sim/builder.hh"
  40
  41 class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
  42 {
  43   public:
  44     DerivO3CPU(MipsSimpleParams *p)
  45         : MipsO3CPU<MipsSimpleImpl>(p)
  46     { }
  47 };
  48
  49 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
  50
  51 Param<int> clock;
  52 Param<int> phase;
  53 Param<int> numThreads;
  54 Param<int> activity;
  55
  56 SimObjectVectorParam<Process *> workload;
  57
  58 SimObjectParam<BaseCPU *> checker;
  59
  60 Param<Counter> max_insts_any_thread;
  61 Param<Counter> max_insts_all_threads;
  62 Param<Counter> max_loads_any_thread;
  63 Param<Counter> max_loads_all_threads;
  64
  65 Param<unsigned> cachePorts;
  66
  67 Param<unsigned> decodeToFetchDelay;
  68 Param<unsigned> renameToFetchDelay;
  69 Param<unsigned> iewToFetchDelay;
  70 Param<unsigned> commitToFetchDelay;
  71 Param<unsigned> fetchWidth;
  72
  73 Param<unsigned> renameToDecodeDelay;
  74 Param<unsigned> iewToDecodeDelay;
  75 Param<unsigned> commitToDecodeDelay;
  76 Param<unsigned> fetchToDecodeDelay;
  77 Param<unsigned> decodeWidth;
  78
  79 Param<unsigned> iewToRenameDelay;
  80 Param<unsigned> commitToRenameDelay;
  81 Param<unsigned> decodeToRenameDelay;
  82 Param<unsigned> renameWidth;
  83
  84 Param<unsigned> commitToIEWDelay;
  85 Param<unsigned> renameToIEWDelay;
  86 Param<unsigned> issueToExecuteDelay;
  87 Param<unsigned> dispatchWidth;
  88 Param<unsigned> issueWidth;
  89 Param<unsigned> wbWidth;
  90 Param<unsigned> wbDepth;
  91 SimObjectParam<FUPool *> fuPool;
  92
  93 Param<unsigned> iewToCommitDelay;
  94 Param<unsigned> renameToROBDelay;
  95 Param<unsigned> commitWidth;
  96 Param<unsigned> squashWidth;
  97 Param<Tick> trapLatency;
  98
  99 Param<unsigned> backComSize;
 100 Param<unsigned> forwardComSize;
 101
 102 Param<std::string> predType;
 103 Param<unsigned> localPredictorSize;
 104 Param<unsigned> localCtrBits;
 105 Param<unsigned> localHistoryTableSize;
 106 Param<unsigned> localHistoryBits;
 107 Param<unsigned> globalPredictorSize;
 108 Param<unsigned> globalCtrBits;
 109 Param<unsigned> globalHistoryBits;
 110 Param<unsigned> choicePredictorSize;
 111 Param<unsigned> choiceCtrBits;
 112
 113 Param<unsigned> BTBEntries;
 114 Param<unsigned> BTBTagSize;
 115
 116 Param<unsigned> RASSize;
 117
 118 Param<unsigned> LQEntries;
 119 Param<unsigned> SQEntries;
 120 Param<unsigned> LFSTSize;
 121 Param<unsigned> SSITSize;
 122
 123 Param<unsigned> numPhysIntRegs;
 124 Param<unsigned> numPhysFloatRegs;
 125 Param<unsigned> numIQEntries;
 126 Param<unsigned> numROBEntries;
 127
 128 Param<unsigned> smtNumFetchingThreads;
 129 Param<std::string>   smtFetchPolicy;
 130 Param<std::string>   smtLSQPolicy;
 131 Param<unsigned> smtLSQThreshold;
 132 Param<std::string>   smtIQPolicy;
 133 Param<unsigned> smtIQThreshold;
 134 Param<std::string>   smtROBPolicy;
 135 Param<unsigned> smtROBThreshold;
 136 Param<std::string>   smtCommitPolicy;
 137
 138 Param<unsigned> instShiftAmt;
 139
 140 Param<bool> defer_registration;
 141
 142 Param<bool> function_trace;
 143 Param<Tick> function_trace_start;
 144
 145 END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
 146
 147 BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
 148
 149     INIT_PARAM(clock, "clock speed"),
 150     INIT_PARAM_DFLT(phase, "clock phase", 0),
 151     INIT_PARAM(numThreads, "number of HW thread contexts"),
 152     INIT_PARAM_DFLT(activity, "Initial activity count", 0),
 153
 154     INIT_PARAM(workload, "Processes to run"),
 155
 156     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 157
 158     INIT_PARAM_DFLT(max_insts_any_thread,
 159                     "Terminate when any thread reaches this inst count",
 160                     0),
 161     INIT_PARAM_DFLT(max_insts_all_threads,
 162                     "Terminate when all threads have reached"
 163                     "this inst count",
 164                     0),
 165     INIT_PARAM_DFLT(max_loads_any_thread,
 166                     "Terminate when any thread reaches this load count",
 167                     0),
 168     INIT_PARAM_DFLT(max_loads_all_threads,
 169                     "Terminate when all threads have reached this load"
 170                     "count",
 171                     0),
 172
 173     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
 174
 175     INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
 176     INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
 177     INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
 178                "delay"),
 179     INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
 180     INIT_PARAM(fetchWidth, "Fetch width"),
 181     INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
 182     INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
 183                "delay"),
 184     INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
 185     INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
 186     INIT_PARAM(decodeWidth, "Decode width"),
 187
 188     INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
 189                "delay"),
 190     INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
 191     INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
 192     INIT_PARAM(renameWidth, "Rename width"),
 193
 194     INIT_PARAM(commitToIEWDelay, "Commit to "
 195                "Issue/Execute/Writeback delay"),
 196     INIT_PARAM(renameToIEWDelay, "Rename to "
 197                "Issue/Execute/Writeback delay"),
 198     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
 199                "to the IEW stage)"),
 200     INIT_PARAM(dispatchWidth, "Dispatch width"),
 201     INIT_PARAM(issueWidth, "Issue width"),
 202     INIT_PARAM(wbWidth, "Writeback width"),
 203     INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
 204     INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
 205
 206     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
 207                "delay"),
 208     INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
 209     INIT_PARAM(commitWidth, "Commit width"),
 210     INIT_PARAM(squashWidth, "Squash width"),
 211     INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
 212
 213     INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
 214     INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
 215
 216     INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
 217     INIT_PARAM(localPredictorSize, "Size of local predictor"),
 218     INIT_PARAM(localCtrBits, "Bits per counter"),
 219     INIT_PARAM(localHistoryTableSize, "Size of local history table"),
 220     INIT_PARAM(localHistoryBits, "Bits for the local history"),
 221     INIT_PARAM(globalPredictorSize, "Size of global predictor"),
 222     INIT_PARAM(globalCtrBits, "Bits per counter"),
 223     INIT_PARAM(globalHistoryBits, "Bits of history"),
 224     INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
 225     INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
 226
 227     INIT_PARAM(BTBEntries, "Number of BTB entries"),
 228     INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
 229
 230     INIT_PARAM(RASSize, "RAS size"),
 231
 232     INIT_PARAM(LQEntries, "Number of load queue entries"),
 233     INIT_PARAM(SQEntries, "Number of store queue entries"),
 234     INIT_PARAM(LFSTSize, "Last fetched store table size"),
 235     INIT_PARAM(SSITSize, "Store set ID table size"),
 236
 237     INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
 238     INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
 239                "registers"),
 240     INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
 241     INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
 242
 243     INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
 244     INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
 245     INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
 246     INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
 247     INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
 248     INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
 249     INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
 250     INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
 251     INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
 252
 253     INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
 254     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 255
 256     INIT_PARAM(function_trace, "Enable function trace"),
 257     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 258
 259 END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
 260
 261 CREATE_SIM_OBJECT(DerivO3CPU)
 262 {
 263     DerivO3CPU *cpu;
 264
 265     // In non-full-system mode, we infer the number of threads from
 266     // the workload if it's not explicitly specified.
 267     int actual_num_threads =
 268         (numThreads.isValid() && numThreads >= workload.size()) ?
 269          numThreads : workload.size();
 270
 271     if (workload.size() == 0) {
 272         fatal("Must specify at least one workload!");
 273     }
 274
 275     MipsSimpleParams *params = new MipsSimpleParams;
 276
 277     params->clock = clock;
 278
 279     params->name = getInstanceName();
 280     params->numberOfThreads = actual_num_threads;
 281     params->activity = activity;
 282
 283     params->workload = workload;
 284
 285     params->checker = checker;
 286
 287     params->max_insts_any_thread = max_insts_any_thread;
 288     params->max_insts_all_threads = max_insts_all_threads;
 289     params->max_loads_any_thread = max_loads_any_thread;
 290     params->max_loads_all_threads = max_loads_all_threads;
 291
 292     //
 293     // Caches
 294     //
 295     params->cachePorts = cachePorts;
 296
 297     params->decodeToFetchDelay = decodeToFetchDelay;
 298     params->renameToFetchDelay = renameToFetchDelay;
 299     params->iewToFetchDelay = iewToFetchDelay;
 300     params->commitToFetchDelay = commitToFetchDelay;
 301     params->fetchWidth = fetchWidth;
 302
 303     params->renameToDecodeDelay = renameToDecodeDelay;
 304     params->iewToDecodeDelay = iewToDecodeDelay;
 305     params->commitToDecodeDelay = commitToDecodeDelay;
 306     params->fetchToDecodeDelay = fetchToDecodeDelay;
 307     params->decodeWidth = decodeWidth;
 308
 309     params->iewToRenameDelay = iewToRenameDelay;
 310     params->commitToRenameDelay = commitToRenameDelay;
 311     params->decodeToRenameDelay = decodeToRenameDelay;
 312     params->renameWidth = renameWidth;
 313
 314     params->commitToIEWDelay = commitToIEWDelay;
 315     params->renameToIEWDelay = renameToIEWDelay;
 316     params->issueToExecuteDelay = issueToExecuteDelay;
 317     params->dispatchWidth = dispatchWidth;
 318     params->issueWidth = issueWidth;
 319     params->wbWidth = wbWidth;
 320     params->wbDepth = wbDepth;
 321     params->fuPool = fuPool;
 322
 323     params->iewToCommitDelay = iewToCommitDelay;
 324     params->renameToROBDelay = renameToROBDelay;
 325     params->commitWidth = commitWidth;
 326     params->squashWidth = squashWidth;
 327     params->trapLatency = trapLatency;
 328
 329     params->backComSize = backComSize;
 330     params->forwardComSize = forwardComSize;
 331
 332     params->predType = predType;
 333     params->localPredictorSize = localPredictorSize;
 334     params->localCtrBits = localCtrBits;
 335     params->localHistoryTableSize = localHistoryTableSize;
 336     params->localHistoryBits = localHistoryBits;
 337     params->globalPredictorSize = globalPredictorSize;
 338     params->globalCtrBits = globalCtrBits;
 339     params->globalHistoryBits = globalHistoryBits;
 340     params->choicePredictorSize = choicePredictorSize;
 341     params->choiceCtrBits = choiceCtrBits;
 342
 343     params->BTBEntries = BTBEntries;
 344     params->BTBTagSize = BTBTagSize;
 345
 346     params->RASSize = RASSize;
 347
 348     params->LQEntries = LQEntries;
 349     params->SQEntries = SQEntries;
 350
 351     params->SSITSize = SSITSize;
 352     params->LFSTSize = LFSTSize;
 353
 354     params->numPhysIntRegs = numPhysIntRegs;
 355     params->numPhysFloatRegs = numPhysFloatRegs;
 356     params->numIQEntries = numIQEntries;
 357     params->numROBEntries = numROBEntries;
 358
 359     params->smtNumFetchingThreads = smtNumFetchingThreads;
 360
 361     // Default smtFetchPolicy to "RoundRobin", if necessary.
 362     std::string round_robin_policy = "RoundRobin";
 363     std::string single_thread = "SingleThread";
 364
 365     if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
 366         params->smtFetchPolicy = round_robin_policy;
 367     else
 368         params->smtFetchPolicy = smtFetchPolicy;
 369
 370     params->smtIQPolicy    = smtIQPolicy;
 371     params->smtLSQPolicy    = smtLSQPolicy;
 372     params->smtLSQThreshold = smtLSQThreshold;
 373     params->smtROBPolicy   = smtROBPolicy;
 374     params->smtROBThreshold = smtROBThreshold;
 375     params->smtCommitPolicy = smtCommitPolicy;
 376
 377     params->instShiftAmt = 2;
 378
 379     params->deferRegistration = defer_registration;
 380
 381     params->functionTrace = function_trace;
 382     params->functionTraceStart = function_trace_start;
 383
 384     cpu = new DerivO3CPU(params);
 385
 386     return cpu;
 387 }
 388
 389 REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
 390