2 * Copyright (c) 2006 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "cpu/base.hh"
35 #include "cpu/o3/mips/cpu.hh"
36 #include "cpu/o3/mips/impl.hh"
37 #include "cpu/o3/mips/params.hh"
38 #include "cpu/o3/fu_pool.hh"
39 #include "sim/builder.hh"
41 class DerivO3CPU
: public MipsO3CPU
<MipsSimpleImpl
>
44 DerivO3CPU(MipsSimpleParams
*p
)
45 : MipsO3CPU
<MipsSimpleImpl
>(p
)
49 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU
)
52 Param
<int> numThreads
;
55 SimObjectVectorParam
<Process
*> workload
;
57 SimObjectParam
<MemObject
*> mem
;
59 SimObjectParam
<BaseCPU
*> checker
;
61 Param
<Counter
> max_insts_any_thread
;
62 Param
<Counter
> max_insts_all_threads
;
63 Param
<Counter
> max_loads_any_thread
;
64 Param
<Counter
> max_loads_all_threads
;
66 Param
<unsigned> cachePorts
;
68 Param
<unsigned> decodeToFetchDelay
;
69 Param
<unsigned> renameToFetchDelay
;
70 Param
<unsigned> iewToFetchDelay
;
71 Param
<unsigned> commitToFetchDelay
;
72 Param
<unsigned> fetchWidth
;
74 Param
<unsigned> renameToDecodeDelay
;
75 Param
<unsigned> iewToDecodeDelay
;
76 Param
<unsigned> commitToDecodeDelay
;
77 Param
<unsigned> fetchToDecodeDelay
;
78 Param
<unsigned> decodeWidth
;
80 Param
<unsigned> iewToRenameDelay
;
81 Param
<unsigned> commitToRenameDelay
;
82 Param
<unsigned> decodeToRenameDelay
;
83 Param
<unsigned> renameWidth
;
85 Param
<unsigned> commitToIEWDelay
;
86 Param
<unsigned> renameToIEWDelay
;
87 Param
<unsigned> issueToExecuteDelay
;
88 Param
<unsigned> dispatchWidth
;
89 Param
<unsigned> issueWidth
;
90 Param
<unsigned> wbWidth
;
91 Param
<unsigned> wbDepth
;
92 SimObjectParam
<FUPool
*> fuPool
;
94 Param
<unsigned> iewToCommitDelay
;
95 Param
<unsigned> renameToROBDelay
;
96 Param
<unsigned> commitWidth
;
97 Param
<unsigned> squashWidth
;
98 Param
<Tick
> trapLatency
;
100 Param
<unsigned> backComSize
;
101 Param
<unsigned> forwardComSize
;
103 Param
<std::string
> predType
;
104 Param
<unsigned> localPredictorSize
;
105 Param
<unsigned> localCtrBits
;
106 Param
<unsigned> localHistoryTableSize
;
107 Param
<unsigned> localHistoryBits
;
108 Param
<unsigned> globalPredictorSize
;
109 Param
<unsigned> globalCtrBits
;
110 Param
<unsigned> globalHistoryBits
;
111 Param
<unsigned> choicePredictorSize
;
112 Param
<unsigned> choiceCtrBits
;
114 Param
<unsigned> BTBEntries
;
115 Param
<unsigned> BTBTagSize
;
117 Param
<unsigned> RASSize
;
119 Param
<unsigned> LQEntries
;
120 Param
<unsigned> SQEntries
;
121 Param
<unsigned> LFSTSize
;
122 Param
<unsigned> SSITSize
;
124 Param
<unsigned> numPhysIntRegs
;
125 Param
<unsigned> numPhysFloatRegs
;
126 Param
<unsigned> numIQEntries
;
127 Param
<unsigned> numROBEntries
;
129 Param
<unsigned> smtNumFetchingThreads
;
130 Param
<std::string
> smtFetchPolicy
;
131 Param
<std::string
> smtLSQPolicy
;
132 Param
<unsigned> smtLSQThreshold
;
133 Param
<std::string
> smtIQPolicy
;
134 Param
<unsigned> smtIQThreshold
;
135 Param
<std::string
> smtROBPolicy
;
136 Param
<unsigned> smtROBThreshold
;
137 Param
<std::string
> smtCommitPolicy
;
139 Param
<unsigned> instShiftAmt
;
141 Param
<bool> defer_registration
;
143 Param
<bool> function_trace
;
144 Param
<Tick
> function_trace_start
;
146 END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU
)
148 BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU
)
150 INIT_PARAM(clock
, "clock speed"),
151 INIT_PARAM(numThreads
, "number of HW thread contexts"),
152 INIT_PARAM_DFLT(activity
, "Initial activity count", 0),
154 INIT_PARAM(workload
, "Processes to run"),
156 INIT_PARAM(mem
, "Memory"),
158 INIT_PARAM_DFLT(checker
, "Checker CPU", NULL
),
160 INIT_PARAM_DFLT(max_insts_any_thread
,
161 "Terminate when any thread reaches this inst count",
163 INIT_PARAM_DFLT(max_insts_all_threads
,
164 "Terminate when all threads have reached"
167 INIT_PARAM_DFLT(max_loads_any_thread
,
168 "Terminate when any thread reaches this load count",
170 INIT_PARAM_DFLT(max_loads_all_threads
,
171 "Terminate when all threads have reached this load"
175 INIT_PARAM_DFLT(cachePorts
, "Cache Ports", 200),
177 INIT_PARAM(decodeToFetchDelay
, "Decode to fetch delay"),
178 INIT_PARAM(renameToFetchDelay
, "Rename to fetch delay"),
179 INIT_PARAM(iewToFetchDelay
, "Issue/Execute/Writeback to fetch"
181 INIT_PARAM(commitToFetchDelay
, "Commit to fetch delay"),
182 INIT_PARAM(fetchWidth
, "Fetch width"),
183 INIT_PARAM(renameToDecodeDelay
, "Rename to decode delay"),
184 INIT_PARAM(iewToDecodeDelay
, "Issue/Execute/Writeback to decode"
186 INIT_PARAM(commitToDecodeDelay
, "Commit to decode delay"),
187 INIT_PARAM(fetchToDecodeDelay
, "Fetch to decode delay"),
188 INIT_PARAM(decodeWidth
, "Decode width"),
190 INIT_PARAM(iewToRenameDelay
, "Issue/Execute/Writeback to rename"
192 INIT_PARAM(commitToRenameDelay
, "Commit to rename delay"),
193 INIT_PARAM(decodeToRenameDelay
, "Decode to rename delay"),
194 INIT_PARAM(renameWidth
, "Rename width"),
196 INIT_PARAM(commitToIEWDelay
, "Commit to "
197 "Issue/Execute/Writeback delay"),
198 INIT_PARAM(renameToIEWDelay
, "Rename to "
199 "Issue/Execute/Writeback delay"),
200 INIT_PARAM(issueToExecuteDelay
, "Issue to execute delay (internal"
201 "to the IEW stage)"),
202 INIT_PARAM(dispatchWidth
, "Dispatch width"),
203 INIT_PARAM(issueWidth
, "Issue width"),
204 INIT_PARAM(wbWidth
, "Writeback width"),
205 INIT_PARAM(wbDepth
, "Writeback depth (number of cycles it can buffer)"),
206 INIT_PARAM_DFLT(fuPool
, "Functional unit pool", NULL
),
208 INIT_PARAM(iewToCommitDelay
, "Issue/Execute/Writeback to commit "
210 INIT_PARAM(renameToROBDelay
, "Rename to reorder buffer delay"),
211 INIT_PARAM(commitWidth
, "Commit width"),
212 INIT_PARAM(squashWidth
, "Squash width"),
213 INIT_PARAM_DFLT(trapLatency
, "Number of cycles before the trap is handled", 6),
215 INIT_PARAM(backComSize
, "Time buffer size for backwards communication"),
216 INIT_PARAM(forwardComSize
, "Time buffer size for forward communication"),
218 INIT_PARAM(predType
, "Type of branch predictor ('local', 'tournament')"),
219 INIT_PARAM(localPredictorSize
, "Size of local predictor"),
220 INIT_PARAM(localCtrBits
, "Bits per counter"),
221 INIT_PARAM(localHistoryTableSize
, "Size of local history table"),
222 INIT_PARAM(localHistoryBits
, "Bits for the local history"),
223 INIT_PARAM(globalPredictorSize
, "Size of global predictor"),
224 INIT_PARAM(globalCtrBits
, "Bits per counter"),
225 INIT_PARAM(globalHistoryBits
, "Bits of history"),
226 INIT_PARAM(choicePredictorSize
, "Size of choice predictor"),
227 INIT_PARAM(choiceCtrBits
, "Bits of choice counters"),
229 INIT_PARAM(BTBEntries
, "Number of BTB entries"),
230 INIT_PARAM(BTBTagSize
, "Size of the BTB tags, in bits"),
232 INIT_PARAM(RASSize
, "RAS size"),
234 INIT_PARAM(LQEntries
, "Number of load queue entries"),
235 INIT_PARAM(SQEntries
, "Number of store queue entries"),
236 INIT_PARAM(LFSTSize
, "Last fetched store table size"),
237 INIT_PARAM(SSITSize
, "Store set ID table size"),
239 INIT_PARAM(numPhysIntRegs
, "Number of physical integer registers"),
240 INIT_PARAM(numPhysFloatRegs
, "Number of physical floating point "
242 INIT_PARAM(numIQEntries
, "Number of instruction queue entries"),
243 INIT_PARAM(numROBEntries
, "Number of reorder buffer entries"),
245 INIT_PARAM_DFLT(smtNumFetchingThreads
, "SMT Number of Fetching Threads", 1),
246 INIT_PARAM_DFLT(smtFetchPolicy
, "SMT Fetch Policy", "SingleThread"),
247 INIT_PARAM_DFLT(smtLSQPolicy
, "SMT LSQ Sharing Policy", "Partitioned"),
248 INIT_PARAM_DFLT(smtLSQThreshold
,"SMT LSQ Threshold", 100),
249 INIT_PARAM_DFLT(smtIQPolicy
, "SMT IQ Policy", "Partitioned"),
250 INIT_PARAM_DFLT(smtIQThreshold
, "SMT IQ Threshold", 100),
251 INIT_PARAM_DFLT(smtROBPolicy
, "SMT ROB Sharing Policy", "Partitioned"),
252 INIT_PARAM_DFLT(smtROBThreshold
,"SMT ROB Threshold", 100),
253 INIT_PARAM_DFLT(smtCommitPolicy
,"SMT Commit Fetch Policy", "RoundRobin"),
255 INIT_PARAM(instShiftAmt
, "Number of bits to shift instructions by"),
256 INIT_PARAM(defer_registration
, "defer system registration (for sampling)"),
258 INIT_PARAM(function_trace
, "Enable function trace"),
259 INIT_PARAM(function_trace_start
, "Cycle to start function trace")
261 END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU
)
263 CREATE_SIM_OBJECT(DerivO3CPU
)
267 // In non-full-system mode, we infer the number of threads from
268 // the workload if it's not explicitly specified.
269 int actual_num_threads
=
270 (numThreads
.isValid() && numThreads
>= workload
.size()) ?
271 numThreads
: workload
.size();
273 if (workload
.size() == 0) {
274 fatal("Must specify at least one workload!");
277 MipsSimpleParams
*params
= new MipsSimpleParams
;
279 params
->clock
= clock
;
281 params
->name
= getInstanceName();
282 params
->numberOfThreads
= actual_num_threads
;
283 params
->activity
= activity
;
285 params
->workload
= workload
;
289 params
->checker
= checker
;
291 params
->max_insts_any_thread
= max_insts_any_thread
;
292 params
->max_insts_all_threads
= max_insts_all_threads
;
293 params
->max_loads_any_thread
= max_loads_any_thread
;
294 params
->max_loads_all_threads
= max_loads_all_threads
;
299 params
->cachePorts
= cachePorts
;
301 params
->decodeToFetchDelay
= decodeToFetchDelay
;
302 params
->renameToFetchDelay
= renameToFetchDelay
;
303 params
->iewToFetchDelay
= iewToFetchDelay
;
304 params
->commitToFetchDelay
= commitToFetchDelay
;
305 params
->fetchWidth
= fetchWidth
;
307 params
->renameToDecodeDelay
= renameToDecodeDelay
;
308 params
->iewToDecodeDelay
= iewToDecodeDelay
;
309 params
->commitToDecodeDelay
= commitToDecodeDelay
;
310 params
->fetchToDecodeDelay
= fetchToDecodeDelay
;
311 params
->decodeWidth
= decodeWidth
;
313 params
->iewToRenameDelay
= iewToRenameDelay
;
314 params
->commitToRenameDelay
= commitToRenameDelay
;
315 params
->decodeToRenameDelay
= decodeToRenameDelay
;
316 params
->renameWidth
= renameWidth
;
318 params
->commitToIEWDelay
= commitToIEWDelay
;
319 params
->renameToIEWDelay
= renameToIEWDelay
;
320 params
->issueToExecuteDelay
= issueToExecuteDelay
;
321 params
->dispatchWidth
= dispatchWidth
;
322 params
->issueWidth
= issueWidth
;
323 params
->wbWidth
= wbWidth
;
324 params
->wbDepth
= wbDepth
;
325 params
->fuPool
= fuPool
;
327 params
->iewToCommitDelay
= iewToCommitDelay
;
328 params
->renameToROBDelay
= renameToROBDelay
;
329 params
->commitWidth
= commitWidth
;
330 params
->squashWidth
= squashWidth
;
331 params
->trapLatency
= trapLatency
;
333 params
->backComSize
= backComSize
;
334 params
->forwardComSize
= forwardComSize
;
336 params
->predType
= predType
;
337 params
->localPredictorSize
= localPredictorSize
;
338 params
->localCtrBits
= localCtrBits
;
339 params
->localHistoryTableSize
= localHistoryTableSize
;
340 params
->localHistoryBits
= localHistoryBits
;
341 params
->globalPredictorSize
= globalPredictorSize
;
342 params
->globalCtrBits
= globalCtrBits
;
343 params
->globalHistoryBits
= globalHistoryBits
;
344 params
->choicePredictorSize
= choicePredictorSize
;
345 params
->choiceCtrBits
= choiceCtrBits
;
347 params
->BTBEntries
= BTBEntries
;
348 params
->BTBTagSize
= BTBTagSize
;
350 params
->RASSize
= RASSize
;
352 params
->LQEntries
= LQEntries
;
353 params
->SQEntries
= SQEntries
;
355 params
->SSITSize
= SSITSize
;
356 params
->LFSTSize
= LFSTSize
;
358 params
->numPhysIntRegs
= numPhysIntRegs
;
359 params
->numPhysFloatRegs
= numPhysFloatRegs
;
360 params
->numIQEntries
= numIQEntries
;
361 params
->numROBEntries
= numROBEntries
;
363 params
->smtNumFetchingThreads
= smtNumFetchingThreads
;
365 // Default smtFetchPolicy to "RoundRobin", if necessary.
366 std::string round_robin_policy
= "RoundRobin";
367 std::string single_thread
= "SingleThread";
369 if (actual_num_threads
> 1 && single_thread
.compare(smtFetchPolicy
) == 0)
370 params
->smtFetchPolicy
= round_robin_policy
;
372 params
->smtFetchPolicy
= smtFetchPolicy
;
374 params
->smtIQPolicy
= smtIQPolicy
;
375 params
->smtLSQPolicy
= smtLSQPolicy
;
376 params
->smtLSQThreshold
= smtLSQThreshold
;
377 params
->smtROBPolicy
= smtROBPolicy
;
378 params
->smtROBThreshold
= smtROBThreshold
;
379 params
->smtCommitPolicy
= smtCommitPolicy
;
381 params
->instShiftAmt
= 2;
383 params
->deferRegistration
= defer_registration
;
385 params
->functionTrace
= function_trace
;
386 params
->functionTraceStart
= function_trace_start
;
388 cpu
= new DerivO3CPU(params
);
393 REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU
)