src/cpu/o3/mips/dyn_inst.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #ifndef __CPU_O3_MIPS_DYN_INST_HH__
  33 #define __CPU_O3_MIPS_DYN_INST_HH__
  34
  35 #include "arch/isa_traits.hh"
  36 #include "cpu/base_dyn_inst.hh"
  37 #include "cpu/inst_seq.hh"
  38 #include "cpu/o3/mips/cpu.hh"
  39 #include "cpu/o3/mips/impl.hh"
  40
  41 class Packet;
  42
  43 /**
  44  * Mostly implementation & ISA specific MipsDynInst. As with most
  45  * other classes in the new CPU model, it is templated on the Impl to
  46  * allow for passing in of all types, such as the CPU type and the ISA
  47  * type. The MipsDynInst serves as the primary interface to the CPU
  48  * for instructions that are executing.
  49  */
  50 template <class Impl>
  51 class MipsDynInst : public BaseDynInst<Impl>
  52 {
  53   public:
  54     /** Typedef for the CPU. */
  55     typedef typename Impl::O3CPU O3CPU;
  56
  57     /** Logical register index type. */
  58     typedef TheISA::RegIndex RegIndex;
  59     /** Integer register index type. */
  60     typedef TheISA::IntReg   IntReg;
  61     typedef TheISA::FloatReg FloatReg;
  62     typedef TheISA::FloatRegBits FloatRegBits;
  63     /** Misc register index type. */
  64     typedef TheISA::MiscReg  MiscReg;
  65
  66     enum {
  67         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  68         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
  69     };
  70
  71   public:
  72     /** BaseDynInst constructor given a binary instruction. */
  73     MipsDynInst(ExtMachInst inst,
  74                 Addr PC, Addr NPC,
  75                 Addr Pred_PC, Addr Pred_NPC,
  76                 InstSeqNum seq_num, O3CPU *cpu);
  77
  78     /** BaseDynInst constructor given a static inst pointer. */
  79     MipsDynInst(StaticInstPtr &_staticInst);
  80
  81     /** Executes the instruction.*/
  82     Fault execute();
  83
  84     /** Initiates the access.  Only valid for memory operations. */
  85     Fault initiateAcc();
  86
  87     /** Completes the access.  Only valid for memory operations. */
  88     Fault completeAcc(PacketPtr pkt);
  89
  90   private:
  91     /** Initializes variables. */
  92     void initVars();
  93
  94   public:
  95     /** Reads a miscellaneous register. */
  96     MiscReg readMiscReg(int misc_reg)
  97     {
  98         return this->cpu->readMiscReg(misc_reg, this->threadNumber);
  99     }
 100
 101     /** Reads a misc. register, including any side-effects the read
 102      * might have as defined by the architecture.
 103      */
 104     MiscReg readMiscRegWithEffect(int misc_reg)
 105     {
 106         return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
 107     }
 108
 109     /** Sets a misc. register. */
 110     void setMiscReg(int misc_reg, const MiscReg &val)
 111     {
 112         this->instResult.integer = val;
 113         this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
 114     }
 115
 116     /** Sets a misc. register, including any side-effects the write
 117      * might have as defined by the architecture.
 118      */
 119     void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 120     {
 121         return this->cpu->setMiscRegWithEffect(misc_reg, val,
 122                                                this->threadNumber);
 123     }
 124
 125     /** Calls a syscall. */
 126     void syscall(int64_t callnum);
 127
 128   public:
 129
 130     // The register accessor methods provide the index of the
 131     // instruction's operand (e.g., 0 or 1), not the architectural
 132     // register index, to simplify the implementation of register
 133     // renaming.  We find the architectural register index by indexing
 134     // into the instruction's own operand index table.  Note that a
 135     // raw pointer to the StaticInst is provided instead of a
 136     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 137     // long as these methods don't copy the pointer into any long-term
 138     // storage (which is pretty hard to imagine they would have reason
 139     // to do).
 140
 141     uint64_t readIntRegOperand(const StaticInst *si, int idx)
 142     {
 143         return this->cpu->readIntReg(this->_srcRegIdx[idx]);
 144     }
 145
 146     FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
 147     {
 148         return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
 149     }
 150
 151     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
 152     {
 153         return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
 154     }
 155
 156     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
 157                                          int width)
 158     {
 159         return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
 160     }
 161
 162     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
 163     {
 164         return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
 165     }
 166
 167     /** @todo: Make results into arrays so they can handle multiple dest
 168      *  registers.
 169      */
 170     void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
 171     {
 172         this->cpu->setIntReg(this->_destRegIdx[idx], val);
 173         BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
 174     }
 175
 176     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
 177                             int width)
 178     {
 179         this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
 180         BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
 181     }
 182
 183     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 184     {
 185         this->cpu->setFloatReg(this->_destRegIdx[idx], val);
 186         BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
 187     }
 188
 189     void setFloatRegOperandBits(const StaticInst *si, int idx,
 190                                 FloatRegBits val, int width)
 191     {
 192         this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
 193         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
 194     }
 195
 196     void setFloatRegOperandBits(const StaticInst *si, int idx,
 197                                 FloatRegBits val)
 198     {
 199         this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
 200         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
 201     }
 202
 203   public:
 204     /** Calculates EA part of a memory instruction. Currently unused,
 205      * though it may be useful in the future if we want to split
 206      * memory operations into EA calculation and memory access parts.
 207      */
 208     Fault calcEA()
 209     {
 210         return this->staticInst->eaCompInst()->execute(this, this->traceData);
 211     }
 212
 213     /** Does the memory access part of a memory instruction. Currently unused,
 214      * though it may be useful in the future if we want to split
 215      * memory operations into EA calculation and memory access parts.
 216      */
 217     Fault memAccess()
 218     {
 219         return this->staticInst->memAccInst()->execute(this, this->traceData);
 220     }
 221 };
 222
 223 #endif // __CPU_O3_MIPS_DYN_INST_HH__
 224