src/cpu/o3/regfile.hh

   1 /*
   2  * Copyright (c) 2016-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder. You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_O3_REGFILE_HH__
  43 #define __CPU_O3_REGFILE_HH__
  44
  45 #include <vector>
  46
  47 #include "arch/types.hh"
  48 #include "base/trace.hh"
  49 #include "config/the_isa.hh"
  50 #include "cpu/o3/comm.hh"
  51 #include "debug/IEW.hh"
  52 #include "enums/VecRegRenameMode.hh"
  53
  54 class UnifiedFreeList;
  55
  56 /**
  57  * Simple physical register file class.
  58  */
  59 class PhysRegFile
  60 {
  61   private:
  62
  63     using VecElem = TheISA::VecElem;
  64     using VecRegContainer = TheISA::VecRegContainer;
  65     using PhysIds = std::vector<PhysRegId>;
  66     using VecMode = Enums::VecRegRenameMode;
  67     using VecPredRegContainer = TheISA::VecPredRegContainer;
  68   public:
  69     using IdRange = std::pair<PhysIds::iterator,
  70                               PhysIds::iterator>;
  71   private:
  72     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
  73
  74     /** Integer register file. */
  75     std::vector<RegVal> intRegFile;
  76     std::vector<PhysRegId> intRegIds;
  77
  78     /** Floating point register file. */
  79     std::vector<RegVal> floatRegFile;
  80     std::vector<PhysRegId> floatRegIds;
  81
  82     /** Vector register file. */
  83     std::vector<VecRegContainer> vectorRegFile;
  84     std::vector<PhysRegId> vecRegIds;
  85     std::vector<PhysRegId> vecElemIds;
  86
  87     /** Predicate register file. */
  88     std::vector<VecPredRegContainer> vecPredRegFile;
  89     std::vector<PhysRegId> vecPredRegIds;
  90
  91     /** Condition-code register file. */
  92     std::vector<RegVal> ccRegFile;
  93     std::vector<PhysRegId> ccRegIds;
  94
  95     /** Misc Reg Ids */
  96     std::vector<PhysRegId> miscRegIds;
  97
  98     /**
  99      * Number of physical general purpose registers
 100      */
 101     unsigned numPhysicalIntRegs;
 102
 103     /**
 104      * Number of physical floating point registers
 105      */
 106     unsigned numPhysicalFloatRegs;
 107
 108     /**
 109      * Number of physical vector registers
 110      */
 111     unsigned numPhysicalVecRegs;
 112
 113     /**
 114      * Number of physical vector element registers
 115      */
 116     unsigned numPhysicalVecElemRegs;
 117
 118     /**
 119      * Number of physical predicate registers
 120      */
 121     unsigned numPhysicalVecPredRegs;
 122
 123     /**
 124      * Number of physical CC registers
 125      */
 126     unsigned numPhysicalCCRegs;
 127
 128     /** Total number of physical registers. */
 129     unsigned totalNumRegs;
 130
 131     /** Mode in which vector registers are addressed. */
 132     VecMode vecMode;
 133
 134   public:
 135     /**
 136      * Constructs a physical register file with the specified amount of
 137      * integer and floating point registers.
 138      */
 139     PhysRegFile(unsigned _numPhysicalIntRegs,
 140                 unsigned _numPhysicalFloatRegs,
 141                 unsigned _numPhysicalVecRegs,
 142                 unsigned _numPhysicalVecPredRegs,
 143                 unsigned _numPhysicalCCRegs,
 144                 VecMode vmode
 145                 );
 146
 147     /**
 148      * Destructor to free resources
 149      */
 150     ~PhysRegFile() {}
 151
 152     /** Initialize the free list */
 153     void initFreeList(UnifiedFreeList *freeList);
 154
 155     /** @return the number of integer physical registers. */
 156     unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
 157
 158     /** @return the number of floating-point physical registers. */
 159     unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
 160     /** @return the number of vector physical registers. */
 161     unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
 162     /** @return the number of predicate physical registers. */
 163     unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; }
 164
 165     /** @return the number of vector physical registers. */
 166     unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
 167
 168     /** @return the number of condition-code physical registers. */
 169     unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
 170
 171     /** @return the total number of physical registers. */
 172     unsigned totalNumPhysRegs() const { return totalNumRegs; }
 173
 174     /** Gets a misc register PhysRegIdPtr. */
 175     PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
 176         return &miscRegIds[reg_idx];
 177     }
 178
 179     /** Reads an integer register. */
 180     RegVal
 181     readIntReg(PhysRegIdPtr phys_reg) const
 182     {
 183         assert(phys_reg->isIntPhysReg());
 184
 185         DPRINTF(IEW, "RegFile: Access to int register %i, has data "
 186                 "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
 187         return intRegFile[phys_reg->index()];
 188     }
 189
 190     RegVal
 191     readFloatReg(PhysRegIdPtr phys_reg) const
 192     {
 193         assert(phys_reg->isFloatPhysReg());
 194
 195         RegVal floatRegBits = floatRegFile[phys_reg->index()];
 196
 197         DPRINTF(IEW, "RegFile: Access to float register %i as int, "
 198                 "has data %#x\n", phys_reg->index(), floatRegBits);
 199
 200         return floatRegBits;
 201     }
 202
 203     /** Reads a vector register. */
 204     const VecRegContainer &
 205     readVecReg(PhysRegIdPtr phys_reg) const
 206     {
 207         assert(phys_reg->isVectorPhysReg());
 208
 209         DPRINTF(IEW, "RegFile: Access to vector register %i, has "
 210                 "data %s\n", int(phys_reg->index()),
 211                 vectorRegFile[phys_reg->index()].print());
 212
 213         return vectorRegFile[phys_reg->index()];
 214     }
 215
 216     /** Reads a vector register for modification. */
 217     VecRegContainer &
 218     getWritableVecReg(PhysRegIdPtr phys_reg)
 219     {
 220         /* const_cast for not duplicating code above. */
 221         return const_cast<VecRegContainer&>(readVecReg(phys_reg));
 222     }
 223
 224     /** Reads a vector register lane. */
 225     template <typename VecElem, int LaneIdx>
 226     VecLaneT<VecElem, true>
 227     readVecLane(PhysRegIdPtr phys_reg) const
 228     {
 229         return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
 230     }
 231
 232     /** Reads a vector register lane. */
 233     template <typename VecElem>
 234     VecLaneT<VecElem, true>
 235     readVecLane(PhysRegIdPtr phys_reg) const
 236     {
 237         return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
 238     }
 239
 240     /** Get a vector register lane for modification. */
 241     template <typename LD>
 242     void
 243     setVecLane(PhysRegIdPtr phys_reg, const LD& val)
 244     {
 245         assert(phys_reg->isVectorPhysReg());
 246
 247         DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
 248                 int(phys_reg->index()), phys_reg->elemIndex(), val);
 249
 250         vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
 251                 phys_reg->elemIndex()) = val;
 252     }
 253
 254     /** Reads a vector element. */
 255     const VecElem &
 256     readVecElem(PhysRegIdPtr phys_reg) const
 257     {
 258         assert(phys_reg->isVectorPhysElem());
 259         auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
 260         const VecElem& val = ret[phys_reg->elemIndex()];
 261         DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
 262                 " has data %#x\n", phys_reg->elemIndex(),
 263                 int(phys_reg->index()), val);
 264
 265         return val;
 266     }
 267
 268     /** Reads a predicate register. */
 269     const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
 270     {
 271         assert(phys_reg->isVecPredPhysReg());
 272
 273         DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
 274                 "data %s\n", int(phys_reg->index()),
 275                 vecPredRegFile[phys_reg->index()].print());
 276
 277         return vecPredRegFile[phys_reg->index()];
 278     }
 279
 280     VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
 281     {
 282         /* const_cast for not duplicating code above. */
 283         return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
 284     }
 285
 286     /** Reads a condition-code register. */
 287     RegVal
 288     readCCReg(PhysRegIdPtr phys_reg)
 289     {
 290         assert(phys_reg->isCCPhysReg());
 291
 292         DPRINTF(IEW, "RegFile: Access to cc register %i, has "
 293                 "data %#x\n", phys_reg->index(),
 294                 ccRegFile[phys_reg->index()]);
 295
 296         return ccRegFile[phys_reg->index()];
 297     }
 298
 299     /** Sets an integer register to the given value. */
 300     void
 301     setIntReg(PhysRegIdPtr phys_reg, RegVal val)
 302     {
 303         assert(phys_reg->isIntPhysReg());
 304
 305         DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
 306                 phys_reg->index(), val);
 307
 308         if (!phys_reg->isZeroReg())
 309             intRegFile[phys_reg->index()] = val;
 310     }
 311
 312     void
 313     setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
 314     {
 315         assert(phys_reg->isFloatPhysReg());
 316
 317         DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
 318                 phys_reg->index(), (uint64_t)val);
 319
 320         if (!phys_reg->isZeroReg())
 321             floatRegFile[phys_reg->index()] = val;
 322     }
 323
 324     /** Sets a vector register to the given value. */
 325     void
 326     setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
 327     {
 328         assert(phys_reg->isVectorPhysReg());
 329
 330         DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
 331                 int(phys_reg->index()), val.print());
 332
 333         vectorRegFile[phys_reg->index()] = val;
 334     }
 335
 336     /** Sets a vector register to the given value. */
 337     void
 338     setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
 339     {
 340         assert(phys_reg->isVectorPhysElem());
 341
 342         DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
 343                 " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
 344
 345         vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
 346                 val;
 347     }
 348
 349     /** Sets a predicate register to the given value. */
 350     void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
 351     {
 352         assert(phys_reg->isVecPredPhysReg());
 353
 354         DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
 355                 int(phys_reg->index()), val.print());
 356
 357         vecPredRegFile[phys_reg->index()] = val;
 358     }
 359
 360     /** Sets a condition-code register to the given value. */
 361     void
 362     setCCReg(PhysRegIdPtr phys_reg, RegVal val)
 363     {
 364         assert(phys_reg->isCCPhysReg());
 365
 366         DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
 367                 phys_reg->index(), (uint64_t)val);
 368
 369         ccRegFile[phys_reg->index()] = val;
 370     }
 371
 372     /** Get the PhysRegIds of the elems of a vector register.
 373      * Auxiliary function to transition from Full vector mode to Elem mode.
 374      */
 375     IdRange getRegElemIds(PhysRegIdPtr reg);
 376
 377     /**
 378      * Get the PhysRegIds of the elems of all vector registers.
 379      * Auxiliary function to transition from Full vector mode to Elem mode
 380      * and to initialise the rename map.
 381      */
 382     IdRange getRegIds(RegClass cls);
 383
 384     /**
 385      * Get the true physical register id.
 386      * As many parts work with PhysRegIdPtr, we need to be able to produce
 387      * the pointer out of just class and register idx.
 388      */
 389     PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
 390 };
 391
 392
 393 #endif //__CPU_O3_REGFILE_HH__