src/cpu/o3/regfile.hh

   1 /*
   2  * Copyright (c) 2016 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder. You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  *          Gabe Black
  43  */
  44
  45 #ifndef __CPU_O3_REGFILE_HH__
  46 #define __CPU_O3_REGFILE_HH__
  47
  48 #include <vector>
  49
  50 #include "arch/isa_traits.hh"
  51 #include "arch/kernel_stats.hh"
  52 #include "arch/types.hh"
  53 #include "base/trace.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/o3/comm.hh"
  56 #include "debug/IEW.hh"
  57 #include "enums/VecRegRenameMode.hh"
  58
  59 class UnifiedFreeList;
  60
  61 /**
  62  * Simple physical register file class.
  63  */
  64 class PhysRegFile
  65 {
  66   private:
  67
  68     typedef TheISA::IntReg IntReg;
  69     typedef TheISA::FloatReg FloatReg;
  70     typedef TheISA::FloatRegBits FloatRegBits;
  71     typedef TheISA::CCReg CCReg;
  72     using VecElem = TheISA::VecElem;
  73     using VecRegContainer = TheISA::VecRegContainer;
  74     using PhysIds = std::vector<PhysRegId>;
  75     using VecMode = Enums::VecRegRenameMode;
  76   public:
  77     using IdRange = std::pair<PhysIds::const_iterator,
  78                               PhysIds::const_iterator>;
  79   private:
  80     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
  81
  82     typedef union {
  83         FloatReg d;
  84         FloatRegBits q;
  85     } PhysFloatReg;
  86
  87     /** Integer register file. */
  88     std::vector<IntReg> intRegFile;
  89     std::vector<PhysRegId> intRegIds;
  90
  91     /** Floating point register file. */
  92     std::vector<PhysFloatReg> floatRegFile;
  93     std::vector<PhysRegId> floatRegIds;
  94
  95     /** Vector register file. */
  96     std::vector<VecRegContainer> vectorRegFile;
  97     std::vector<PhysRegId> vecRegIds;
  98     std::vector<PhysRegId> vecElemIds;
  99
 100     /** Condition-code register file. */
 101     std::vector<CCReg> ccRegFile;
 102     std::vector<PhysRegId> ccRegIds;
 103
 104     /** Misc Reg Ids */
 105     std::vector<PhysRegId> miscRegIds;
 106
 107     /**
 108      * Number of physical general purpose registers
 109      */
 110     unsigned numPhysicalIntRegs;
 111
 112     /**
 113      * Number of physical floating point registers
 114      */
 115     unsigned numPhysicalFloatRegs;
 116
 117     /**
 118      * Number of physical vector registers
 119      */
 120     unsigned numPhysicalVecRegs;
 121
 122     /**
 123      * Number of physical vector element registers
 124      */
 125     unsigned numPhysicalVecElemRegs;
 126
 127     /**
 128      * Number of physical CC registers
 129      */
 130     unsigned numPhysicalCCRegs;
 131
 132     /** Total number of physical registers. */
 133     unsigned totalNumRegs;
 134
 135     /** Mode in which vector registers are addressed. */
 136     VecMode vecMode;
 137
 138   public:
 139     /**
 140      * Constructs a physical register file with the specified amount of
 141      * integer and floating point registers.
 142      */
 143     PhysRegFile(unsigned _numPhysicalIntRegs,
 144                 unsigned _numPhysicalFloatRegs,
 145                 unsigned _numPhysicalVecRegs,
 146                 unsigned _numPhysicalCCRegs,
 147                 VecMode vmode
 148                 );
 149
 150     /**
 151      * Destructor to free resources
 152      */
 153     ~PhysRegFile() {}
 154
 155     /** Initialize the free list */
 156     void initFreeList(UnifiedFreeList *freeList);
 157
 158     /** @return the number of integer physical registers. */
 159     unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
 160
 161     /** @return the number of floating-point physical registers. */
 162     unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
 163     /** @return the number of vector physical registers. */
 164     unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
 165
 166     /** @return the number of vector physical registers. */
 167     unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
 168
 169     /** @return the number of condition-code physical registers. */
 170     unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
 171
 172     /** @return the total number of physical registers. */
 173     unsigned totalNumPhysRegs() const { return totalNumRegs; }
 174
 175     /** Gets a misc register PhysRegIdPtr. */
 176     PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
 177         return &miscRegIds[reg_idx];
 178     }
 179
 180     /** Reads an integer register. */
 181     uint64_t readIntReg(PhysRegIdPtr phys_reg) const
 182     {
 183         assert(phys_reg->isIntPhysReg());
 184
 185         DPRINTF(IEW, "RegFile: Access to int register %i, has data "
 186                 "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
 187         return intRegFile[phys_reg->index()];
 188     }
 189
 190     /** Reads a floating point register (double precision). */
 191     FloatReg readFloatReg(PhysRegIdPtr phys_reg) const
 192     {
 193         assert(phys_reg->isFloatPhysReg());
 194
 195         DPRINTF(IEW, "RegFile: Access to float register %i, has "
 196                 "data %#x\n", phys_reg->index(),
 197                 floatRegFile[phys_reg->index()].q);
 198
 199         return floatRegFile[phys_reg->index()].d;
 200     }
 201
 202     FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const
 203     {
 204         assert(phys_reg->isFloatPhysReg());
 205
 206         FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q;
 207
 208         DPRINTF(IEW, "RegFile: Access to float register %i as int, "
 209                 "has data %#x\n", phys_reg->index(),
 210                 (uint64_t)floatRegBits);
 211
 212         return floatRegBits;
 213     }
 214
 215     /** Reads a vector register. */
 216     const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const
 217     {
 218         assert(phys_reg->isVectorPhysReg());
 219
 220         DPRINTF(IEW, "RegFile: Access to vector register %i, has "
 221                 "data %s\n", int(phys_reg->index()),
 222                 vectorRegFile[phys_reg->index()].as<VecElem>().print());
 223
 224         return vectorRegFile[phys_reg->index()];
 225     }
 226
 227     /** Reads a vector register for modification. */
 228     VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg)
 229     {
 230         /* const_cast for not duplicating code above. */
 231         return const_cast<VecRegContainer&>(readVecReg(phys_reg));
 232     }
 233
 234     /** Reads a vector register lane. */
 235     template <typename VecElem, int LaneIdx>
 236     VecLaneT<VecElem, true>
 237     readVecLane(PhysRegIdPtr phys_reg) const
 238     {
 239         return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
 240     }
 241
 242     /** Reads a vector register lane. */
 243     template <typename VecElem>
 244     VecLaneT<VecElem, true>
 245     readVecLane(PhysRegIdPtr phys_reg) const
 246     {
 247         return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
 248     }
 249
 250     /** Get a vector register lane for modification. */
 251     template <typename LD>
 252     void
 253     setVecLane(PhysRegIdPtr phys_reg, const LD& val)
 254     {
 255         assert(phys_reg->isVectorPhysReg());
 256
 257         DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
 258                 int(phys_reg->index()), phys_reg->elemIndex(), val);
 259
 260         vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
 261                 phys_reg->elemIndex()) = val;
 262     }
 263
 264     /** Reads a vector element. */
 265     const VecElem& readVecElem(PhysRegIdPtr phys_reg) const
 266     {
 267         assert(phys_reg->isVectorPhysElem());
 268         auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
 269         const VecElem& val = ret[phys_reg->elemIndex()];
 270         DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
 271                 " has data %#x\n", phys_reg->elemIndex(),
 272                 int(phys_reg->index()), val);
 273
 274         return val;
 275     }
 276
 277     /** Reads a condition-code register. */
 278     CCReg readCCReg(PhysRegIdPtr phys_reg)
 279     {
 280         assert(phys_reg->isCCPhysReg());
 281
 282         DPRINTF(IEW, "RegFile: Access to cc register %i, has "
 283                 "data %#x\n", phys_reg->index(),
 284                 ccRegFile[phys_reg->index()]);
 285
 286         return ccRegFile[phys_reg->index()];
 287     }
 288
 289     /** Sets an integer register to the given value. */
 290     void setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
 291     {
 292         assert(phys_reg->isIntPhysReg());
 293
 294         DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
 295                 phys_reg->index(), val);
 296
 297         if (!phys_reg->isZeroReg())
 298             intRegFile[phys_reg->index()] = val;
 299     }
 300
 301     /** Sets a double precision floating point register to the given value. */
 302     void setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
 303     {
 304         assert(phys_reg->isFloatPhysReg());
 305
 306         DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
 307                 phys_reg->index(), (uint64_t)val);
 308
 309         if (!phys_reg->isZeroReg())
 310             floatRegFile[phys_reg->index()].d = val;
 311     }
 312
 313     void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
 314     {
 315         assert(phys_reg->isFloatPhysReg());
 316
 317         DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
 318                 phys_reg->index(), (uint64_t)val);
 319
 320         if (!phys_reg->isZeroReg())
 321             floatRegFile[phys_reg->index()].q = val;
 322     }
 323
 324     /** Sets a vector register to the given value. */
 325     void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
 326     {
 327         assert(phys_reg->isVectorPhysReg());
 328
 329         DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
 330                 int(phys_reg->index()), val.print());
 331
 332         vectorRegFile[phys_reg->index()] = val;
 333     }
 334
 335     /** Sets a vector register to the given value. */
 336     void setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
 337     {
 338         assert(phys_reg->isVectorPhysElem());
 339
 340         DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
 341                 " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
 342
 343         vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
 344                 val;
 345     }
 346
 347     /** Sets a condition-code register to the given value. */
 348     void setCCReg(PhysRegIdPtr phys_reg, CCReg val)
 349     {
 350         assert(phys_reg->isCCPhysReg());
 351
 352         DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
 353                 phys_reg->index(), (uint64_t)val);
 354
 355         ccRegFile[phys_reg->index()] = val;
 356     }
 357
 358     /** Get the PhysRegIds of the elems of a vector register.
 359      * Auxiliary function to transition from Full vector mode to Elem mode.
 360      */
 361     IdRange getRegElemIds(PhysRegIdPtr reg);
 362
 363     /**
 364      * Get the PhysRegIds of the elems of all vector registers.
 365      * Auxiliary function to transition from Full vector mode to Elem mode
 366      * and to initialise the rename map.
 367      */
 368     IdRange getRegIds(RegClass cls);
 369
 370      /**
 371       * Get the true physical register id.
 372       * As many parts work with PhysRegIdPtr, we need to be able to produce
 373       * the pointer out of just class and register idx.
 374       */
 375      PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
 376 };
 377
 378
 379 #endif //__CPU_O3_REGFILE_HH__