2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __CPU_O3_REGFILE_HH__
33 #define __CPU_O3_REGFILE_HH__
35 #include "arch/isa_traits.hh"
36 #include "arch/types.hh"
37 #include "base/trace.hh"
38 #include "config/full_system.hh"
39 #include "cpu/o3/comm.hh"
40 #include "sim/faults.hh"
43 #include "kern/kernel_stats.hh"
50 * Simple physical register file class.
51 * Right now this is specific to Alpha until we decide if/how to make things
52 * generic enough to support other ISAs.
58 typedef TheISA::IntReg IntReg;
59 typedef TheISA::FloatReg FloatReg;
60 typedef TheISA::FloatRegBits FloatRegBits;
61 typedef TheISA::MiscRegFile MiscRegFile;
62 typedef TheISA::MiscReg MiscReg;
69 // Note that most of the definitions of the IntReg, FloatReg, etc. exist
70 // within the Impl/ISA class and not within this PhysRegFile class.
72 // Will make these registers public for now, but they probably should
73 // be private eventually with some accessor functions.
75 typedef typename Impl::O3CPU O3CPU;
78 * Constructs a physical register file with the specified amount of
79 * integer and floating point registers.
81 PhysRegFile(unsigned _numPhysicalIntRegs,
82 unsigned _numPhysicalFloatRegs);
84 //Everything below should be pretty well identical to the normal
85 //register file that exists within AlphaISA class.
86 //The duplication is unfortunate but it's better than having
87 //different ways to access certain registers.
89 /** Reads an integer register. */
90 uint64_t readIntReg(PhysRegIndex reg_idx)
92 assert(reg_idx < numPhysicalIntRegs);
94 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
95 "%#x\n", int(reg_idx), intRegFile[reg_idx]);
96 return intRegFile[reg_idx];
99 FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
101 // Remove the base Float reg dependency.
102 reg_idx = reg_idx - numPhysicalIntRegs;
104 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
106 FloatReg floatReg = floatRegFile[reg_idx].d;
108 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
109 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
114 /** Reads a floating point register (double precision). */
115 FloatReg readFloatReg(PhysRegIndex reg_idx)
117 // Remove the base Float reg dependency.
118 reg_idx = reg_idx - numPhysicalIntRegs;
120 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
122 FloatReg floatReg = floatRegFile[reg_idx].d;
124 DPRINTF(IEW, "RegFile: Access to float register %i, has "
125 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
130 /** Reads a floating point register as an integer. */
131 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
133 // Remove the base Float reg dependency.
134 reg_idx = reg_idx - numPhysicalIntRegs;
136 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
138 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
140 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
141 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
146 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
148 // Remove the base Float reg dependency.
149 reg_idx = reg_idx - numPhysicalIntRegs;
151 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
153 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
155 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
156 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
161 /** Sets an integer register to the given value. */
162 void setIntReg(PhysRegIndex reg_idx, uint64_t val)
164 assert(reg_idx < numPhysicalIntRegs);
166 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
169 if (reg_idx != TheISA::ZeroReg)
170 intRegFile[reg_idx] = val;
173 /** Sets a single precision floating point register to the given value. */
174 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
176 // Remove the base Float reg dependency.
177 reg_idx = reg_idx - numPhysicalIntRegs;
179 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
181 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
182 int(reg_idx), (uint64_t)val);
184 if (reg_idx != TheISA::ZeroReg)
185 floatRegFile[reg_idx].d = val;
188 /** Sets a double precision floating point register to the given value. */
189 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
191 // Remove the base Float reg dependency.
192 reg_idx = reg_idx - numPhysicalIntRegs;
194 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
196 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
197 int(reg_idx), (uint64_t)val);
199 if (reg_idx != TheISA::ZeroReg)
200 floatRegFile[reg_idx].d = val;
203 /** Sets a floating point register to the given integer value. */
204 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
206 // Remove the base Float reg dependency.
207 reg_idx = reg_idx - numPhysicalIntRegs;
209 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
211 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
212 int(reg_idx), (uint64_t)val);
214 floatRegFile[reg_idx].q = val;
217 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
219 // Remove the base Float reg dependency.
220 reg_idx = reg_idx - numPhysicalIntRegs;
222 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
224 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
225 int(reg_idx), (uint64_t)val);
227 floatRegFile[reg_idx].q = val;
230 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
232 return miscRegs[thread_id].readReg(misc_reg);
235 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
238 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
239 cpu->tcBase(thread_id));
242 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
244 return miscRegs[thread_id].setReg(misc_reg, val);
247 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
250 return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
251 cpu->tcBase(thread_id));
255 int readIntrFlag() { return intrflag; }
256 /** Sets an interrupt flag. */
257 void setIntrFlag(int val) { intrflag = val; }
261 /** (signed) integer register file. */
264 /** Floating point register file. */
265 PhysFloatReg *floatRegFile;
267 /** Miscellaneous register file. */
268 MiscRegFile miscRegs[Impl::MaxThreads];
272 int intrflag; // interrupt flag
280 /** Sets the CPU pointer. */
281 void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; }
283 /** Number of physical integer registers. */
284 unsigned numPhysicalIntRegs;
285 /** Number of physical floating point registers. */
286 unsigned numPhysicalFloatRegs;
289 template <class Impl>
290 PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
291 unsigned _numPhysicalFloatRegs)
292 : numPhysicalIntRegs(_numPhysicalIntRegs),
293 numPhysicalFloatRegs(_numPhysicalFloatRegs)
295 intRegFile = new IntReg[numPhysicalIntRegs];
296 floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
298 for (int i = 0; i < Impl::MaxThreads; ++i) {
302 memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
303 memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);