src/cpu/o3/regfile.hh

   1 /*
   2  * Copyright (c) 2016 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder. You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  *          Gabe Black
  43  */
  44
  45 #ifndef __CPU_O3_REGFILE_HH__
  46 #define __CPU_O3_REGFILE_HH__
  47
  48 #include <vector>
  49
  50 #include "arch/isa_traits.hh"
  51 #include "arch/kernel_stats.hh"
  52 #include "arch/types.hh"
  53 #include "base/trace.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/o3/comm.hh"
  56 #include "debug/IEW.hh"
  57 #include "enums/VecRegRenameMode.hh"
  58
  59 class UnifiedFreeList;
  60
  61 /**
  62  * Simple physical register file class.
  63  */
  64 class PhysRegFile
  65 {
  66   private:
  67
  68     typedef TheISA::CCReg CCReg;
  69     using VecElem = TheISA::VecElem;
  70     using VecRegContainer = TheISA::VecRegContainer;
  71     using PhysIds = std::vector<PhysRegId>;
  72     using VecMode = Enums::VecRegRenameMode;
  73   public:
  74     using IdRange = std::pair<PhysIds::const_iterator,
  75                               PhysIds::const_iterator>;
  76   private:
  77     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
  78
  79     /** Integer register file. */
  80     std::vector<RegVal> intRegFile;
  81     std::vector<PhysRegId> intRegIds;
  82
  83     /** Floating point register file. */
  84     std::vector<RegVal> floatRegFile;
  85     std::vector<PhysRegId> floatRegIds;
  86
  87     /** Vector register file. */
  88     std::vector<VecRegContainer> vectorRegFile;
  89     std::vector<PhysRegId> vecRegIds;
  90     std::vector<PhysRegId> vecElemIds;
  91
  92     /** Condition-code register file. */
  93     std::vector<CCReg> ccRegFile;
  94     std::vector<PhysRegId> ccRegIds;
  95
  96     /** Misc Reg Ids */
  97     std::vector<PhysRegId> miscRegIds;
  98
  99     /**
 100      * Number of physical general purpose registers
 101      */
 102     unsigned numPhysicalIntRegs;
 103
 104     /**
 105      * Number of physical floating point registers
 106      */
 107     unsigned numPhysicalFloatRegs;
 108
 109     /**
 110      * Number of physical vector registers
 111      */
 112     unsigned numPhysicalVecRegs;
 113
 114     /**
 115      * Number of physical vector element registers
 116      */
 117     unsigned numPhysicalVecElemRegs;
 118
 119     /**
 120      * Number of physical CC registers
 121      */
 122     unsigned numPhysicalCCRegs;
 123
 124     /** Total number of physical registers. */
 125     unsigned totalNumRegs;
 126
 127     /** Mode in which vector registers are addressed. */
 128     VecMode vecMode;
 129
 130   public:
 131     /**
 132      * Constructs a physical register file with the specified amount of
 133      * integer and floating point registers.
 134      */
 135     PhysRegFile(unsigned _numPhysicalIntRegs,
 136                 unsigned _numPhysicalFloatRegs,
 137                 unsigned _numPhysicalVecRegs,
 138                 unsigned _numPhysicalCCRegs,
 139                 VecMode vmode
 140                 );
 141
 142     /**
 143      * Destructor to free resources
 144      */
 145     ~PhysRegFile() {}
 146
 147     /** Initialize the free list */
 148     void initFreeList(UnifiedFreeList *freeList);
 149
 150     /** @return the number of integer physical registers. */
 151     unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
 152
 153     /** @return the number of floating-point physical registers. */
 154     unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
 155     /** @return the number of vector physical registers. */
 156     unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
 157
 158     /** @return the number of vector physical registers. */
 159     unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
 160
 161     /** @return the number of condition-code physical registers. */
 162     unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
 163
 164     /** @return the total number of physical registers. */
 165     unsigned totalNumPhysRegs() const { return totalNumRegs; }
 166
 167     /** Gets a misc register PhysRegIdPtr. */
 168     PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
 169         return &miscRegIds[reg_idx];
 170     }
 171
 172     /** Reads an integer register. */
 173     RegVal
 174     readIntReg(PhysRegIdPtr phys_reg) const
 175     {
 176         assert(phys_reg->isIntPhysReg());
 177
 178         DPRINTF(IEW, "RegFile: Access to int register %i, has data "
 179                 "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
 180         return intRegFile[phys_reg->index()];
 181     }
 182
 183     RegVal
 184     readFloatRegBits(PhysRegIdPtr phys_reg) const
 185     {
 186         assert(phys_reg->isFloatPhysReg());
 187
 188         RegVal floatRegBits = floatRegFile[phys_reg->index()];
 189
 190         DPRINTF(IEW, "RegFile: Access to float register %i as int, "
 191                 "has data %#x\n", phys_reg->index(), floatRegBits);
 192
 193         return floatRegBits;
 194     }
 195
 196     /** Reads a vector register. */
 197     const VecRegContainer &
 198     readVecReg(PhysRegIdPtr phys_reg) const
 199     {
 200         assert(phys_reg->isVectorPhysReg());
 201
 202         DPRINTF(IEW, "RegFile: Access to vector register %i, has "
 203                 "data %s\n", int(phys_reg->index()),
 204                 vectorRegFile[phys_reg->index()].as<VecElem>().print());
 205
 206         return vectorRegFile[phys_reg->index()];
 207     }
 208
 209     /** Reads a vector register for modification. */
 210     VecRegContainer &
 211     getWritableVecReg(PhysRegIdPtr phys_reg)
 212     {
 213         /* const_cast for not duplicating code above. */
 214         return const_cast<VecRegContainer&>(readVecReg(phys_reg));
 215     }
 216
 217     /** Reads a vector register lane. */
 218     template <typename VecElem, int LaneIdx>
 219     VecLaneT<VecElem, true>
 220     readVecLane(PhysRegIdPtr phys_reg) const
 221     {
 222         return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
 223     }
 224
 225     /** Reads a vector register lane. */
 226     template <typename VecElem>
 227     VecLaneT<VecElem, true>
 228     readVecLane(PhysRegIdPtr phys_reg) const
 229     {
 230         return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
 231     }
 232
 233     /** Get a vector register lane for modification. */
 234     template <typename LD>
 235     void
 236     setVecLane(PhysRegIdPtr phys_reg, const LD& val)
 237     {
 238         assert(phys_reg->isVectorPhysReg());
 239
 240         DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
 241                 int(phys_reg->index()), phys_reg->elemIndex(), val);
 242
 243         vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
 244                 phys_reg->elemIndex()) = val;
 245     }
 246
 247     /** Reads a vector element. */
 248     const VecElem &
 249     readVecElem(PhysRegIdPtr phys_reg) const
 250     {
 251         assert(phys_reg->isVectorPhysElem());
 252         auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
 253         const VecElem& val = ret[phys_reg->elemIndex()];
 254         DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
 255                 " has data %#x\n", phys_reg->elemIndex(),
 256                 int(phys_reg->index()), val);
 257
 258         return val;
 259     }
 260
 261     /** Reads a condition-code register. */
 262     CCReg
 263     readCCReg(PhysRegIdPtr phys_reg)
 264     {
 265         assert(phys_reg->isCCPhysReg());
 266
 267         DPRINTF(IEW, "RegFile: Access to cc register %i, has "
 268                 "data %#x\n", phys_reg->index(),
 269                 ccRegFile[phys_reg->index()]);
 270
 271         return ccRegFile[phys_reg->index()];
 272     }
 273
 274     /** Sets an integer register to the given value. */
 275     void
 276     setIntReg(PhysRegIdPtr phys_reg, RegVal val)
 277     {
 278         assert(phys_reg->isIntPhysReg());
 279
 280         DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
 281                 phys_reg->index(), val);
 282
 283         if (!phys_reg->isZeroReg())
 284             intRegFile[phys_reg->index()] = val;
 285     }
 286
 287     void
 288     setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
 289     {
 290         assert(phys_reg->isFloatPhysReg());
 291
 292         DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
 293                 phys_reg->index(), (uint64_t)val);
 294
 295         if (!phys_reg->isZeroReg())
 296             floatRegFile[phys_reg->index()] = val;
 297     }
 298
 299     /** Sets a vector register to the given value. */
 300     void
 301     setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
 302     {
 303         assert(phys_reg->isVectorPhysReg());
 304
 305         DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
 306                 int(phys_reg->index()), val.print());
 307
 308         vectorRegFile[phys_reg->index()] = val;
 309     }
 310
 311     /** Sets a vector register to the given value. */
 312     void
 313     setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
 314     {
 315         assert(phys_reg->isVectorPhysElem());
 316
 317         DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
 318                 " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
 319
 320         vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
 321                 val;
 322     }
 323
 324     /** Sets a condition-code register to the given value. */
 325     void
 326     setCCReg(PhysRegIdPtr phys_reg, CCReg val)
 327     {
 328         assert(phys_reg->isCCPhysReg());
 329
 330         DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
 331                 phys_reg->index(), (uint64_t)val);
 332
 333         ccRegFile[phys_reg->index()] = val;
 334     }
 335
 336     /** Get the PhysRegIds of the elems of a vector register.
 337      * Auxiliary function to transition from Full vector mode to Elem mode.
 338      */
 339     IdRange getRegElemIds(PhysRegIdPtr reg);
 340
 341     /**
 342      * Get the PhysRegIds of the elems of all vector registers.
 343      * Auxiliary function to transition from Full vector mode to Elem mode
 344      * and to initialise the rename map.
 345      */
 346     IdRange getRegIds(RegClass cls);
 347
 348     /**
 349      * Get the true physical register id.
 350      * As many parts work with PhysRegIdPtr, we need to be able to produce
 351      * the pointer out of just class and register idx.
 352      */
 353     PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
 354 };
 355
 356
 357 #endif //__CPU_O3_REGFILE_HH__