src/cpu/o3/rename.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_O3_RENAME_HH__
  32 #define __CPU_O3_RENAME_HH__
  33
  34 #include <list>
  35
  36 #include "base/statistics.hh"
  37 #include "base/timebuf.hh"
  38
  39 /**
  40  * DefaultRename handles both single threaded and SMT rename. Its
  41  * width is specified by the parameters; each cycle it tries to rename
  42  * that many instructions. It holds onto the rename history of all
  43  * instructions with destination registers, storing the
  44  * arch. register, the new physical register, and the old physical
  45  * register, to allow for undoing of mappings if squashing happens, or
  46  * freeing up registers upon commit. Rename handles blocking if the
  47  * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
  48  * and does so by stalling on the instruction until the ROB is empty
  49  * and there are no instructions in flight to the ROB.
  50  */
  51 template<class Impl>
  52 class DefaultRename
  53 {
  54   public:
  55     // Typedefs from the Impl.
  56     typedef typename Impl::CPUPol CPUPol;
  57     typedef typename Impl::DynInstPtr DynInstPtr;
  58     typedef typename Impl::FullCPU FullCPU;
  59     typedef typename Impl::Params Params;
  60
  61     // Typedefs from the CPUPol
  62     typedef typename CPUPol::DecodeStruct DecodeStruct;
  63     typedef typename CPUPol::RenameStruct RenameStruct;
  64     typedef typename CPUPol::TimeStruct TimeStruct;
  65     typedef typename CPUPol::FreeList FreeList;
  66     typedef typename CPUPol::RenameMap RenameMap;
  67     // These are used only for initialization.
  68     typedef typename CPUPol::IEW IEW;
  69     typedef typename CPUPol::Commit Commit;
  70
  71     // Typedefs from the ISA.
  72     typedef TheISA::RegIndex RegIndex;
  73
  74     // A list is used to queue the instructions.  Barrier insts must
  75     // be added to the front of the list, which is the only reason for
  76     // using a list instead of a queue. (Most other stages use a
  77     // queue)
  78     typedef std::list<DynInstPtr> InstQueue;
  79
  80   public:
  81     /** Overall rename status. Used to determine if the CPU can
  82      * deschedule itself due to a lack of activity.
  83      */
  84     enum RenameStatus {
  85         Active,
  86         Inactive
  87     };
  88
  89     /** Individual thread status. */
  90     enum ThreadStatus {
  91         Running,
  92         Idle,
  93         StartSquash,
  94         Squashing,
  95         Blocked,
  96         Unblocking,
  97         SerializeStall
  98     };
  99
 100   private:
 101     /** Rename status. */
 102     RenameStatus _status;
 103
 104     /** Per-thread status. */
 105     ThreadStatus renameStatus[Impl::MaxThreads];
 106
 107   public:
 108     /** DefaultRename constructor. */
 109     DefaultRename(Params *params);
 110
 111     /** Returns the name of rename. */
 112     std::string name() const;
 113
 114     /** Registers statistics. */
 115     void regStats();
 116
 117     /** Sets CPU pointer. */
 118     void setCPU(FullCPU *cpu_ptr);
 119
 120     /** Sets the main backwards communication time buffer pointer. */
 121     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 122
 123     /** Sets pointer to time buffer used to communicate to the next stage. */
 124     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 125
 126     /** Sets pointer to time buffer coming from decode. */
 127     void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
 128
 129     /** Sets pointer to IEW stage. Used only for initialization. */
 130     void setIEWStage(IEW *iew_stage)
 131     { iew_ptr = iew_stage; }
 132
 133     /** Sets pointer to commit stage. Used only for initialization. */
 134     void setCommitStage(Commit *commit_stage)
 135     { commit_ptr = commit_stage; }
 136
 137   private:
 138     /** Pointer to IEW stage. Used only for initialization. */
 139     IEW *iew_ptr;
 140
 141     /** Pointer to commit stage. Used only for initialization. */
 142     Commit *commit_ptr;
 143
 144   public:
 145     /** Initializes variables for the stage. */
 146     void initStage();
 147
 148     /** Sets pointer to list of active threads. */
 149     void setActiveThreads(std::list<unsigned> *at_ptr);
 150
 151     /** Sets pointer to rename maps (per-thread structures). */
 152     void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
 153
 154     /** Sets pointer to the free list. */
 155     void setFreeList(FreeList *fl_ptr);
 156
 157     /** Sets pointer to the scoreboard. */
 158     void setScoreboard(Scoreboard *_scoreboard);
 159
 160     /** Switches out the rename stage. */
 161     void switchOut();
 162
 163     /** Completes the switch out. */
 164     void doSwitchOut();
 165
 166     /** Takes over from another CPU's thread. */
 167     void takeOverFrom();
 168
 169     /** Squashes all instructions in a thread. */
 170     void squash(unsigned tid);
 171
 172     /** Ticks rename, which processes all input signals and attempts to rename
 173      * as many instructions as possible.
 174      */
 175     void tick();
 176
 177     /** Debugging function used to dump history buffer of renamings. */
 178     void dumpHistory();
 179
 180   private:
 181     /** Determines what to do based on rename's current status.
 182      * @param status_change rename() sets this variable if there was a status
 183      * change (ie switching from blocking to unblocking).
 184      * @param tid Thread id to rename instructions from.
 185      */
 186     void rename(bool &status_change, unsigned tid);
 187
 188     /** Renames instructions for the given thread. Also handles serializing
 189      * instructions.
 190      */
 191     void renameInsts(unsigned tid);
 192
 193     /** Inserts unused instructions from a given thread into the skid buffer,
 194      * to be renamed once rename unblocks.
 195      */
 196     void skidInsert(unsigned tid);
 197
 198     /** Separates instructions from decode into individual lists of instructions
 199      * sorted by thread.
 200      */
 201     void sortInsts();
 202
 203     /** Returns if all of the skid buffers are empty. */
 204     bool skidsEmpty();
 205
 206     /** Updates overall rename status based on all of the threads' statuses. */
 207     void updateStatus();
 208
 209     /** Switches rename to blocking, and signals back that rename has become
 210      * blocked.
 211      * @return Returns true if there is a status change.
 212      */
 213     bool block(unsigned tid);
 214
 215     /** Switches rename to unblocking if the skid buffer is empty, and signals
 216      * back that rename has unblocked.
 217      * @return Returns true if there is a status change.
 218      */
 219     bool unblock(unsigned tid);
 220
 221     /** Executes actual squash, removing squashed instructions. */
 222     void doSquash(unsigned tid);
 223
 224     /** Removes a committed instruction's rename history. */
 225     void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
 226
 227     /** Renames the source registers of an instruction. */
 228     inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
 229
 230     /** Renames the destination registers of an instruction. */
 231     inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
 232
 233     /** Calculates the number of free ROB entries for a specific thread. */
 234     inline int calcFreeROBEntries(unsigned tid);
 235
 236     /** Calculates the number of free IQ entries for a specific thread. */
 237     inline int calcFreeIQEntries(unsigned tid);
 238
 239     /** Calculates the number of free LSQ entries for a specific thread. */
 240     inline int calcFreeLSQEntries(unsigned tid);
 241
 242     /** Returns the number of valid instructions coming from decode. */
 243     unsigned validInsts();
 244
 245     /** Reads signals telling rename to block/unblock. */
 246     void readStallSignals(unsigned tid);
 247
 248     /** Checks if any stages are telling rename to block. */
 249     bool checkStall(unsigned tid);
 250
 251     /** Gets the number of free entries for a specific thread. */
 252     void readFreeEntries(unsigned tid);
 253
 254     /** Checks the signals and updates the status. */
 255     bool checkSignalsAndUpdate(unsigned tid);
 256
 257     /** Either serializes on the next instruction available in the InstQueue,
 258      * or records that it must serialize on the next instruction to enter
 259      * rename.
 260      * @param inst_list The list of younger, unprocessed instructions for the
 261      * thread that has the serializeAfter instruction.
 262      * @param tid The thread id.
 263      */
 264     void serializeAfter(InstQueue &inst_list, unsigned tid);
 265
 266     /** Holds the information for each destination register rename. It holds
 267      * the instruction's sequence number, the arch register, the old physical
 268      * register for that arch. register, and the new physical register.
 269      */
 270     struct RenameHistory {
 271         RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
 272                       PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
 273             : instSeqNum(_instSeqNum), archReg(_archReg),
 274               newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
 275         {
 276         }
 277
 278         /** The sequence number of the instruction that renamed. */
 279         InstSeqNum instSeqNum;
 280         /** The architectural register index that was renamed. */
 281         RegIndex archReg;
 282         /** The new physical register that the arch. register is renamed to. */
 283         PhysRegIndex newPhysReg;
 284         /** The old physical register that the arch. register was renamed to. */
 285         PhysRegIndex prevPhysReg;
 286     };
 287
 288     /** A per-thread list of all destination register renames, used to either
 289      * undo rename mappings or free old physical registers.
 290      */
 291     std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
 292
 293     /** Pointer to CPU. */
 294     FullCPU *cpu;
 295
 296     /** Pointer to main time buffer used for backwards communication. */
 297     TimeBuffer<TimeStruct> *timeBuffer;
 298
 299     /** Wire to get IEW's output from backwards time buffer. */
 300     typename TimeBuffer<TimeStruct>::wire fromIEW;
 301
 302     /** Wire to get commit's output from backwards time buffer. */
 303     typename TimeBuffer<TimeStruct>::wire fromCommit;
 304
 305     /** Wire to write infromation heading to previous stages. */
 306     typename TimeBuffer<TimeStruct>::wire toDecode;
 307
 308     /** Rename instruction queue. */
 309     TimeBuffer<RenameStruct> *renameQueue;
 310
 311     /** Wire to write any information heading to IEW. */
 312     typename TimeBuffer<RenameStruct>::wire toIEW;
 313
 314     /** Decode instruction queue interface. */
 315     TimeBuffer<DecodeStruct> *decodeQueue;
 316
 317     /** Wire to get decode's output from decode queue. */
 318     typename TimeBuffer<DecodeStruct>::wire fromDecode;
 319
 320     /** Queue of all instructions coming from decode this cycle. */
 321     InstQueue insts[Impl::MaxThreads];
 322
 323     /** Skid buffer between rename and decode. */
 324     InstQueue skidBuffer[Impl::MaxThreads];
 325
 326     /** Rename map interface. */
 327     RenameMap *renameMap[Impl::MaxThreads];
 328
 329     /** Free list interface. */
 330     FreeList *freeList;
 331
 332     /** Pointer to the list of active threads. */
 333     std::list<unsigned> *activeThreads;
 334
 335     /** Pointer to the scoreboard. */
 336     Scoreboard *scoreboard;
 337
 338     /** Count of instructions in progress that have been sent off to the IQ
 339      * and ROB, but are not yet included in their occupancy counts.
 340      */
 341     int instsInProgress[Impl::MaxThreads];
 342
 343     /** Variable that tracks if decode has written to the time buffer this
 344      * cycle. Used to tell CPU if there is activity this cycle.
 345      */
 346     bool wroteToTimeBuffer;
 347
 348     /** Structures whose free entries impact the amount of instructions that
 349      * can be renamed.
 350      */
 351     struct FreeEntries {
 352         unsigned iqEntries;
 353         unsigned lsqEntries;
 354         unsigned robEntries;
 355     };
 356
 357     /** Per-thread tracking of the number of free entries of back-end
 358      * structures.
 359      */
 360     FreeEntries freeEntries[Impl::MaxThreads];
 361
 362     /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
 363      * partitioned between threads, so the ROB must tell rename when it is
 364      * empty.
 365      */
 366     bool emptyROB[Impl::MaxThreads];
 367
 368     /** Source of possible stalls. */
 369     struct Stalls {
 370         bool iew;
 371         bool commit;
 372     };
 373
 374     /** Tracks which stages are telling decode to stall. */
 375     Stalls stalls[Impl::MaxThreads];
 376
 377     /** The serialize instruction that rename has stalled on. */
 378     DynInstPtr serializeInst[Impl::MaxThreads];
 379
 380     /** Records if rename needs to serialize on the next instruction for any
 381      * thread.
 382      */
 383     bool serializeOnNextInst[Impl::MaxThreads];
 384
 385     /** Delay between iew and rename, in ticks. */
 386     int iewToRenameDelay;
 387
 388     /** Delay between decode and rename, in ticks. */
 389     int decodeToRenameDelay;
 390
 391     /** Delay between commit and rename, in ticks. */
 392     unsigned commitToRenameDelay;
 393
 394     /** Rename width, in instructions. */
 395     unsigned renameWidth;
 396
 397     /** Commit width, in instructions.  Used so rename knows how many
 398      *  instructions might have freed registers in the previous cycle.
 399      */
 400     unsigned commitWidth;
 401
 402     /** The index of the instruction in the time buffer to IEW that rename is
 403      * currently using.
 404      */
 405     unsigned toIEWIndex;
 406
 407     /** Whether or not rename needs to block this cycle. */
 408     bool blockThisCycle;
 409
 410     /** The number of threads active in rename. */
 411     unsigned numThreads;
 412
 413     /** The maximum skid buffer size. */
 414     unsigned skidBufferMax;
 415
 416     /** Enum to record the source of a structure full stall.  Can come from
 417      * either ROB, IQ, LSQ, and it is priortized in that order.
 418      */
 419     enum FullSource {
 420         ROB,
 421         IQ,
 422         LSQ,
 423         NONE
 424     };
 425
 426     /** Function used to increment the stat that corresponds to the source of
 427      * the stall.
 428      */
 429     inline void incrFullStat(const FullSource &source);
 430
 431     /** Stat for total number of cycles spent squashing. */
 432     Stats::Scalar<> renameSquashCycles;
 433     /** Stat for total number of cycles spent idle. */
 434     Stats::Scalar<> renameIdleCycles;
 435     /** Stat for total number of cycles spent blocking. */
 436     Stats::Scalar<> renameBlockCycles;
 437     /** Stat for total number of cycles spent stalling for a serializing inst. */
 438     Stats::Scalar<> renameSerializeStallCycles;
 439     /** Stat for total number of cycles spent running normally. */
 440     Stats::Scalar<> renameRunCycles;
 441     /** Stat for total number of cycles spent unblocking. */
 442     Stats::Scalar<> renameUnblockCycles;
 443     /** Stat for total number of renamed instructions. */
 444     Stats::Scalar<> renameRenamedInsts;
 445     /** Stat for total number of squashed instructions that rename discards. */
 446     Stats::Scalar<> renameSquashedInsts;
 447     /** Stat for total number of times that the ROB starts a stall in rename. */
 448     Stats::Scalar<> renameROBFullEvents;
 449     /** Stat for total number of times that the IQ starts a stall in rename. */
 450     Stats::Scalar<> renameIQFullEvents;
 451     /** Stat for total number of times that the LSQ starts a stall in rename. */
 452     Stats::Scalar<> renameLSQFullEvents;
 453     /** Stat for total number of times that rename runs out of free registers
 454      * to use to rename. */
 455     Stats::Scalar<> renameFullRegistersEvents;
 456     /** Stat for total number of renamed destination registers. */
 457     Stats::Scalar<> renameRenamedOperands;
 458     /** Stat for total number of source register rename lookups. */
 459     Stats::Scalar<> renameRenameLookups;
 460     /** Stat for total number of committed renaming mappings. */
 461     Stats::Scalar<> renameCommittedMaps;
 462     /** Stat for total number of mappings that were undone due to a squash. */
 463     Stats::Scalar<> renameUndoneMaps;
 464     /** Number of serialize instructions handled. */
 465     Stats::Scalar<> renamedSerializing;
 466     /** Number of instructions marked as temporarily serializing. */
 467     Stats::Scalar<> renamedTempSerializing;
 468     /** Number of instructions inserted into skid buffers. */
 469     Stats::Scalar<> renameSkidInsts;
 470 };
 471
 472 #endif // __CPU_O3_RENAME_HH__