src/cpu/o3/rename_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include <list>
  33
  34 #include "arch/isa_traits.hh"
  35 #include "arch/regfile.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/o3/rename.hh"
  38
  39 template <class Impl>
  40 DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
  41     : cpu(_cpu),
  42       iewToRenameDelay(params->iewToRenameDelay),
  43       decodeToRenameDelay(params->decodeToRenameDelay),
  44       commitToRenameDelay(params->commitToRenameDelay),
  45       renameWidth(params->renameWidth),
  46       commitWidth(params->commitWidth),
  47       resumeSerialize(false),
  48       resumeUnblocking(false),
  49       numThreads(params->numberOfThreads),
  50       maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
  51 {
  52     _status = Inactive;
  53
  54     for (int i=0; i< numThreads; i++) {
  55         renameStatus[i] = Idle;
  56
  57         freeEntries[i].iqEntries = 0;
  58         freeEntries[i].lsqEntries = 0;
  59         freeEntries[i].robEntries = 0;
  60
  61         stalls[i].iew = false;
  62         stalls[i].commit = false;
  63         serializeInst[i] = NULL;
  64
  65         instsInProgress[i] = 0;
  66
  67         emptyROB[i] = true;
  68
  69         serializeOnNextInst[i] = false;
  70     }
  71
  72     // @todo: Make into a parameter.
  73     skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
  74 }
  75
  76 template <class Impl>
  77 std::string
  78 DefaultRename<Impl>::name() const
  79 {
  80     return cpu->name() + ".rename";
  81 }
  82
  83 template <class Impl>
  84 void
  85 DefaultRename<Impl>::regStats()
  86 {
  87     renameSquashCycles
  88         .name(name() + ".RENAME:SquashCycles")
  89         .desc("Number of cycles rename is squashing")
  90         .prereq(renameSquashCycles);
  91     renameIdleCycles
  92         .name(name() + ".RENAME:IdleCycles")
  93         .desc("Number of cycles rename is idle")
  94         .prereq(renameIdleCycles);
  95     renameBlockCycles
  96         .name(name() + ".RENAME:BlockCycles")
  97         .desc("Number of cycles rename is blocking")
  98         .prereq(renameBlockCycles);
  99     renameSerializeStallCycles
 100         .name(name() + ".RENAME:serializeStallCycles")
 101         .desc("count of cycles rename stalled for serializing inst")
 102         .flags(Stats::total);
 103     renameRunCycles
 104         .name(name() + ".RENAME:RunCycles")
 105         .desc("Number of cycles rename is running")
 106         .prereq(renameIdleCycles);
 107     renameUnblockCycles
 108         .name(name() + ".RENAME:UnblockCycles")
 109         .desc("Number of cycles rename is unblocking")
 110         .prereq(renameUnblockCycles);
 111     renameRenamedInsts
 112         .name(name() + ".RENAME:RenamedInsts")
 113         .desc("Number of instructions processed by rename")
 114         .prereq(renameRenamedInsts);
 115     renameSquashedInsts
 116         .name(name() + ".RENAME:SquashedInsts")
 117         .desc("Number of squashed instructions processed by rename")
 118         .prereq(renameSquashedInsts);
 119     renameROBFullEvents
 120         .name(name() + ".RENAME:ROBFullEvents")
 121         .desc("Number of times rename has blocked due to ROB full")
 122         .prereq(renameROBFullEvents);
 123     renameIQFullEvents
 124         .name(name() + ".RENAME:IQFullEvents")
 125         .desc("Number of times rename has blocked due to IQ full")
 126         .prereq(renameIQFullEvents);
 127     renameLSQFullEvents
 128         .name(name() + ".RENAME:LSQFullEvents")
 129         .desc("Number of times rename has blocked due to LSQ full")
 130         .prereq(renameLSQFullEvents);
 131     renameFullRegistersEvents
 132         .name(name() + ".RENAME:FullRegisterEvents")
 133         .desc("Number of times there has been no free registers")
 134         .prereq(renameFullRegistersEvents);
 135     renameRenamedOperands
 136         .name(name() + ".RENAME:RenamedOperands")
 137         .desc("Number of destination operands rename has renamed")
 138         .prereq(renameRenamedOperands);
 139     renameRenameLookups
 140         .name(name() + ".RENAME:RenameLookups")
 141         .desc("Number of register rename lookups that rename has made")
 142         .prereq(renameRenameLookups);
 143     renameCommittedMaps
 144         .name(name() + ".RENAME:CommittedMaps")
 145         .desc("Number of HB maps that are committed")
 146         .prereq(renameCommittedMaps);
 147     renameUndoneMaps
 148         .name(name() + ".RENAME:UndoneMaps")
 149         .desc("Number of HB maps that are undone due to squashing")
 150         .prereq(renameUndoneMaps);
 151     renamedSerializing
 152         .name(name() + ".RENAME:serializingInsts")
 153         .desc("count of serializing insts renamed")
 154         .flags(Stats::total)
 155         ;
 156     renamedTempSerializing
 157         .name(name() + ".RENAME:tempSerializingInsts")
 158         .desc("count of temporary serializing insts renamed")
 159         .flags(Stats::total)
 160         ;
 161     renameSkidInsts
 162         .name(name() + ".RENAME:skidInsts")
 163         .desc("count of insts added to the skid buffer")
 164         .flags(Stats::total)
 165         ;
 166 }
 167
 168 template <class Impl>
 169 void
 170 DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 171 {
 172     timeBuffer = tb_ptr;
 173
 174     // Setup wire to read information from time buffer, from IEW stage.
 175     fromIEW = timeBuffer->getWire(-iewToRenameDelay);
 176
 177     // Setup wire to read infromation from time buffer, from commit stage.
 178     fromCommit = timeBuffer->getWire(-commitToRenameDelay);
 179
 180     // Setup wire to write information to previous stages.
 181     toDecode = timeBuffer->getWire(0);
 182 }
 183
 184 template <class Impl>
 185 void
 186 DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 187 {
 188     renameQueue = rq_ptr;
 189
 190     // Setup wire to write information to future stages.
 191     toIEW = renameQueue->getWire(0);
 192 }
 193
 194 template <class Impl>
 195 void
 196 DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
 197 {
 198     decodeQueue = dq_ptr;
 199
 200     // Setup wire to get information from decode.
 201     fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
 202 }
 203
 204 template <class Impl>
 205 void
 206 DefaultRename<Impl>::initStage()
 207 {
 208     // Grab the number of free entries directly from the stages.
 209     for (int tid=0; tid < numThreads; tid++) {
 210         freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
 211         freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
 212         freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
 213         emptyROB[tid] = true;
 214     }
 215 }
 216
 217 template<class Impl>
 218 void
 219 DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 220 {
 221     activeThreads = at_ptr;
 222 }
 223
 224
 225 template <class Impl>
 226 void
 227 DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
 228 {
 229     for (int i=0; i<numThreads; i++) {
 230         renameMap[i] = &rm_ptr[i];
 231     }
 232 }
 233
 234 template <class Impl>
 235 void
 236 DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
 237 {
 238     freeList = fl_ptr;
 239 }
 240
 241 template<class Impl>
 242 void
 243 DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
 244 {
 245     scoreboard = _scoreboard;
 246 }
 247
 248 template <class Impl>
 249 bool
 250 DefaultRename<Impl>::drain()
 251 {
 252     // Rename is ready to switch out at any time.
 253     cpu->signalDrained();
 254     return true;
 255 }
 256
 257 template <class Impl>
 258 void
 259 DefaultRename<Impl>::switchOut()
 260 {
 261     // Clear any state, fix up the rename map.
 262     for (int i = 0; i < numThreads; i++) {
 263         typename std::list<RenameHistory>::iterator hb_it =
 264             historyBuffer[i].begin();
 265
 266         while (!historyBuffer[i].empty()) {
 267             assert(hb_it != historyBuffer[i].end());
 268
 269             DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
 270                     "number %i.\n", i, (*hb_it).instSeqNum);
 271
 272             // Tell the rename map to set the architected register to the
 273             // previous physical register that it was renamed to.
 274             renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
 275
 276             // Put the renamed physical register back on the free list.
 277             freeList->addReg(hb_it->newPhysReg);
 278
 279             // Be sure to mark its register as ready if it's a misc register.
 280             if (hb_it->newPhysReg >= maxPhysicalRegs) {
 281                 scoreboard->setReg(hb_it->newPhysReg);
 282             }
 283
 284             historyBuffer[i].erase(hb_it++);
 285         }
 286         insts[i].clear();
 287         skidBuffer[i].clear();
 288     }
 289 }
 290
 291 template <class Impl>
 292 void
 293 DefaultRename<Impl>::takeOverFrom()
 294 {
 295     _status = Inactive;
 296     initStage();
 297
 298     // Reset all state prior to taking over from the other CPU.
 299     for (int i=0; i< numThreads; i++) {
 300         renameStatus[i] = Idle;
 301
 302         stalls[i].iew = false;
 303         stalls[i].commit = false;
 304         serializeInst[i] = NULL;
 305
 306         instsInProgress[i] = 0;
 307
 308         emptyROB[i] = true;
 309
 310         serializeOnNextInst[i] = false;
 311     }
 312 }
 313
 314 template <class Impl>
 315 void
 316 DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
 317 {
 318     DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
 319
 320     // Clear the stall signal if rename was blocked or unblocking before.
 321     // If it still needs to block, the blocking should happen the next
 322     // cycle and there should be space to hold everything due to the squash.
 323     if (renameStatus[tid] == Blocked ||
 324         renameStatus[tid] == Unblocking) {
 325         toDecode->renameUnblock[tid] = 1;
 326
 327         resumeSerialize = false;
 328         serializeInst[tid] = NULL;
 329     } else if (renameStatus[tid] == SerializeStall) {
 330         if (serializeInst[tid]->seqNum <= squash_seq_num) {
 331             DPRINTF(Rename, "Rename will resume serializing after squash\n");
 332             resumeSerialize = true;
 333             assert(serializeInst[tid]);
 334         } else {
 335             resumeSerialize = false;
 336             toDecode->renameUnblock[tid] = 1;
 337
 338             serializeInst[tid] = NULL;
 339         }
 340     }
 341
 342     // Set the status to Squashing.
 343     renameStatus[tid] = Squashing;
 344
 345     // Squash any instructions from decode.
 346     unsigned squashCount = 0;
 347
 348     for (int i=0; i<fromDecode->size; i++) {
 349         if (fromDecode->insts[i]->threadNumber == tid &&
 350             fromDecode->insts[i]->seqNum > squash_seq_num) {
 351             fromDecode->insts[i]->setSquashed();
 352             wroteToTimeBuffer = true;
 353             squashCount++;
 354         }
 355
 356     }
 357
 358     // Clear the instruction list and skid buffer in case they have any
 359     // insts in them. Since we support multiple ISAs, we cant just:
 360     // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
 361     // a possible delay slot inst for different architectures
 362     // insts[tid].clear();
 363 #if ISA_HAS_DELAY_SLOT
 364     DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
 365             "[sn:%i].\n",tid, squash_seq_num);
 366     ListIt ilist_it = insts[tid].begin();
 367     while (ilist_it != insts[tid].end()) {
 368         if ((*ilist_it)->seqNum > squash_seq_num) {
 369             (*ilist_it)->setSquashed();
 370             DPRINTF(Rename, "Squashing incoming decode instruction, "
 371                     "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
 372         }
 373         ilist_it++;
 374     }
 375 #else
 376     insts[tid].clear();
 377 #endif
 378
 379     // Clear the skid buffer in case it has any data in it.
 380     // See comments above.
 381     //     skidBuffer[tid].clear();
 382 #if ISA_HAS_DELAY_SLOT
 383     DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
 384             "until [sn:%i].\n", tid, squash_seq_num);
 385     ListIt slist_it = skidBuffer[tid].begin();
 386     while (slist_it != skidBuffer[tid].end()) {
 387         if ((*slist_it)->seqNum > squash_seq_num) {
 388             (*slist_it)->setSquashed();
 389             DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
 390                     "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
 391         }
 392         slist_it++;
 393     }
 394     resumeUnblocking = (skidBuffer[tid].size() != 0);
 395     DPRINTF(Rename, "Resume unblocking set to %s\n",
 396             resumeUnblocking ? "true" : "false");
 397 #else
 398     skidBuffer[tid].clear();
 399 #endif
 400     doSquash(squash_seq_num, tid);
 401 }
 402
 403 template <class Impl>
 404 void
 405 DefaultRename<Impl>::tick()
 406 {
 407     wroteToTimeBuffer = false;
 408
 409     blockThisCycle = false;
 410
 411     bool status_change = false;
 412
 413     toIEWIndex = 0;
 414
 415     sortInsts();
 416
 417     std::list<unsigned>::iterator threads = activeThreads->begin();
 418     std::list<unsigned>::iterator end = activeThreads->end();
 419
 420     // Check stall and squash signals.
 421     while (threads != end) {
 422         unsigned tid = *threads++;
 423
 424         DPRINTF(Rename, "Processing [tid:%i]\n", tid);
 425
 426         status_change = checkSignalsAndUpdate(tid) || status_change;
 427
 428         rename(status_change, tid);
 429     }
 430
 431     if (status_change) {
 432         updateStatus();
 433     }
 434
 435     if (wroteToTimeBuffer) {
 436         DPRINTF(Activity, "Activity this cycle.\n");
 437         cpu->activityThisCycle();
 438     }
 439
 440     threads = activeThreads->begin();
 441
 442     while (threads != end) {
 443         unsigned tid = *threads++;
 444
 445         // If we committed this cycle then doneSeqNum will be > 0
 446         if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
 447             !fromCommit->commitInfo[tid].squash &&
 448             renameStatus[tid] != Squashing) {
 449
 450             removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
 451                                   tid);
 452         }
 453     }
 454
 455     // @todo: make into updateProgress function
 456     for (int tid=0; tid < numThreads; tid++) {
 457         instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
 458
 459         assert(instsInProgress[tid] >=0);
 460     }
 461
 462 }
 463
 464 template<class Impl>
 465 void
 466 DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
 467 {
 468     // If status is Running or idle,
 469     //     call renameInsts()
 470     // If status is Unblocking,
 471     //     buffer any instructions coming from decode
 472     //     continue trying to empty skid buffer
 473     //     check if stall conditions have passed
 474
 475     if (renameStatus[tid] == Blocked) {
 476         ++renameBlockCycles;
 477     } else if (renameStatus[tid] == Squashing) {
 478         ++renameSquashCycles;
 479     } else if (renameStatus[tid] == SerializeStall) {
 480         ++renameSerializeStallCycles;
 481         // If we are currently in SerializeStall and resumeSerialize
 482         // was set, then that means that we are resuming serializing
 483         // this cycle.  Tell the previous stages to block.
 484         if (resumeSerialize) {
 485             resumeSerialize = false;
 486             block(tid);
 487             toDecode->renameUnblock[tid] = false;
 488         }
 489     } else if (renameStatus[tid] == Unblocking) {
 490         if (resumeUnblocking) {
 491             block(tid);
 492             resumeUnblocking = false;
 493             toDecode->renameUnblock[tid] = false;
 494         }
 495     }
 496
 497     if (renameStatus[tid] == Running ||
 498         renameStatus[tid] == Idle) {
 499         DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
 500                 "stage.\n", tid);
 501
 502         renameInsts(tid);
 503     } else if (renameStatus[tid] == Unblocking) {
 504         renameInsts(tid);
 505
 506         if (validInsts()) {
 507             // Add the current inputs to the skid buffer so they can be
 508             // reprocessed when this stage unblocks.
 509             skidInsert(tid);
 510         }
 511
 512         // If we switched over to blocking, then there's a potential for
 513         // an overall status change.
 514         status_change = unblock(tid) || status_change || blockThisCycle;
 515     }
 516 }
 517
 518 template <class Impl>
 519 void
 520 DefaultRename<Impl>::renameInsts(unsigned tid)
 521 {
 522     // Instructions can be either in the skid buffer or the queue of
 523     // instructions coming from decode, depending on the status.
 524     int insts_available = renameStatus[tid] == Unblocking ?
 525         skidBuffer[tid].size() : insts[tid].size();
 526
 527     // Check the decode queue to see if instructions are available.
 528     // If there are no available instructions to rename, then do nothing.
 529     if (insts_available == 0) {
 530         DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
 531                 tid);
 532         // Should I change status to idle?
 533         ++renameIdleCycles;
 534         return;
 535     } else if (renameStatus[tid] == Unblocking) {
 536         ++renameUnblockCycles;
 537     } else if (renameStatus[tid] == Running) {
 538         ++renameRunCycles;
 539     }
 540
 541     DynInstPtr inst;
 542
 543     // Will have to do a different calculation for the number of free
 544     // entries.
 545     int free_rob_entries = calcFreeROBEntries(tid);
 546     int free_iq_entries  = calcFreeIQEntries(tid);
 547     int free_lsq_entries = calcFreeLSQEntries(tid);
 548     int min_free_entries = free_rob_entries;
 549
 550     FullSource source = ROB;
 551
 552     if (free_iq_entries < min_free_entries) {
 553         min_free_entries = free_iq_entries;
 554         source = IQ;
 555     }
 556
 557     if (free_lsq_entries < min_free_entries) {
 558         min_free_entries = free_lsq_entries;
 559         source = LSQ;
 560     }
 561
 562     // Check if there's any space left.
 563     if (min_free_entries <= 0) {
 564         DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
 565                 "entries.\n"
 566                 "ROB has %i free entries.\n"
 567                 "IQ has %i free entries.\n"
 568                 "LSQ has %i free entries.\n",
 569                 tid,
 570                 free_rob_entries,
 571                 free_iq_entries,
 572                 free_lsq_entries);
 573
 574         blockThisCycle = true;
 575
 576         block(tid);
 577
 578         incrFullStat(source);
 579
 580         return;
 581     } else if (min_free_entries < insts_available) {
 582         DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
 583                 "%i insts available, but only %i insts can be "
 584                 "renamed due to ROB/IQ/LSQ limits.\n",
 585                 tid, insts_available, min_free_entries);
 586
 587         insts_available = min_free_entries;
 588
 589         blockThisCycle = true;
 590
 591         incrFullStat(source);
 592     }
 593
 594     InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
 595         skidBuffer[tid] : insts[tid];
 596
 597     DPRINTF(Rename, "[tid:%u]: %i available instructions to "
 598             "send iew.\n", tid, insts_available);
 599
 600     DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
 601             "dispatched to IQ last cycle.\n",
 602             tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
 603
 604     // Handle serializing the next instruction if necessary.
 605     if (serializeOnNextInst[tid]) {
 606         if (emptyROB[tid] && instsInProgress[tid] == 0) {
 607             // ROB already empty; no need to serialize.
 608             serializeOnNextInst[tid] = false;
 609         } else if (!insts_to_rename.empty()) {
 610             insts_to_rename.front()->setSerializeBefore();
 611         }
 612     }
 613
 614     int renamed_insts = 0;
 615
 616     while (insts_available > 0 &&  toIEWIndex < renameWidth) {
 617         DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
 618
 619         assert(!insts_to_rename.empty());
 620
 621         inst = insts_to_rename.front();
 622
 623         insts_to_rename.pop_front();
 624
 625         if (renameStatus[tid] == Unblocking) {
 626             DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
 627                     "skidBuffer\n",
 628                     tid, inst->seqNum, inst->readPC());
 629         }
 630
 631         if (inst->isSquashed()) {
 632             DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
 633                     "squashed, skipping.\n",
 634                     tid, inst->seqNum, inst->readPC());
 635
 636             ++renameSquashedInsts;
 637
 638             // Decrement how many instructions are available.
 639             --insts_available;
 640
 641             continue;
 642         }
 643
 644         DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
 645                 "PC %#x.\n",
 646                 tid, inst->seqNum, inst->readPC());
 647
 648         // Handle serializeAfter/serializeBefore instructions.
 649         // serializeAfter marks the next instruction as serializeBefore.
 650         // serializeBefore makes the instruction wait in rename until the ROB
 651         // is empty.
 652
 653         // In this model, IPR accesses are serialize before
 654         // instructions, and store conditionals are serialize after
 655         // instructions.  This is mainly due to lack of support for
 656         // out-of-order operations of either of those classes of
 657         // instructions.
 658         if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
 659             !inst->isSerializeHandled()) {
 660             DPRINTF(Rename, "Serialize before instruction encountered.\n");
 661
 662             if (!inst->isTempSerializeBefore()) {
 663                 renamedSerializing++;
 664                 inst->setSerializeHandled();
 665             } else {
 666                 renamedTempSerializing++;
 667             }
 668
 669             // Change status over to SerializeStall so that other stages know
 670             // what this is blocked on.
 671             renameStatus[tid] = SerializeStall;
 672
 673             serializeInst[tid] = inst;
 674
 675             blockThisCycle = true;
 676
 677             break;
 678         } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
 679                    !inst->isSerializeHandled()) {
 680             DPRINTF(Rename, "Serialize after instruction encountered.\n");
 681
 682             renamedSerializing++;
 683
 684             inst->setSerializeHandled();
 685
 686             serializeAfter(insts_to_rename, tid);
 687         }
 688
 689         // Check here to make sure there are enough destination registers
 690         // to rename to.  Otherwise block.
 691         if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
 692             DPRINTF(Rename, "Blocking due to lack of free "
 693                     "physical registers to rename to.\n");
 694             blockThisCycle = true;
 695             insts_to_rename.push_front(inst);
 696             ++renameFullRegistersEvents;
 697
 698             break;
 699         }
 700
 701         renameSrcRegs(inst, inst->threadNumber);
 702
 703         renameDestRegs(inst, inst->threadNumber);
 704
 705         ++renamed_insts;
 706
 707         // Put instruction in rename queue.
 708         toIEW->insts[toIEWIndex] = inst;
 709         ++(toIEW->size);
 710
 711         // Increment which instruction we're on.
 712         ++toIEWIndex;
 713
 714         // Decrement how many instructions are available.
 715         --insts_available;
 716     }
 717
 718     instsInProgress[tid] += renamed_insts;
 719     renameRenamedInsts += renamed_insts;
 720
 721     // If we wrote to the time buffer, record this.
 722     if (toIEWIndex) {
 723         wroteToTimeBuffer = true;
 724     }
 725
 726     // Check if there's any instructions left that haven't yet been renamed.
 727     // If so then block.
 728     if (insts_available) {
 729         blockThisCycle = true;
 730     }
 731
 732     if (blockThisCycle) {
 733         block(tid);
 734         toDecode->renameUnblock[tid] = false;
 735     }
 736 }
 737
 738 template<class Impl>
 739 void
 740 DefaultRename<Impl>::skidInsert(unsigned tid)
 741 {
 742     DynInstPtr inst = NULL;
 743
 744     while (!insts[tid].empty()) {
 745         inst = insts[tid].front();
 746
 747         insts[tid].pop_front();
 748
 749         assert(tid == inst->threadNumber);
 750
 751         DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
 752                 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
 753
 754         ++renameSkidInsts;
 755
 756         skidBuffer[tid].push_back(inst);
 757     }
 758
 759     if (skidBuffer[tid].size() > skidBufferMax)
 760     {
 761         typename InstQueue::iterator it;
 762         warn("Skidbuffer contents:\n");
 763         for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
 764         {
 765             warn("[tid:%u]: %s [sn:%i].\n", tid,
 766                     (*it)->staticInst->disassemble(inst->readPC()),
 767                     (*it)->seqNum);
 768         }
 769         panic("Skidbuffer Exceeded Max Size");
 770     }
 771 }
 772
 773 template <class Impl>
 774 void
 775 DefaultRename<Impl>::sortInsts()
 776 {
 777     int insts_from_decode = fromDecode->size;
 778 #ifdef DEBUG
 779 #if !ISA_HAS_DELAY_SLOT
 780     for (int i=0; i < numThreads; i++)
 781         assert(insts[i].empty());
 782 #endif
 783 #endif
 784     for (int i = 0; i < insts_from_decode; ++i) {
 785         DynInstPtr inst = fromDecode->insts[i];
 786         insts[inst->threadNumber].push_back(inst);
 787     }
 788 }
 789
 790 template<class Impl>
 791 bool
 792 DefaultRename<Impl>::skidsEmpty()
 793 {
 794     std::list<unsigned>::iterator threads = activeThreads->begin();
 795     std::list<unsigned>::iterator end = activeThreads->end();
 796
 797     while (threads != end) {
 798         unsigned tid = *threads++;
 799
 800         if (!skidBuffer[tid].empty())
 801             return false;
 802     }
 803
 804     return true;
 805 }
 806
 807 template<class Impl>
 808 void
 809 DefaultRename<Impl>::updateStatus()
 810 {
 811     bool any_unblocking = false;
 812
 813     std::list<unsigned>::iterator threads = activeThreads->begin();
 814     std::list<unsigned>::iterator end = activeThreads->end();
 815
 816     while (threads != end) {
 817         unsigned tid = *threads++;
 818
 819         if (renameStatus[tid] == Unblocking) {
 820             any_unblocking = true;
 821             break;
 822         }
 823     }
 824
 825     // Rename will have activity if it's unblocking.
 826     if (any_unblocking) {
 827         if (_status == Inactive) {
 828             _status = Active;
 829
 830             DPRINTF(Activity, "Activating stage.\n");
 831
 832             cpu->activateStage(O3CPU::RenameIdx);
 833         }
 834     } else {
 835         // If it's not unblocking, then rename will not have any internal
 836         // activity.  Switch it to inactive.
 837         if (_status == Active) {
 838             _status = Inactive;
 839             DPRINTF(Activity, "Deactivating stage.\n");
 840
 841             cpu->deactivateStage(O3CPU::RenameIdx);
 842         }
 843     }
 844 }
 845
 846 template <class Impl>
 847 bool
 848 DefaultRename<Impl>::block(unsigned tid)
 849 {
 850     DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
 851
 852     // Add the current inputs onto the skid buffer, so they can be
 853     // reprocessed when this stage unblocks.
 854     skidInsert(tid);
 855
 856     // Only signal backwards to block if the previous stages do not think
 857     // rename is already blocked.
 858     if (renameStatus[tid] != Blocked) {
 859         // If resumeUnblocking is set, we unblocked during the squash,
 860         // but now we're have unblocking status. We need to tell earlier
 861         // stages to block.
 862         if (resumeUnblocking || renameStatus[tid] != Unblocking) {
 863             toDecode->renameBlock[tid] = true;
 864             toDecode->renameUnblock[tid] = false;
 865             wroteToTimeBuffer = true;
 866         }
 867
 868         // Rename can not go from SerializeStall to Blocked, otherwise
 869         // it would not know to complete the serialize stall.
 870         if (renameStatus[tid] != SerializeStall) {
 871             // Set status to Blocked.
 872             renameStatus[tid] = Blocked;
 873             return true;
 874         }
 875     }
 876
 877     return false;
 878 }
 879
 880 template <class Impl>
 881 bool
 882 DefaultRename<Impl>::unblock(unsigned tid)
 883 {
 884     DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
 885
 886     // Rename is done unblocking if the skid buffer is empty.
 887     if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
 888
 889         DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
 890
 891         toDecode->renameUnblock[tid] = true;
 892         wroteToTimeBuffer = true;
 893
 894         renameStatus[tid] = Running;
 895         return true;
 896     }
 897
 898     return false;
 899 }
 900
 901 template <class Impl>
 902 void
 903 DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
 904 {
 905     typename std::list<RenameHistory>::iterator hb_it =
 906         historyBuffer[tid].begin();
 907
 908     // After a syscall squashes everything, the history buffer may be empty
 909     // but the ROB may still be squashing instructions.
 910     if (historyBuffer[tid].empty()) {
 911         return;
 912     }
 913
 914     // Go through the most recent instructions, undoing the mappings
 915     // they did and freeing up the registers.
 916     while (!historyBuffer[tid].empty() &&
 917            (*hb_it).instSeqNum > squashed_seq_num) {
 918         assert(hb_it != historyBuffer[tid].end());
 919
 920         DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
 921                 "number %i.\n", tid, (*hb_it).instSeqNum);
 922
 923         // Tell the rename map to set the architected register to the
 924         // previous physical register that it was renamed to.
 925         renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
 926
 927         // Put the renamed physical register back on the free list.
 928         freeList->addReg(hb_it->newPhysReg);
 929
 930         // Be sure to mark its register as ready if it's a misc register.
 931         if (hb_it->newPhysReg >= maxPhysicalRegs) {
 932             scoreboard->setReg(hb_it->newPhysReg);
 933         }
 934
 935         historyBuffer[tid].erase(hb_it++);
 936
 937         ++renameUndoneMaps;
 938     }
 939 }
 940
 941 template<class Impl>
 942 void
 943 DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
 944 {
 945     DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
 946             "history buffer %u (size=%i), until [sn:%lli].\n",
 947             tid, tid, historyBuffer[tid].size(), inst_seq_num);
 948
 949     typename std::list<RenameHistory>::iterator hb_it =
 950         historyBuffer[tid].end();
 951
 952     --hb_it;
 953
 954     if (historyBuffer[tid].empty()) {
 955         DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
 956         return;
 957     } else if (hb_it->instSeqNum > inst_seq_num) {
 958         DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
 959                 "that a syscall happened recently.\n", tid);
 960         return;
 961     }
 962
 963     // Commit all the renames up until (and including) the committed sequence
 964     // number. Some or even all of the committed instructions may not have
 965     // rename histories if they did not have destination registers that were
 966     // renamed.
 967     while (!historyBuffer[tid].empty() &&
 968            hb_it != historyBuffer[tid].end() &&
 969            (*hb_it).instSeqNum <= inst_seq_num) {
 970
 971         DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
 972                 "[sn:%lli].\n",
 973                 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
 974
 975         freeList->addReg((*hb_it).prevPhysReg);
 976         ++renameCommittedMaps;
 977
 978         historyBuffer[tid].erase(hb_it--);
 979     }
 980 }
 981
 982 template <class Impl>
 983 inline void
 984 DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
 985 {
 986     assert(renameMap[tid] != 0);
 987
 988     unsigned num_src_regs = inst->numSrcRegs();
 989
 990     // Get the architectual register numbers from the source and
 991     // destination operands, and redirect them to the right register.
 992     // Will need to mark dependencies though.
 993     for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
 994         RegIndex src_reg = inst->srcRegIdx(src_idx);
 995         RegIndex flat_src_reg = src_reg;
 996         if (src_reg < TheISA::FP_Base_DepTag) {
 997             flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
 998             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
 999         } else {
1000             // Floating point and Miscellaneous registers need their indexes
1001             // adjusted to account for the expanded number of flattened int regs.
1002             flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1003         }
1004
1005         inst->flattenSrcReg(src_idx, flat_src_reg);
1006
1007         // Look up the source registers to get the phys. register they've
1008         // been renamed to, and set the sources to those registers.
1009         PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1010
1011         DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1012                 "physical reg %i.\n", tid, (int)flat_src_reg,
1013                 (int)renamed_reg);
1014
1015         inst->renameSrcReg(src_idx, renamed_reg);
1016
1017         // See if the register is ready or not.
1018         if (scoreboard->getReg(renamed_reg) == true) {
1019             DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
1020
1021             inst->markSrcRegReady(src_idx);
1022         }
1023
1024         ++renameRenameLookups;
1025     }
1026 }
1027
1028 template <class Impl>
1029 inline void
1030 DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
1031 {
1032     typename RenameMap::RenameInfo rename_result;
1033
1034     unsigned num_dest_regs = inst->numDestRegs();
1035
1036     // Rename the destination registers.
1037     for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1038         RegIndex dest_reg = inst->destRegIdx(dest_idx);
1039         RegIndex flat_dest_reg = dest_reg;
1040         if (dest_reg < TheISA::FP_Base_DepTag) {
1041             // Integer registers are flattened.
1042             flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1043             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1044         } else {
1045             // Floating point and Miscellaneous registers need their indexes
1046             // adjusted to account for the expanded number of flattened int regs.
1047             flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1048         }
1049
1050         inst->flattenDestReg(dest_idx, flat_dest_reg);
1051
1052         // Get the physical register that the destination will be
1053         // renamed to.
1054         rename_result = renameMap[tid]->rename(flat_dest_reg);
1055
1056         //Mark Scoreboard entry as not ready
1057         scoreboard->unsetReg(rename_result.first);
1058
1059         DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1060                 "reg %i.\n", tid, (int)flat_dest_reg,
1061                 (int)rename_result.first);
1062
1063         // Record the rename information so that a history can be kept.
1064         RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1065                                rename_result.first,
1066                                rename_result.second);
1067
1068         historyBuffer[tid].push_front(hb_entry);
1069
1070         DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1071                 "(size=%i), [sn:%lli].\n",tid,
1072                 historyBuffer[tid].size(),
1073                 (*historyBuffer[tid].begin()).instSeqNum);
1074
1075         // Tell the instruction to rename the appropriate destination
1076         // register (dest_idx) to the new physical register
1077         // (rename_result.first), and record the previous physical
1078         // register that the same logical register was renamed to
1079         // (rename_result.second).
1080         inst->renameDestReg(dest_idx,
1081                             rename_result.first,
1082                             rename_result.second);
1083
1084         ++renameRenamedOperands;
1085     }
1086 }
1087
1088 template <class Impl>
1089 inline int
1090 DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1091 {
1092     int num_free = freeEntries[tid].robEntries -
1093                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1094
1095     //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1096
1097     return num_free;
1098 }
1099
1100 template <class Impl>
1101 inline int
1102 DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1103 {
1104     int num_free = freeEntries[tid].iqEntries -
1105                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1106
1107     //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1108
1109     return num_free;
1110 }
1111
1112 template <class Impl>
1113 inline int
1114 DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1115 {
1116     int num_free = freeEntries[tid].lsqEntries -
1117                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1118
1119     //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1120
1121     return num_free;
1122 }
1123
1124 template <class Impl>
1125 unsigned
1126 DefaultRename<Impl>::validInsts()
1127 {
1128     unsigned inst_count = 0;
1129
1130     for (int i=0; i<fromDecode->size; i++) {
1131         if (!fromDecode->insts[i]->isSquashed())
1132             inst_count++;
1133     }
1134
1135     return inst_count;
1136 }
1137
1138 template <class Impl>
1139 void
1140 DefaultRename<Impl>::readStallSignals(unsigned tid)
1141 {
1142     if (fromIEW->iewBlock[tid]) {
1143         stalls[tid].iew = true;
1144     }
1145
1146     if (fromIEW->iewUnblock[tid]) {
1147         assert(stalls[tid].iew);
1148         stalls[tid].iew = false;
1149     }
1150
1151     if (fromCommit->commitBlock[tid]) {
1152         stalls[tid].commit = true;
1153     }
1154
1155     if (fromCommit->commitUnblock[tid]) {
1156         assert(stalls[tid].commit);
1157         stalls[tid].commit = false;
1158     }
1159 }
1160
1161 template <class Impl>
1162 bool
1163 DefaultRename<Impl>::checkStall(unsigned tid)
1164 {
1165     bool ret_val = false;
1166
1167     if (stalls[tid].iew) {
1168         DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1169         ret_val = true;
1170     } else if (stalls[tid].commit) {
1171         DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1172         ret_val = true;
1173     } else if (calcFreeROBEntries(tid) <= 0) {
1174         DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1175         ret_val = true;
1176     } else if (calcFreeIQEntries(tid) <= 0) {
1177         DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1178         ret_val = true;
1179     } else if (calcFreeLSQEntries(tid) <= 0) {
1180         DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1181         ret_val = true;
1182     } else if (renameMap[tid]->numFreeEntries() <= 0) {
1183         DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1184         ret_val = true;
1185     } else if (renameStatus[tid] == SerializeStall &&
1186                (!emptyROB[tid] || instsInProgress[tid])) {
1187         DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1188                 "empty.\n",
1189                 tid);
1190         ret_val = true;
1191     }
1192
1193     return ret_val;
1194 }
1195
1196 template <class Impl>
1197 void
1198 DefaultRename<Impl>::readFreeEntries(unsigned tid)
1199 {
1200     bool updated = false;
1201     if (fromIEW->iewInfo[tid].usedIQ) {
1202         freeEntries[tid].iqEntries =
1203             fromIEW->iewInfo[tid].freeIQEntries;
1204         updated = true;
1205     }
1206
1207     if (fromIEW->iewInfo[tid].usedLSQ) {
1208         freeEntries[tid].lsqEntries =
1209             fromIEW->iewInfo[tid].freeLSQEntries;
1210         updated = true;
1211     }
1212
1213     if (fromCommit->commitInfo[tid].usedROB) {
1214         freeEntries[tid].robEntries =
1215             fromCommit->commitInfo[tid].freeROBEntries;
1216         emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1217         updated = true;
1218     }
1219
1220     DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1221             tid,
1222             freeEntries[tid].iqEntries,
1223             freeEntries[tid].robEntries,
1224             freeEntries[tid].lsqEntries);
1225
1226     DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1227             tid, instsInProgress[tid]);
1228 }
1229
1230 template <class Impl>
1231 bool
1232 DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1233 {
1234     // Check if there's a squash signal, squash if there is
1235     // Check stall signals, block if necessary.
1236     // If status was blocked
1237     //     check if stall conditions have passed
1238     //         if so then go to unblocking
1239     // If status was Squashing
1240     //     check if squashing is not high.  Switch to running this cycle.
1241     // If status was serialize stall
1242     //     check if ROB is empty and no insts are in flight to the ROB
1243
1244     readFreeEntries(tid);
1245     readStallSignals(tid);
1246
1247     if (fromCommit->commitInfo[tid].squash) {
1248         DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1249                 "commit.\n", tid);
1250
1251 #if ISA_HAS_DELAY_SLOT
1252         InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1253 #else
1254         InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1255 #endif
1256
1257         squash(squashed_seq_num, tid);
1258
1259         return true;
1260     }
1261
1262     if (fromCommit->commitInfo[tid].robSquashing) {
1263         DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1264
1265         renameStatus[tid] = Squashing;
1266
1267         return true;
1268     }
1269
1270     if (checkStall(tid)) {
1271         return block(tid);
1272     }
1273
1274     if (renameStatus[tid] == Blocked) {
1275         DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1276                 tid);
1277
1278         renameStatus[tid] = Unblocking;
1279
1280         unblock(tid);
1281
1282         return true;
1283     }
1284
1285     if (renameStatus[tid] == Squashing) {
1286         // Switch status to running if rename isn't being told to block or
1287         // squash this cycle.
1288         if (resumeSerialize) {
1289             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1290                     tid);
1291
1292             renameStatus[tid] = SerializeStall;
1293             return true;
1294         } else if (resumeUnblocking) {
1295             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1296                     tid);
1297             renameStatus[tid] = Unblocking;
1298             return true;
1299         } else {
1300             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1301                     tid);
1302
1303             renameStatus[tid] = Running;
1304             return false;
1305         }
1306     }
1307
1308     if (renameStatus[tid] == SerializeStall) {
1309         // Stall ends once the ROB is free.
1310         DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1311                 "unblocking.\n", tid);
1312
1313         DynInstPtr serial_inst = serializeInst[tid];
1314
1315         renameStatus[tid] = Unblocking;
1316
1317         unblock(tid);
1318
1319         DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1320                 "PC %#x.\n",
1321                 tid, serial_inst->seqNum, serial_inst->readPC());
1322
1323         // Put instruction into queue here.
1324         serial_inst->clearSerializeBefore();
1325
1326         if (!skidBuffer[tid].empty()) {
1327             skidBuffer[tid].push_front(serial_inst);
1328         } else {
1329             insts[tid].push_front(serial_inst);
1330         }
1331
1332         DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1333                 " Adding to front of list.\n", tid);
1334
1335         serializeInst[tid] = NULL;
1336
1337         return true;
1338     }
1339
1340     // If we've reached this point, we have not gotten any signals that
1341     // cause rename to change its status.  Rename remains the same as before.
1342     return false;
1343 }
1344
1345 template<class Impl>
1346 void
1347 DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1348                                    unsigned tid)
1349 {
1350     if (inst_list.empty()) {
1351         // Mark a bit to say that I must serialize on the next instruction.
1352         serializeOnNextInst[tid] = true;
1353         return;
1354     }
1355
1356     // Set the next instruction as serializing.
1357     inst_list.front()->setSerializeBefore();
1358 }
1359
1360 template <class Impl>
1361 inline void
1362 DefaultRename<Impl>::incrFullStat(const FullSource &source)
1363 {
1364     switch (source) {
1365       case ROB:
1366         ++renameROBFullEvents;
1367         break;
1368       case IQ:
1369         ++renameIQFullEvents;
1370         break;
1371       case LSQ:
1372         ++renameLSQFullEvents;
1373         break;
1374       default:
1375         panic("Rename full stall stat should be incremented for a reason!");
1376         break;
1377     }
1378 }
1379
1380 template <class Impl>
1381 void
1382 DefaultRename<Impl>::dumpHistory()
1383 {
1384     typename std::list<RenameHistory>::iterator buf_it;
1385
1386     for (int i = 0; i < numThreads; i++) {
1387
1388         buf_it = historyBuffer[i].begin();
1389
1390         while (buf_it != historyBuffer[i].end()) {
1391             cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1392                     "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1393                     (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1394
1395             buf_it++;
1396         }
1397     }
1398 }