src/cpu/o3/rename_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Korey Sewell
  30  */
  31
  32 #include <list>
  33
  34 #include "arch/isa_traits.hh"
  35 #include "arch/regfile.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/o3/rename.hh"
  38
  39 template <class Impl>
  40 DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
  41     : cpu(_cpu),
  42       iewToRenameDelay(params->iewToRenameDelay),
  43       decodeToRenameDelay(params->decodeToRenameDelay),
  44       commitToRenameDelay(params->commitToRenameDelay),
  45       renameWidth(params->renameWidth),
  46       commitWidth(params->commitWidth),
  47       resumeSerialize(false),
  48       resumeUnblocking(false),
  49       numThreads(params->numberOfThreads),
  50       maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
  51 {
  52     _status = Inactive;
  53
  54     for (int i=0; i< numThreads; i++) {
  55         renameStatus[i] = Idle;
  56
  57         freeEntries[i].iqEntries = 0;
  58         freeEntries[i].lsqEntries = 0;
  59         freeEntries[i].robEntries = 0;
  60
  61         stalls[i].iew = false;
  62         stalls[i].commit = false;
  63         serializeInst[i] = NULL;
  64
  65         instsInProgress[i] = 0;
  66
  67         emptyROB[i] = true;
  68
  69         serializeOnNextInst[i] = false;
  70     }
  71
  72     // @todo: Make into a parameter.
  73     skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
  74 }
  75
  76 template <class Impl>
  77 std::string
  78 DefaultRename<Impl>::name() const
  79 {
  80     return cpu->name() + ".rename";
  81 }
  82
  83 template <class Impl>
  84 void
  85 DefaultRename<Impl>::regStats()
  86 {
  87     renameSquashCycles
  88         .name(name() + ".RENAME:SquashCycles")
  89         .desc("Number of cycles rename is squashing")
  90         .prereq(renameSquashCycles);
  91     renameIdleCycles
  92         .name(name() + ".RENAME:IdleCycles")
  93         .desc("Number of cycles rename is idle")
  94         .prereq(renameIdleCycles);
  95     renameBlockCycles
  96         .name(name() + ".RENAME:BlockCycles")
  97         .desc("Number of cycles rename is blocking")
  98         .prereq(renameBlockCycles);
  99     renameSerializeStallCycles
 100         .name(name() + ".RENAME:serializeStallCycles")
 101         .desc("count of cycles rename stalled for serializing inst")
 102         .flags(Stats::total);
 103     renameRunCycles
 104         .name(name() + ".RENAME:RunCycles")
 105         .desc("Number of cycles rename is running")
 106         .prereq(renameIdleCycles);
 107     renameUnblockCycles
 108         .name(name() + ".RENAME:UnblockCycles")
 109         .desc("Number of cycles rename is unblocking")
 110         .prereq(renameUnblockCycles);
 111     renameRenamedInsts
 112         .name(name() + ".RENAME:RenamedInsts")
 113         .desc("Number of instructions processed by rename")
 114         .prereq(renameRenamedInsts);
 115     renameSquashedInsts
 116         .name(name() + ".RENAME:SquashedInsts")
 117         .desc("Number of squashed instructions processed by rename")
 118         .prereq(renameSquashedInsts);
 119     renameROBFullEvents
 120         .name(name() + ".RENAME:ROBFullEvents")
 121         .desc("Number of times rename has blocked due to ROB full")
 122         .prereq(renameROBFullEvents);
 123     renameIQFullEvents
 124         .name(name() + ".RENAME:IQFullEvents")
 125         .desc("Number of times rename has blocked due to IQ full")
 126         .prereq(renameIQFullEvents);
 127     renameLSQFullEvents
 128         .name(name() + ".RENAME:LSQFullEvents")
 129         .desc("Number of times rename has blocked due to LSQ full")
 130         .prereq(renameLSQFullEvents);
 131     renameFullRegistersEvents
 132         .name(name() + ".RENAME:FullRegisterEvents")
 133         .desc("Number of times there has been no free registers")
 134         .prereq(renameFullRegistersEvents);
 135     renameRenamedOperands
 136         .name(name() + ".RENAME:RenamedOperands")
 137         .desc("Number of destination operands rename has renamed")
 138         .prereq(renameRenamedOperands);
 139     renameRenameLookups
 140         .name(name() + ".RENAME:RenameLookups")
 141         .desc("Number of register rename lookups that rename has made")
 142         .prereq(renameRenameLookups);
 143     renameCommittedMaps
 144         .name(name() + ".RENAME:CommittedMaps")
 145         .desc("Number of HB maps that are committed")
 146         .prereq(renameCommittedMaps);
 147     renameUndoneMaps
 148         .name(name() + ".RENAME:UndoneMaps")
 149         .desc("Number of HB maps that are undone due to squashing")
 150         .prereq(renameUndoneMaps);
 151     renamedSerializing
 152         .name(name() + ".RENAME:serializingInsts")
 153         .desc("count of serializing insts renamed")
 154         .flags(Stats::total)
 155         ;
 156     renamedTempSerializing
 157         .name(name() + ".RENAME:tempSerializingInsts")
 158         .desc("count of temporary serializing insts renamed")
 159         .flags(Stats::total)
 160         ;
 161     renameSkidInsts
 162         .name(name() + ".RENAME:skidInsts")
 163         .desc("count of insts added to the skid buffer")
 164         .flags(Stats::total)
 165         ;
 166 }
 167
 168 template <class Impl>
 169 void
 170 DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 171 {
 172     timeBuffer = tb_ptr;
 173
 174     // Setup wire to read information from time buffer, from IEW stage.
 175     fromIEW = timeBuffer->getWire(-iewToRenameDelay);
 176
 177     // Setup wire to read infromation from time buffer, from commit stage.
 178     fromCommit = timeBuffer->getWire(-commitToRenameDelay);
 179
 180     // Setup wire to write information to previous stages.
 181     toDecode = timeBuffer->getWire(0);
 182 }
 183
 184 template <class Impl>
 185 void
 186 DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 187 {
 188     renameQueue = rq_ptr;
 189
 190     // Setup wire to write information to future stages.
 191     toIEW = renameQueue->getWire(0);
 192 }
 193
 194 template <class Impl>
 195 void
 196 DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
 197 {
 198     decodeQueue = dq_ptr;
 199
 200     // Setup wire to get information from decode.
 201     fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
 202 }
 203
 204 template <class Impl>
 205 void
 206 DefaultRename<Impl>::initStage()
 207 {
 208     // Grab the number of free entries directly from the stages.
 209     for (int tid=0; tid < numThreads; tid++) {
 210         freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
 211         freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
 212         freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
 213         emptyROB[tid] = true;
 214     }
 215 }
 216
 217 template<class Impl>
 218 void
 219 DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 220 {
 221     activeThreads = at_ptr;
 222 }
 223
 224
 225 template <class Impl>
 226 void
 227 DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
 228 {
 229     for (int i=0; i<numThreads; i++) {
 230         renameMap[i] = &rm_ptr[i];
 231     }
 232 }
 233
 234 template <class Impl>
 235 void
 236 DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
 237 {
 238     freeList = fl_ptr;
 239 }
 240
 241 template<class Impl>
 242 void
 243 DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
 244 {
 245     scoreboard = _scoreboard;
 246 }
 247
 248 template <class Impl>
 249 bool
 250 DefaultRename<Impl>::drain()
 251 {
 252     // Rename is ready to switch out at any time.
 253     cpu->signalDrained();
 254     return true;
 255 }
 256
 257 template <class Impl>
 258 void
 259 DefaultRename<Impl>::switchOut()
 260 {
 261     // Clear any state, fix up the rename map.
 262     for (int i = 0; i < numThreads; i++) {
 263         typename std::list<RenameHistory>::iterator hb_it =
 264             historyBuffer[i].begin();
 265
 266         while (!historyBuffer[i].empty()) {
 267             assert(hb_it != historyBuffer[i].end());
 268
 269             DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
 270                     "number %i.\n", i, (*hb_it).instSeqNum);
 271
 272             // Tell the rename map to set the architected register to the
 273             // previous physical register that it was renamed to.
 274             renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
 275
 276             // Put the renamed physical register back on the free list.
 277             freeList->addReg(hb_it->newPhysReg);
 278
 279             // Be sure to mark its register as ready if it's a misc register.
 280             if (hb_it->newPhysReg >= maxPhysicalRegs) {
 281                 scoreboard->setReg(hb_it->newPhysReg);
 282             }
 283
 284             historyBuffer[i].erase(hb_it++);
 285         }
 286         insts[i].clear();
 287         skidBuffer[i].clear();
 288     }
 289 }
 290
 291 template <class Impl>
 292 void
 293 DefaultRename<Impl>::takeOverFrom()
 294 {
 295     _status = Inactive;
 296     initStage();
 297
 298     // Reset all state prior to taking over from the other CPU.
 299     for (int i=0; i< numThreads; i++) {
 300         renameStatus[i] = Idle;
 301
 302         stalls[i].iew = false;
 303         stalls[i].commit = false;
 304         serializeInst[i] = NULL;
 305
 306         instsInProgress[i] = 0;
 307
 308         emptyROB[i] = true;
 309
 310         serializeOnNextInst[i] = false;
 311     }
 312 }
 313
 314 template <class Impl>
 315 void
 316 DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
 317 {
 318     DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
 319
 320     // Clear the stall signal if rename was blocked or unblocking before.
 321     // If it still needs to block, the blocking should happen the next
 322     // cycle and there should be space to hold everything due to the squash.
 323     if (renameStatus[tid] == Blocked ||
 324         renameStatus[tid] == Unblocking) {
 325         toDecode->renameUnblock[tid] = 1;
 326
 327         resumeSerialize = false;
 328         serializeInst[tid] = NULL;
 329     } else if (renameStatus[tid] == SerializeStall) {
 330         if (serializeInst[tid]->seqNum <= squash_seq_num) {
 331             DPRINTF(Rename, "Rename will resume serializing after squash\n");
 332             resumeSerialize = true;
 333             assert(serializeInst[tid]);
 334         } else {
 335             resumeSerialize = false;
 336             toDecode->renameUnblock[tid] = 1;
 337
 338             serializeInst[tid] = NULL;
 339         }
 340     }
 341
 342     // Set the status to Squashing.
 343     renameStatus[tid] = Squashing;
 344
 345     // Squash any instructions from decode.
 346     unsigned squashCount = 0;
 347
 348     for (int i=0; i<fromDecode->size; i++) {
 349         if (fromDecode->insts[i]->threadNumber == tid &&
 350             fromDecode->insts[i]->seqNum > squash_seq_num) {
 351             fromDecode->insts[i]->setSquashed();
 352             wroteToTimeBuffer = true;
 353             squashCount++;
 354         }
 355
 356     }
 357
 358     // Clear the instruction list and skid buffer in case they have any
 359     // insts in them.
 360     insts[tid].clear();
 361
 362     // Clear the skid buffer in case it has any data in it.
 363     skidBuffer[tid].clear();
 364
 365     doSquash(squash_seq_num, tid);
 366 }
 367
 368 template <class Impl>
 369 void
 370 DefaultRename<Impl>::tick()
 371 {
 372     wroteToTimeBuffer = false;
 373
 374     blockThisCycle = false;
 375
 376     bool status_change = false;
 377
 378     toIEWIndex = 0;
 379
 380     sortInsts();
 381
 382     std::list<unsigned>::iterator threads = activeThreads->begin();
 383     std::list<unsigned>::iterator end = activeThreads->end();
 384
 385     // Check stall and squash signals.
 386     while (threads != end) {
 387         unsigned tid = *threads++;
 388
 389         DPRINTF(Rename, "Processing [tid:%i]\n", tid);
 390
 391         status_change = checkSignalsAndUpdate(tid) || status_change;
 392
 393         rename(status_change, tid);
 394     }
 395
 396     if (status_change) {
 397         updateStatus();
 398     }
 399
 400     if (wroteToTimeBuffer) {
 401         DPRINTF(Activity, "Activity this cycle.\n");
 402         cpu->activityThisCycle();
 403     }
 404
 405     threads = activeThreads->begin();
 406
 407     while (threads != end) {
 408         unsigned tid = *threads++;
 409
 410         // If we committed this cycle then doneSeqNum will be > 0
 411         if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
 412             !fromCommit->commitInfo[tid].squash &&
 413             renameStatus[tid] != Squashing) {
 414
 415             removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
 416                                   tid);
 417         }
 418     }
 419
 420     // @todo: make into updateProgress function
 421     for (int tid=0; tid < numThreads; tid++) {
 422         instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
 423
 424         assert(instsInProgress[tid] >=0);
 425     }
 426
 427 }
 428
 429 template<class Impl>
 430 void
 431 DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
 432 {
 433     // If status is Running or idle,
 434     //     call renameInsts()
 435     // If status is Unblocking,
 436     //     buffer any instructions coming from decode
 437     //     continue trying to empty skid buffer
 438     //     check if stall conditions have passed
 439
 440     if (renameStatus[tid] == Blocked) {
 441         ++renameBlockCycles;
 442     } else if (renameStatus[tid] == Squashing) {
 443         ++renameSquashCycles;
 444     } else if (renameStatus[tid] == SerializeStall) {
 445         ++renameSerializeStallCycles;
 446         // If we are currently in SerializeStall and resumeSerialize
 447         // was set, then that means that we are resuming serializing
 448         // this cycle.  Tell the previous stages to block.
 449         if (resumeSerialize) {
 450             resumeSerialize = false;
 451             block(tid);
 452             toDecode->renameUnblock[tid] = false;
 453         }
 454     } else if (renameStatus[tid] == Unblocking) {
 455         if (resumeUnblocking) {
 456             block(tid);
 457             resumeUnblocking = false;
 458             toDecode->renameUnblock[tid] = false;
 459         }
 460     }
 461
 462     if (renameStatus[tid] == Running ||
 463         renameStatus[tid] == Idle) {
 464         DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
 465                 "stage.\n", tid);
 466
 467         renameInsts(tid);
 468     } else if (renameStatus[tid] == Unblocking) {
 469         renameInsts(tid);
 470
 471         if (validInsts()) {
 472             // Add the current inputs to the skid buffer so they can be
 473             // reprocessed when this stage unblocks.
 474             skidInsert(tid);
 475         }
 476
 477         // If we switched over to blocking, then there's a potential for
 478         // an overall status change.
 479         status_change = unblock(tid) || status_change || blockThisCycle;
 480     }
 481 }
 482
 483 template <class Impl>
 484 void
 485 DefaultRename<Impl>::renameInsts(unsigned tid)
 486 {
 487     // Instructions can be either in the skid buffer or the queue of
 488     // instructions coming from decode, depending on the status.
 489     int insts_available = renameStatus[tid] == Unblocking ?
 490         skidBuffer[tid].size() : insts[tid].size();
 491
 492     // Check the decode queue to see if instructions are available.
 493     // If there are no available instructions to rename, then do nothing.
 494     if (insts_available == 0) {
 495         DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
 496                 tid);
 497         // Should I change status to idle?
 498         ++renameIdleCycles;
 499         return;
 500     } else if (renameStatus[tid] == Unblocking) {
 501         ++renameUnblockCycles;
 502     } else if (renameStatus[tid] == Running) {
 503         ++renameRunCycles;
 504     }
 505
 506     DynInstPtr inst;
 507
 508     // Will have to do a different calculation for the number of free
 509     // entries.
 510     int free_rob_entries = calcFreeROBEntries(tid);
 511     int free_iq_entries  = calcFreeIQEntries(tid);
 512     int free_lsq_entries = calcFreeLSQEntries(tid);
 513     int min_free_entries = free_rob_entries;
 514
 515     FullSource source = ROB;
 516
 517     if (free_iq_entries < min_free_entries) {
 518         min_free_entries = free_iq_entries;
 519         source = IQ;
 520     }
 521
 522     if (free_lsq_entries < min_free_entries) {
 523         min_free_entries = free_lsq_entries;
 524         source = LSQ;
 525     }
 526
 527     // Check if there's any space left.
 528     if (min_free_entries <= 0) {
 529         DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
 530                 "entries.\n"
 531                 "ROB has %i free entries.\n"
 532                 "IQ has %i free entries.\n"
 533                 "LSQ has %i free entries.\n",
 534                 tid,
 535                 free_rob_entries,
 536                 free_iq_entries,
 537                 free_lsq_entries);
 538
 539         blockThisCycle = true;
 540
 541         block(tid);
 542
 543         incrFullStat(source);
 544
 545         return;
 546     } else if (min_free_entries < insts_available) {
 547         DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
 548                 "%i insts available, but only %i insts can be "
 549                 "renamed due to ROB/IQ/LSQ limits.\n",
 550                 tid, insts_available, min_free_entries);
 551
 552         insts_available = min_free_entries;
 553
 554         blockThisCycle = true;
 555
 556         incrFullStat(source);
 557     }
 558
 559     InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
 560         skidBuffer[tid] : insts[tid];
 561
 562     DPRINTF(Rename, "[tid:%u]: %i available instructions to "
 563             "send iew.\n", tid, insts_available);
 564
 565     DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
 566             "dispatched to IQ last cycle.\n",
 567             tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
 568
 569     // Handle serializing the next instruction if necessary.
 570     if (serializeOnNextInst[tid]) {
 571         if (emptyROB[tid] && instsInProgress[tid] == 0) {
 572             // ROB already empty; no need to serialize.
 573             serializeOnNextInst[tid] = false;
 574         } else if (!insts_to_rename.empty()) {
 575             insts_to_rename.front()->setSerializeBefore();
 576         }
 577     }
 578
 579     int renamed_insts = 0;
 580
 581     while (insts_available > 0 &&  toIEWIndex < renameWidth) {
 582         DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
 583
 584         assert(!insts_to_rename.empty());
 585
 586         inst = insts_to_rename.front();
 587
 588         insts_to_rename.pop_front();
 589
 590         if (renameStatus[tid] == Unblocking) {
 591             DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
 592                     "skidBuffer\n",
 593                     tid, inst->seqNum, inst->readPC());
 594         }
 595
 596         if (inst->isSquashed()) {
 597             DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
 598                     "squashed, skipping.\n",
 599                     tid, inst->seqNum, inst->readPC());
 600
 601             ++renameSquashedInsts;
 602
 603             // Decrement how many instructions are available.
 604             --insts_available;
 605
 606             continue;
 607         }
 608
 609         DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
 610                 "PC %#x.\n",
 611                 tid, inst->seqNum, inst->readPC());
 612
 613         // Handle serializeAfter/serializeBefore instructions.
 614         // serializeAfter marks the next instruction as serializeBefore.
 615         // serializeBefore makes the instruction wait in rename until the ROB
 616         // is empty.
 617
 618         // In this model, IPR accesses are serialize before
 619         // instructions, and store conditionals are serialize after
 620         // instructions.  This is mainly due to lack of support for
 621         // out-of-order operations of either of those classes of
 622         // instructions.
 623         if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
 624             !inst->isSerializeHandled()) {
 625             DPRINTF(Rename, "Serialize before instruction encountered.\n");
 626
 627             if (!inst->isTempSerializeBefore()) {
 628                 renamedSerializing++;
 629                 inst->setSerializeHandled();
 630             } else {
 631                 renamedTempSerializing++;
 632             }
 633
 634             // Change status over to SerializeStall so that other stages know
 635             // what this is blocked on.
 636             renameStatus[tid] = SerializeStall;
 637
 638             serializeInst[tid] = inst;
 639
 640             blockThisCycle = true;
 641
 642             break;
 643         } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
 644                    !inst->isSerializeHandled()) {
 645             DPRINTF(Rename, "Serialize after instruction encountered.\n");
 646
 647             renamedSerializing++;
 648
 649             inst->setSerializeHandled();
 650
 651             serializeAfter(insts_to_rename, tid);
 652         }
 653
 654         // Check here to make sure there are enough destination registers
 655         // to rename to.  Otherwise block.
 656         if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
 657             DPRINTF(Rename, "Blocking due to lack of free "
 658                     "physical registers to rename to.\n");
 659             blockThisCycle = true;
 660             insts_to_rename.push_front(inst);
 661             ++renameFullRegistersEvents;
 662
 663             break;
 664         }
 665
 666         renameSrcRegs(inst, inst->threadNumber);
 667
 668         renameDestRegs(inst, inst->threadNumber);
 669
 670         ++renamed_insts;
 671
 672         // Put instruction in rename queue.
 673         toIEW->insts[toIEWIndex] = inst;
 674         ++(toIEW->size);
 675
 676         // Increment which instruction we're on.
 677         ++toIEWIndex;
 678
 679         // Decrement how many instructions are available.
 680         --insts_available;
 681     }
 682
 683     instsInProgress[tid] += renamed_insts;
 684     renameRenamedInsts += renamed_insts;
 685
 686     // If we wrote to the time buffer, record this.
 687     if (toIEWIndex) {
 688         wroteToTimeBuffer = true;
 689     }
 690
 691     // Check if there's any instructions left that haven't yet been renamed.
 692     // If so then block.
 693     if (insts_available) {
 694         blockThisCycle = true;
 695     }
 696
 697     if (blockThisCycle) {
 698         block(tid);
 699         toDecode->renameUnblock[tid] = false;
 700     }
 701 }
 702
 703 template<class Impl>
 704 void
 705 DefaultRename<Impl>::skidInsert(unsigned tid)
 706 {
 707     DynInstPtr inst = NULL;
 708
 709     while (!insts[tid].empty()) {
 710         inst = insts[tid].front();
 711
 712         insts[tid].pop_front();
 713
 714         assert(tid == inst->threadNumber);
 715
 716         DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
 717                 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
 718
 719         ++renameSkidInsts;
 720
 721         skidBuffer[tid].push_back(inst);
 722     }
 723
 724     if (skidBuffer[tid].size() > skidBufferMax)
 725     {
 726         typename InstQueue::iterator it;
 727         warn("Skidbuffer contents:\n");
 728         for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
 729         {
 730             warn("[tid:%u]: %s [sn:%i].\n", tid,
 731                     (*it)->staticInst->disassemble(inst->readPC()),
 732                     (*it)->seqNum);
 733         }
 734         panic("Skidbuffer Exceeded Max Size");
 735     }
 736 }
 737
 738 template <class Impl>
 739 void
 740 DefaultRename<Impl>::sortInsts()
 741 {
 742     int insts_from_decode = fromDecode->size;
 743 #ifdef DEBUG
 744     for (int i=0; i < numThreads; i++)
 745         assert(insts[i].empty());
 746 #endif
 747     for (int i = 0; i < insts_from_decode; ++i) {
 748         DynInstPtr inst = fromDecode->insts[i];
 749         insts[inst->threadNumber].push_back(inst);
 750     }
 751 }
 752
 753 template<class Impl>
 754 bool
 755 DefaultRename<Impl>::skidsEmpty()
 756 {
 757     std::list<unsigned>::iterator threads = activeThreads->begin();
 758     std::list<unsigned>::iterator end = activeThreads->end();
 759
 760     while (threads != end) {
 761         unsigned tid = *threads++;
 762
 763         if (!skidBuffer[tid].empty())
 764             return false;
 765     }
 766
 767     return true;
 768 }
 769
 770 template<class Impl>
 771 void
 772 DefaultRename<Impl>::updateStatus()
 773 {
 774     bool any_unblocking = false;
 775
 776     std::list<unsigned>::iterator threads = activeThreads->begin();
 777     std::list<unsigned>::iterator end = activeThreads->end();
 778
 779     while (threads != end) {
 780         unsigned tid = *threads++;
 781
 782         if (renameStatus[tid] == Unblocking) {
 783             any_unblocking = true;
 784             break;
 785         }
 786     }
 787
 788     // Rename will have activity if it's unblocking.
 789     if (any_unblocking) {
 790         if (_status == Inactive) {
 791             _status = Active;
 792
 793             DPRINTF(Activity, "Activating stage.\n");
 794
 795             cpu->activateStage(O3CPU::RenameIdx);
 796         }
 797     } else {
 798         // If it's not unblocking, then rename will not have any internal
 799         // activity.  Switch it to inactive.
 800         if (_status == Active) {
 801             _status = Inactive;
 802             DPRINTF(Activity, "Deactivating stage.\n");
 803
 804             cpu->deactivateStage(O3CPU::RenameIdx);
 805         }
 806     }
 807 }
 808
 809 template <class Impl>
 810 bool
 811 DefaultRename<Impl>::block(unsigned tid)
 812 {
 813     DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
 814
 815     // Add the current inputs onto the skid buffer, so they can be
 816     // reprocessed when this stage unblocks.
 817     skidInsert(tid);
 818
 819     // Only signal backwards to block if the previous stages do not think
 820     // rename is already blocked.
 821     if (renameStatus[tid] != Blocked) {
 822         // If resumeUnblocking is set, we unblocked during the squash,
 823         // but now we're have unblocking status. We need to tell earlier
 824         // stages to block.
 825         if (resumeUnblocking || renameStatus[tid] != Unblocking) {
 826             toDecode->renameBlock[tid] = true;
 827             toDecode->renameUnblock[tid] = false;
 828             wroteToTimeBuffer = true;
 829         }
 830
 831         // Rename can not go from SerializeStall to Blocked, otherwise
 832         // it would not know to complete the serialize stall.
 833         if (renameStatus[tid] != SerializeStall) {
 834             // Set status to Blocked.
 835             renameStatus[tid] = Blocked;
 836             return true;
 837         }
 838     }
 839
 840     return false;
 841 }
 842
 843 template <class Impl>
 844 bool
 845 DefaultRename<Impl>::unblock(unsigned tid)
 846 {
 847     DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
 848
 849     // Rename is done unblocking if the skid buffer is empty.
 850     if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
 851
 852         DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
 853
 854         toDecode->renameUnblock[tid] = true;
 855         wroteToTimeBuffer = true;
 856
 857         renameStatus[tid] = Running;
 858         return true;
 859     }
 860
 861     return false;
 862 }
 863
 864 template <class Impl>
 865 void
 866 DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
 867 {
 868     typename std::list<RenameHistory>::iterator hb_it =
 869         historyBuffer[tid].begin();
 870
 871     // After a syscall squashes everything, the history buffer may be empty
 872     // but the ROB may still be squashing instructions.
 873     if (historyBuffer[tid].empty()) {
 874         return;
 875     }
 876
 877     // Go through the most recent instructions, undoing the mappings
 878     // they did and freeing up the registers.
 879     while (!historyBuffer[tid].empty() &&
 880            (*hb_it).instSeqNum > squashed_seq_num) {
 881         assert(hb_it != historyBuffer[tid].end());
 882
 883         DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
 884                 "number %i.\n", tid, (*hb_it).instSeqNum);
 885
 886         // Tell the rename map to set the architected register to the
 887         // previous physical register that it was renamed to.
 888         renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
 889
 890         // Put the renamed physical register back on the free list.
 891         freeList->addReg(hb_it->newPhysReg);
 892
 893         // Be sure to mark its register as ready if it's a misc register.
 894         if (hb_it->newPhysReg >= maxPhysicalRegs) {
 895             scoreboard->setReg(hb_it->newPhysReg);
 896         }
 897
 898         historyBuffer[tid].erase(hb_it++);
 899
 900         ++renameUndoneMaps;
 901     }
 902 }
 903
 904 template<class Impl>
 905 void
 906 DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
 907 {
 908     DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
 909             "history buffer %u (size=%i), until [sn:%lli].\n",
 910             tid, tid, historyBuffer[tid].size(), inst_seq_num);
 911
 912     typename std::list<RenameHistory>::iterator hb_it =
 913         historyBuffer[tid].end();
 914
 915     --hb_it;
 916
 917     if (historyBuffer[tid].empty()) {
 918         DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
 919         return;
 920     } else if (hb_it->instSeqNum > inst_seq_num) {
 921         DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
 922                 "that a syscall happened recently.\n", tid);
 923         return;
 924     }
 925
 926     // Commit all the renames up until (and including) the committed sequence
 927     // number. Some or even all of the committed instructions may not have
 928     // rename histories if they did not have destination registers that were
 929     // renamed.
 930     while (!historyBuffer[tid].empty() &&
 931            hb_it != historyBuffer[tid].end() &&
 932            (*hb_it).instSeqNum <= inst_seq_num) {
 933
 934         DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
 935                 "[sn:%lli].\n",
 936                 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
 937
 938         freeList->addReg((*hb_it).prevPhysReg);
 939         ++renameCommittedMaps;
 940
 941         historyBuffer[tid].erase(hb_it--);
 942     }
 943 }
 944
 945 template <class Impl>
 946 inline void
 947 DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
 948 {
 949     assert(renameMap[tid] != 0);
 950
 951     unsigned num_src_regs = inst->numSrcRegs();
 952
 953     // Get the architectual register numbers from the source and
 954     // destination operands, and redirect them to the right register.
 955     // Will need to mark dependencies though.
 956     for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
 957         RegIndex src_reg = inst->srcRegIdx(src_idx);
 958         RegIndex flat_src_reg = src_reg;
 959         if (src_reg < TheISA::FP_Base_DepTag) {
 960             flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
 961             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
 962         } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
 963             src_reg = src_reg - TheISA::FP_Base_DepTag;
 964             flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg);
 965             flat_src_reg += TheISA::NumIntRegs;
 966         } else {
 967             flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
 968             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
 969         }
 970
 971         inst->flattenSrcReg(src_idx, flat_src_reg);
 972
 973         // Look up the source registers to get the phys. register they've
 974         // been renamed to, and set the sources to those registers.
 975         PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
 976
 977         DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
 978                 "physical reg %i.\n", tid, (int)flat_src_reg,
 979                 (int)renamed_reg);
 980
 981         inst->renameSrcReg(src_idx, renamed_reg);
 982
 983         // See if the register is ready or not.
 984         if (scoreboard->getReg(renamed_reg) == true) {
 985             DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg);
 986
 987             inst->markSrcRegReady(src_idx);
 988         } else {
 989             DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg);
 990         }
 991
 992         ++renameRenameLookups;
 993     }
 994 }
 995
 996 template <class Impl>
 997 inline void
 998 DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
 999 {
1000     typename RenameMap::RenameInfo rename_result;
1001
1002     unsigned num_dest_regs = inst->numDestRegs();
1003
1004     // Rename the destination registers.
1005     for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1006         RegIndex dest_reg = inst->destRegIdx(dest_idx);
1007         RegIndex flat_dest_reg = dest_reg;
1008         if (dest_reg < TheISA::FP_Base_DepTag) {
1009             // Integer registers are flattened.
1010             flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1011             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1012         } else {
1013             // Floating point and Miscellaneous registers need their indexes
1014             // adjusted to account for the expanded number of flattened int regs.
1015             flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1016             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
1017         }
1018
1019         inst->flattenDestReg(dest_idx, flat_dest_reg);
1020
1021         // Get the physical register that the destination will be
1022         // renamed to.
1023         rename_result = renameMap[tid]->rename(flat_dest_reg);
1024
1025         //Mark Scoreboard entry as not ready
1026         scoreboard->unsetReg(rename_result.first);
1027
1028         DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1029                 "reg %i.\n", tid, (int)flat_dest_reg,
1030                 (int)rename_result.first);
1031
1032         // Record the rename information so that a history can be kept.
1033         RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1034                                rename_result.first,
1035                                rename_result.second);
1036
1037         historyBuffer[tid].push_front(hb_entry);
1038
1039         DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1040                 "(size=%i), [sn:%lli].\n",tid,
1041                 historyBuffer[tid].size(),
1042                 (*historyBuffer[tid].begin()).instSeqNum);
1043
1044         // Tell the instruction to rename the appropriate destination
1045         // register (dest_idx) to the new physical register
1046         // (rename_result.first), and record the previous physical
1047         // register that the same logical register was renamed to
1048         // (rename_result.second).
1049         inst->renameDestReg(dest_idx,
1050                             rename_result.first,
1051                             rename_result.second);
1052
1053         ++renameRenamedOperands;
1054     }
1055 }
1056
1057 template <class Impl>
1058 inline int
1059 DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1060 {
1061     int num_free = freeEntries[tid].robEntries -
1062                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1063
1064     //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1065
1066     return num_free;
1067 }
1068
1069 template <class Impl>
1070 inline int
1071 DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1072 {
1073     int num_free = freeEntries[tid].iqEntries -
1074                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1075
1076     //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1077
1078     return num_free;
1079 }
1080
1081 template <class Impl>
1082 inline int
1083 DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1084 {
1085     int num_free = freeEntries[tid].lsqEntries -
1086                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1087
1088     //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1089
1090     return num_free;
1091 }
1092
1093 template <class Impl>
1094 unsigned
1095 DefaultRename<Impl>::validInsts()
1096 {
1097     unsigned inst_count = 0;
1098
1099     for (int i=0; i<fromDecode->size; i++) {
1100         if (!fromDecode->insts[i]->isSquashed())
1101             inst_count++;
1102     }
1103
1104     return inst_count;
1105 }
1106
1107 template <class Impl>
1108 void
1109 DefaultRename<Impl>::readStallSignals(unsigned tid)
1110 {
1111     if (fromIEW->iewBlock[tid]) {
1112         stalls[tid].iew = true;
1113     }
1114
1115     if (fromIEW->iewUnblock[tid]) {
1116         assert(stalls[tid].iew);
1117         stalls[tid].iew = false;
1118     }
1119
1120     if (fromCommit->commitBlock[tid]) {
1121         stalls[tid].commit = true;
1122     }
1123
1124     if (fromCommit->commitUnblock[tid]) {
1125         assert(stalls[tid].commit);
1126         stalls[tid].commit = false;
1127     }
1128 }
1129
1130 template <class Impl>
1131 bool
1132 DefaultRename<Impl>::checkStall(unsigned tid)
1133 {
1134     bool ret_val = false;
1135
1136     if (stalls[tid].iew) {
1137         DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1138         ret_val = true;
1139     } else if (stalls[tid].commit) {
1140         DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1141         ret_val = true;
1142     } else if (calcFreeROBEntries(tid) <= 0) {
1143         DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1144         ret_val = true;
1145     } else if (calcFreeIQEntries(tid) <= 0) {
1146         DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1147         ret_val = true;
1148     } else if (calcFreeLSQEntries(tid) <= 0) {
1149         DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1150         ret_val = true;
1151     } else if (renameMap[tid]->numFreeEntries() <= 0) {
1152         DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1153         ret_val = true;
1154     } else if (renameStatus[tid] == SerializeStall &&
1155                (!emptyROB[tid] || instsInProgress[tid])) {
1156         DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1157                 "empty.\n",
1158                 tid);
1159         ret_val = true;
1160     }
1161
1162     return ret_val;
1163 }
1164
1165 template <class Impl>
1166 void
1167 DefaultRename<Impl>::readFreeEntries(unsigned tid)
1168 {
1169     bool updated = false;
1170     if (fromIEW->iewInfo[tid].usedIQ) {
1171         freeEntries[tid].iqEntries =
1172             fromIEW->iewInfo[tid].freeIQEntries;
1173         updated = true;
1174     }
1175
1176     if (fromIEW->iewInfo[tid].usedLSQ) {
1177         freeEntries[tid].lsqEntries =
1178             fromIEW->iewInfo[tid].freeLSQEntries;
1179         updated = true;
1180     }
1181
1182     if (fromCommit->commitInfo[tid].usedROB) {
1183         freeEntries[tid].robEntries =
1184             fromCommit->commitInfo[tid].freeROBEntries;
1185         emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1186         updated = true;
1187     }
1188
1189     DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1190             tid,
1191             freeEntries[tid].iqEntries,
1192             freeEntries[tid].robEntries,
1193             freeEntries[tid].lsqEntries);
1194
1195     DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1196             tid, instsInProgress[tid]);
1197 }
1198
1199 template <class Impl>
1200 bool
1201 DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1202 {
1203     // Check if there's a squash signal, squash if there is
1204     // Check stall signals, block if necessary.
1205     // If status was blocked
1206     //     check if stall conditions have passed
1207     //         if so then go to unblocking
1208     // If status was Squashing
1209     //     check if squashing is not high.  Switch to running this cycle.
1210     // If status was serialize stall
1211     //     check if ROB is empty and no insts are in flight to the ROB
1212
1213     readFreeEntries(tid);
1214     readStallSignals(tid);
1215
1216     if (fromCommit->commitInfo[tid].squash) {
1217         DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1218                 "commit.\n", tid);
1219
1220         squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1221
1222         return true;
1223     }
1224
1225     if (fromCommit->commitInfo[tid].robSquashing) {
1226         DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1227
1228         renameStatus[tid] = Squashing;
1229
1230         return true;
1231     }
1232
1233     if (checkStall(tid)) {
1234         return block(tid);
1235     }
1236
1237     if (renameStatus[tid] == Blocked) {
1238         DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1239                 tid);
1240
1241         renameStatus[tid] = Unblocking;
1242
1243         unblock(tid);
1244
1245         return true;
1246     }
1247
1248     if (renameStatus[tid] == Squashing) {
1249         // Switch status to running if rename isn't being told to block or
1250         // squash this cycle.
1251         if (resumeSerialize) {
1252             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1253                     tid);
1254
1255             renameStatus[tid] = SerializeStall;
1256             return true;
1257         } else if (resumeUnblocking) {
1258             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1259                     tid);
1260             renameStatus[tid] = Unblocking;
1261             return true;
1262         } else {
1263             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1264                     tid);
1265
1266             renameStatus[tid] = Running;
1267             return false;
1268         }
1269     }
1270
1271     if (renameStatus[tid] == SerializeStall) {
1272         // Stall ends once the ROB is free.
1273         DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1274                 "unblocking.\n", tid);
1275
1276         DynInstPtr serial_inst = serializeInst[tid];
1277
1278         renameStatus[tid] = Unblocking;
1279
1280         unblock(tid);
1281
1282         DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1283                 "PC %#x.\n",
1284                 tid, serial_inst->seqNum, serial_inst->readPC());
1285
1286         // Put instruction into queue here.
1287         serial_inst->clearSerializeBefore();
1288
1289         if (!skidBuffer[tid].empty()) {
1290             skidBuffer[tid].push_front(serial_inst);
1291         } else {
1292             insts[tid].push_front(serial_inst);
1293         }
1294
1295         DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1296                 " Adding to front of list.\n", tid);
1297
1298         serializeInst[tid] = NULL;
1299
1300         return true;
1301     }
1302
1303     // If we've reached this point, we have not gotten any signals that
1304     // cause rename to change its status.  Rename remains the same as before.
1305     return false;
1306 }
1307
1308 template<class Impl>
1309 void
1310 DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1311                                    unsigned tid)
1312 {
1313     if (inst_list.empty()) {
1314         // Mark a bit to say that I must serialize on the next instruction.
1315         serializeOnNextInst[tid] = true;
1316         return;
1317     }
1318
1319     // Set the next instruction as serializing.
1320     inst_list.front()->setSerializeBefore();
1321 }
1322
1323 template <class Impl>
1324 inline void
1325 DefaultRename<Impl>::incrFullStat(const FullSource &source)
1326 {
1327     switch (source) {
1328       case ROB:
1329         ++renameROBFullEvents;
1330         break;
1331       case IQ:
1332         ++renameIQFullEvents;
1333         break;
1334       case LSQ:
1335         ++renameLSQFullEvents;
1336         break;
1337       default:
1338         panic("Rename full stall stat should be incremented for a reason!");
1339         break;
1340     }
1341 }
1342
1343 template <class Impl>
1344 void
1345 DefaultRename<Impl>::dumpHistory()
1346 {
1347     typename std::list<RenameHistory>::iterator buf_it;
1348
1349     for (int i = 0; i < numThreads; i++) {
1350
1351         buf_it = historyBuffer[i].begin();
1352
1353         while (buf_it != historyBuffer[i].end()) {
1354             cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1355                     "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1356                     (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1357
1358             buf_it++;
1359         }
1360     }
1361 }