src/cpu/o3/rename_impl.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include <list>
  45
  46 #include "arch/isa_traits.hh"
  47 #include "arch/registers.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/o3/rename.hh"
  50 #include "debug/Activity.hh"
  51 #include "debug/Rename.hh"
  52 #include "params/DerivO3CPU.hh"
  53
  54 using namespace std;
  55
  56 template <class Impl>
  57 DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
  58     : cpu(_cpu),
  59       iewToRenameDelay(params->iewToRenameDelay),
  60       decodeToRenameDelay(params->decodeToRenameDelay),
  61       commitToRenameDelay(params->commitToRenameDelay),
  62       renameWidth(params->renameWidth),
  63       commitWidth(params->commitWidth),
  64       resumeSerialize(false),
  65       resumeUnblocking(false),
  66       numThreads(params->numThreads),
  67       maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
  68 {
  69     _status = Inactive;
  70
  71     for (ThreadID tid = 0; tid < numThreads; tid++) {
  72         renameStatus[tid] = Idle;
  73
  74         freeEntries[tid].iqEntries = 0;
  75         freeEntries[tid].lsqEntries = 0;
  76         freeEntries[tid].robEntries = 0;
  77
  78         stalls[tid].iew = false;
  79         stalls[tid].commit = false;
  80         serializeInst[tid] = NULL;
  81
  82         instsInProgress[tid] = 0;
  83
  84         emptyROB[tid] = true;
  85
  86         serializeOnNextInst[tid] = false;
  87     }
  88
  89     // @todo: Make into a parameter.
  90     skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
  91 }
  92
  93 template <class Impl>
  94 std::string
  95 DefaultRename<Impl>::name() const
  96 {
  97     return cpu->name() + ".rename";
  98 }
  99
 100 template <class Impl>
 101 void
 102 DefaultRename<Impl>::regStats()
 103 {
 104     renameSquashCycles
 105         .name(name() + ".SquashCycles")
 106         .desc("Number of cycles rename is squashing")
 107         .prereq(renameSquashCycles);
 108     renameIdleCycles
 109         .name(name() + ".IdleCycles")
 110         .desc("Number of cycles rename is idle")
 111         .prereq(renameIdleCycles);
 112     renameBlockCycles
 113         .name(name() + ".BlockCycles")
 114         .desc("Number of cycles rename is blocking")
 115         .prereq(renameBlockCycles);
 116     renameSerializeStallCycles
 117         .name(name() + ".serializeStallCycles")
 118         .desc("count of cycles rename stalled for serializing inst")
 119         .flags(Stats::total);
 120     renameRunCycles
 121         .name(name() + ".RunCycles")
 122         .desc("Number of cycles rename is running")
 123         .prereq(renameIdleCycles);
 124     renameUnblockCycles
 125         .name(name() + ".UnblockCycles")
 126         .desc("Number of cycles rename is unblocking")
 127         .prereq(renameUnblockCycles);
 128     renameRenamedInsts
 129         .name(name() + ".RenamedInsts")
 130         .desc("Number of instructions processed by rename")
 131         .prereq(renameRenamedInsts);
 132     renameSquashedInsts
 133         .name(name() + ".SquashedInsts")
 134         .desc("Number of squashed instructions processed by rename")
 135         .prereq(renameSquashedInsts);
 136     renameROBFullEvents
 137         .name(name() + ".ROBFullEvents")
 138         .desc("Number of times rename has blocked due to ROB full")
 139         .prereq(renameROBFullEvents);
 140     renameIQFullEvents
 141         .name(name() + ".IQFullEvents")
 142         .desc("Number of times rename has blocked due to IQ full")
 143         .prereq(renameIQFullEvents);
 144     renameLSQFullEvents
 145         .name(name() + ".LSQFullEvents")
 146         .desc("Number of times rename has blocked due to LSQ full")
 147         .prereq(renameLSQFullEvents);
 148     renameFullRegistersEvents
 149         .name(name() + ".FullRegisterEvents")
 150         .desc("Number of times there has been no free registers")
 151         .prereq(renameFullRegistersEvents);
 152     renameRenamedOperands
 153         .name(name() + ".RenamedOperands")
 154         .desc("Number of destination operands rename has renamed")
 155         .prereq(renameRenamedOperands);
 156     renameRenameLookups
 157         .name(name() + ".RenameLookups")
 158         .desc("Number of register rename lookups that rename has made")
 159         .prereq(renameRenameLookups);
 160     renameCommittedMaps
 161         .name(name() + ".CommittedMaps")
 162         .desc("Number of HB maps that are committed")
 163         .prereq(renameCommittedMaps);
 164     renameUndoneMaps
 165         .name(name() + ".UndoneMaps")
 166         .desc("Number of HB maps that are undone due to squashing")
 167         .prereq(renameUndoneMaps);
 168     renamedSerializing
 169         .name(name() + ".serializingInsts")
 170         .desc("count of serializing insts renamed")
 171         .flags(Stats::total)
 172         ;
 173     renamedTempSerializing
 174         .name(name() + ".tempSerializingInsts")
 175         .desc("count of temporary serializing insts renamed")
 176         .flags(Stats::total)
 177         ;
 178     renameSkidInsts
 179         .name(name() + ".skidInsts")
 180         .desc("count of insts added to the skid buffer")
 181         .flags(Stats::total)
 182         ;
 183     intRenameLookups
 184         .name(name() + ".int_rename_lookups")
 185         .desc("Number of integer rename lookups")
 186         .prereq(intRenameLookups);
 187     fpRenameLookups
 188         .name(name() + ".fp_rename_lookups")
 189         .desc("Number of floating rename lookups")
 190         .prereq(fpRenameLookups);
 191 }
 192
 193 template <class Impl>
 194 void
 195 DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 196 {
 197     timeBuffer = tb_ptr;
 198
 199     // Setup wire to read information from time buffer, from IEW stage.
 200     fromIEW = timeBuffer->getWire(-iewToRenameDelay);
 201
 202     // Setup wire to read infromation from time buffer, from commit stage.
 203     fromCommit = timeBuffer->getWire(-commitToRenameDelay);
 204
 205     // Setup wire to write information to previous stages.
 206     toDecode = timeBuffer->getWire(0);
 207 }
 208
 209 template <class Impl>
 210 void
 211 DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 212 {
 213     renameQueue = rq_ptr;
 214
 215     // Setup wire to write information to future stages.
 216     toIEW = renameQueue->getWire(0);
 217 }
 218
 219 template <class Impl>
 220 void
 221 DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
 222 {
 223     decodeQueue = dq_ptr;
 224
 225     // Setup wire to get information from decode.
 226     fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
 227 }
 228
 229 template <class Impl>
 230 void
 231 DefaultRename<Impl>::initStage()
 232 {
 233     // Grab the number of free entries directly from the stages.
 234     for (ThreadID tid = 0; tid < numThreads; tid++) {
 235         freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
 236         freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
 237         freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
 238         emptyROB[tid] = true;
 239     }
 240 }
 241
 242 template<class Impl>
 243 void
 244 DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
 245 {
 246     activeThreads = at_ptr;
 247 }
 248
 249
 250 template <class Impl>
 251 void
 252 DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
 253 {
 254     for (ThreadID tid = 0; tid < numThreads; tid++)
 255         renameMap[tid] = &rm_ptr[tid];
 256 }
 257
 258 template <class Impl>
 259 void
 260 DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
 261 {
 262     freeList = fl_ptr;
 263 }
 264
 265 template<class Impl>
 266 void
 267 DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
 268 {
 269     scoreboard = _scoreboard;
 270 }
 271
 272 template <class Impl>
 273 bool
 274 DefaultRename<Impl>::drain()
 275 {
 276     // Rename is ready to switch out at any time.
 277     cpu->signalDrained();
 278     return true;
 279 }
 280
 281 template <class Impl>
 282 void
 283 DefaultRename<Impl>::switchOut()
 284 {
 285     // Clear any state, fix up the rename map.
 286     for (ThreadID tid = 0; tid < numThreads; tid++) {
 287         typename std::list<RenameHistory>::iterator hb_it =
 288             historyBuffer[tid].begin();
 289
 290         while (!historyBuffer[tid].empty()) {
 291             assert(hb_it != historyBuffer[tid].end());
 292
 293             DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
 294                     "number %i.\n", tid, (*hb_it).instSeqNum);
 295
 296             // Tell the rename map to set the architected register to the
 297             // previous physical register that it was renamed to.
 298             renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
 299
 300             // Put the renamed physical register back on the free list.
 301             freeList->addReg(hb_it->newPhysReg);
 302
 303             // Be sure to mark its register as ready if it's a misc register.
 304             if (hb_it->newPhysReg >= maxPhysicalRegs) {
 305                 scoreboard->setReg(hb_it->newPhysReg);
 306             }
 307
 308             historyBuffer[tid].erase(hb_it++);
 309         }
 310         insts[tid].clear();
 311         skidBuffer[tid].clear();
 312     }
 313 }
 314
 315 template <class Impl>
 316 void
 317 DefaultRename<Impl>::takeOverFrom()
 318 {
 319     _status = Inactive;
 320     initStage();
 321
 322     // Reset all state prior to taking over from the other CPU.
 323     for (ThreadID tid = 0; tid < numThreads; tid++) {
 324         renameStatus[tid] = Idle;
 325
 326         stalls[tid].iew = false;
 327         stalls[tid].commit = false;
 328         serializeInst[tid] = NULL;
 329
 330         instsInProgress[tid] = 0;
 331
 332         emptyROB[tid] = true;
 333
 334         serializeOnNextInst[tid] = false;
 335     }
 336 }
 337
 338 template <class Impl>
 339 void
 340 DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
 341 {
 342     DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
 343
 344     // Clear the stall signal if rename was blocked or unblocking before.
 345     // If it still needs to block, the blocking should happen the next
 346     // cycle and there should be space to hold everything due to the squash.
 347     if (renameStatus[tid] == Blocked ||
 348         renameStatus[tid] == Unblocking) {
 349         toDecode->renameUnblock[tid] = 1;
 350
 351         resumeSerialize = false;
 352         serializeInst[tid] = NULL;
 353     } else if (renameStatus[tid] == SerializeStall) {
 354         if (serializeInst[tid]->seqNum <= squash_seq_num) {
 355             DPRINTF(Rename, "Rename will resume serializing after squash\n");
 356             resumeSerialize = true;
 357             assert(serializeInst[tid]);
 358         } else {
 359             resumeSerialize = false;
 360             toDecode->renameUnblock[tid] = 1;
 361
 362             serializeInst[tid] = NULL;
 363         }
 364     }
 365
 366     // Set the status to Squashing.
 367     renameStatus[tid] = Squashing;
 368
 369     // Squash any instructions from decode.
 370     unsigned squashCount = 0;
 371
 372     for (int i=0; i<fromDecode->size; i++) {
 373         if (fromDecode->insts[i]->threadNumber == tid &&
 374             fromDecode->insts[i]->seqNum > squash_seq_num) {
 375             fromDecode->insts[i]->setSquashed();
 376             wroteToTimeBuffer = true;
 377             squashCount++;
 378         }
 379
 380     }
 381
 382     // Clear the instruction list and skid buffer in case they have any
 383     // insts in them.
 384     insts[tid].clear();
 385
 386     // Clear the skid buffer in case it has any data in it.
 387     skidBuffer[tid].clear();
 388
 389     doSquash(squash_seq_num, tid);
 390 }
 391
 392 template <class Impl>
 393 void
 394 DefaultRename<Impl>::tick()
 395 {
 396     wroteToTimeBuffer = false;
 397
 398     blockThisCycle = false;
 399
 400     bool status_change = false;
 401
 402     toIEWIndex = 0;
 403
 404     sortInsts();
 405
 406     list<ThreadID>::iterator threads = activeThreads->begin();
 407     list<ThreadID>::iterator end = activeThreads->end();
 408
 409     // Check stall and squash signals.
 410     while (threads != end) {
 411         ThreadID tid = *threads++;
 412
 413         DPRINTF(Rename, "Processing [tid:%i]\n", tid);
 414
 415         status_change = checkSignalsAndUpdate(tid) || status_change;
 416
 417         rename(status_change, tid);
 418     }
 419
 420     if (status_change) {
 421         updateStatus();
 422     }
 423
 424     if (wroteToTimeBuffer) {
 425         DPRINTF(Activity, "Activity this cycle.\n");
 426         cpu->activityThisCycle();
 427     }
 428
 429     threads = activeThreads->begin();
 430
 431     while (threads != end) {
 432         ThreadID tid = *threads++;
 433
 434         // If we committed this cycle then doneSeqNum will be > 0
 435         if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
 436             !fromCommit->commitInfo[tid].squash &&
 437             renameStatus[tid] != Squashing) {
 438
 439             removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
 440                                   tid);
 441         }
 442     }
 443
 444     // @todo: make into updateProgress function
 445     for (ThreadID tid = 0; tid < numThreads; tid++) {
 446         instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
 447
 448         assert(instsInProgress[tid] >=0);
 449     }
 450
 451 }
 452
 453 template<class Impl>
 454 void
 455 DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
 456 {
 457     // If status is Running or idle,
 458     //     call renameInsts()
 459     // If status is Unblocking,
 460     //     buffer any instructions coming from decode
 461     //     continue trying to empty skid buffer
 462     //     check if stall conditions have passed
 463
 464     if (renameStatus[tid] == Blocked) {
 465         ++renameBlockCycles;
 466     } else if (renameStatus[tid] == Squashing) {
 467         ++renameSquashCycles;
 468     } else if (renameStatus[tid] == SerializeStall) {
 469         ++renameSerializeStallCycles;
 470         // If we are currently in SerializeStall and resumeSerialize
 471         // was set, then that means that we are resuming serializing
 472         // this cycle.  Tell the previous stages to block.
 473         if (resumeSerialize) {
 474             resumeSerialize = false;
 475             block(tid);
 476             toDecode->renameUnblock[tid] = false;
 477         }
 478     } else if (renameStatus[tid] == Unblocking) {
 479         if (resumeUnblocking) {
 480             block(tid);
 481             resumeUnblocking = false;
 482             toDecode->renameUnblock[tid] = false;
 483         }
 484     }
 485
 486     if (renameStatus[tid] == Running ||
 487         renameStatus[tid] == Idle) {
 488         DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
 489                 "stage.\n", tid);
 490
 491         renameInsts(tid);
 492     } else if (renameStatus[tid] == Unblocking) {
 493         renameInsts(tid);
 494
 495         if (validInsts()) {
 496             // Add the current inputs to the skid buffer so they can be
 497             // reprocessed when this stage unblocks.
 498             skidInsert(tid);
 499         }
 500
 501         // If we switched over to blocking, then there's a potential for
 502         // an overall status change.
 503         status_change = unblock(tid) || status_change || blockThisCycle;
 504     }
 505 }
 506
 507 template <class Impl>
 508 void
 509 DefaultRename<Impl>::renameInsts(ThreadID tid)
 510 {
 511     // Instructions can be either in the skid buffer or the queue of
 512     // instructions coming from decode, depending on the status.
 513     int insts_available = renameStatus[tid] == Unblocking ?
 514         skidBuffer[tid].size() : insts[tid].size();
 515
 516     // Check the decode queue to see if instructions are available.
 517     // If there are no available instructions to rename, then do nothing.
 518     if (insts_available == 0) {
 519         DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
 520                 tid);
 521         // Should I change status to idle?
 522         ++renameIdleCycles;
 523         return;
 524     } else if (renameStatus[tid] == Unblocking) {
 525         ++renameUnblockCycles;
 526     } else if (renameStatus[tid] == Running) {
 527         ++renameRunCycles;
 528     }
 529
 530     DynInstPtr inst;
 531
 532     // Will have to do a different calculation for the number of free
 533     // entries.
 534     int free_rob_entries = calcFreeROBEntries(tid);
 535     int free_iq_entries  = calcFreeIQEntries(tid);
 536     int free_lsq_entries = calcFreeLSQEntries(tid);
 537     int min_free_entries = free_rob_entries;
 538
 539     FullSource source = ROB;
 540
 541     if (free_iq_entries < min_free_entries) {
 542         min_free_entries = free_iq_entries;
 543         source = IQ;
 544     }
 545
 546     if (free_lsq_entries < min_free_entries) {
 547         min_free_entries = free_lsq_entries;
 548         source = LSQ;
 549     }
 550
 551     // Check if there's any space left.
 552     if (min_free_entries <= 0) {
 553         DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
 554                 "entries.\n"
 555                 "ROB has %i free entries.\n"
 556                 "IQ has %i free entries.\n"
 557                 "LSQ has %i free entries.\n",
 558                 tid,
 559                 free_rob_entries,
 560                 free_iq_entries,
 561                 free_lsq_entries);
 562
 563         blockThisCycle = true;
 564
 565         block(tid);
 566
 567         incrFullStat(source);
 568
 569         return;
 570     } else if (min_free_entries < insts_available) {
 571         DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
 572                 "%i insts available, but only %i insts can be "
 573                 "renamed due to ROB/IQ/LSQ limits.\n",
 574                 tid, insts_available, min_free_entries);
 575
 576         insts_available = min_free_entries;
 577
 578         blockThisCycle = true;
 579
 580         incrFullStat(source);
 581     }
 582
 583     InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
 584         skidBuffer[tid] : insts[tid];
 585
 586     DPRINTF(Rename, "[tid:%u]: %i available instructions to "
 587             "send iew.\n", tid, insts_available);
 588
 589     DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
 590             "dispatched to IQ last cycle.\n",
 591             tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
 592
 593     // Handle serializing the next instruction if necessary.
 594     if (serializeOnNextInst[tid]) {
 595         if (emptyROB[tid] && instsInProgress[tid] == 0) {
 596             // ROB already empty; no need to serialize.
 597             serializeOnNextInst[tid] = false;
 598         } else if (!insts_to_rename.empty()) {
 599             insts_to_rename.front()->setSerializeBefore();
 600         }
 601     }
 602
 603     int renamed_insts = 0;
 604
 605     while (insts_available > 0 &&  toIEWIndex < renameWidth) {
 606         DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
 607
 608         assert(!insts_to_rename.empty());
 609
 610         inst = insts_to_rename.front();
 611
 612         insts_to_rename.pop_front();
 613
 614         if (renameStatus[tid] == Unblocking) {
 615             DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
 616                     "skidBuffer\n", tid, inst->seqNum, inst->pcState());
 617         }
 618
 619         if (inst->isSquashed()) {
 620             DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
 621                     "squashed, skipping.\n", tid, inst->seqNum,
 622                     inst->pcState());
 623
 624             ++renameSquashedInsts;
 625
 626             // Decrement how many instructions are available.
 627             --insts_available;
 628
 629             continue;
 630         }
 631
 632         DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
 633                 "PC %s.\n", tid, inst->seqNum, inst->pcState());
 634
 635         // Handle serializeAfter/serializeBefore instructions.
 636         // serializeAfter marks the next instruction as serializeBefore.
 637         // serializeBefore makes the instruction wait in rename until the ROB
 638         // is empty.
 639
 640         // In this model, IPR accesses are serialize before
 641         // instructions, and store conditionals are serialize after
 642         // instructions.  This is mainly due to lack of support for
 643         // out-of-order operations of either of those classes of
 644         // instructions.
 645         if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
 646             !inst->isSerializeHandled()) {
 647             DPRINTF(Rename, "Serialize before instruction encountered.\n");
 648
 649             if (!inst->isTempSerializeBefore()) {
 650                 renamedSerializing++;
 651                 inst->setSerializeHandled();
 652             } else {
 653                 renamedTempSerializing++;
 654             }
 655
 656             // Change status over to SerializeStall so that other stages know
 657             // what this is blocked on.
 658             renameStatus[tid] = SerializeStall;
 659
 660             serializeInst[tid] = inst;
 661
 662             blockThisCycle = true;
 663
 664             break;
 665         } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
 666                    !inst->isSerializeHandled()) {
 667             DPRINTF(Rename, "Serialize after instruction encountered.\n");
 668
 669             renamedSerializing++;
 670
 671             inst->setSerializeHandled();
 672
 673             serializeAfter(insts_to_rename, tid);
 674         }
 675
 676         // Check here to make sure there are enough destination registers
 677         // to rename to.  Otherwise block.
 678         if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
 679             DPRINTF(Rename, "Blocking due to lack of free "
 680                     "physical registers to rename to.\n");
 681             blockThisCycle = true;
 682             insts_to_rename.push_front(inst);
 683             ++renameFullRegistersEvents;
 684
 685             break;
 686         }
 687
 688         renameSrcRegs(inst, inst->threadNumber);
 689
 690         renameDestRegs(inst, inst->threadNumber);
 691
 692         ++renamed_insts;
 693
 694 #if TRACING_ON
 695         inst->renameTick = curTick() - inst->fetchTick;
 696 #endif
 697
 698         // Put instruction in rename queue.
 699         toIEW->insts[toIEWIndex] = inst;
 700         ++(toIEW->size);
 701
 702         // Increment which instruction we're on.
 703         ++toIEWIndex;
 704
 705         // Decrement how many instructions are available.
 706         --insts_available;
 707     }
 708
 709     instsInProgress[tid] += renamed_insts;
 710     renameRenamedInsts += renamed_insts;
 711
 712     // If we wrote to the time buffer, record this.
 713     if (toIEWIndex) {
 714         wroteToTimeBuffer = true;
 715     }
 716
 717     // Check if there's any instructions left that haven't yet been renamed.
 718     // If so then block.
 719     if (insts_available) {
 720         blockThisCycle = true;
 721     }
 722
 723     if (blockThisCycle) {
 724         block(tid);
 725         toDecode->renameUnblock[tid] = false;
 726     }
 727 }
 728
 729 template<class Impl>
 730 void
 731 DefaultRename<Impl>::skidInsert(ThreadID tid)
 732 {
 733     DynInstPtr inst = NULL;
 734
 735     while (!insts[tid].empty()) {
 736         inst = insts[tid].front();
 737
 738         insts[tid].pop_front();
 739
 740         assert(tid == inst->threadNumber);
 741
 742         DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
 743                 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
 744
 745         ++renameSkidInsts;
 746
 747         skidBuffer[tid].push_back(inst);
 748     }
 749
 750     if (skidBuffer[tid].size() > skidBufferMax)
 751     {
 752         typename InstQueue::iterator it;
 753         warn("Skidbuffer contents:\n");
 754         for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
 755         {
 756             warn("[tid:%u]: %s [sn:%i].\n", tid,
 757                     (*it)->staticInst->disassemble(inst->instAddr()),
 758                     (*it)->seqNum);
 759         }
 760         panic("Skidbuffer Exceeded Max Size");
 761     }
 762 }
 763
 764 template <class Impl>
 765 void
 766 DefaultRename<Impl>::sortInsts()
 767 {
 768     int insts_from_decode = fromDecode->size;
 769     for (int i = 0; i < insts_from_decode; ++i) {
 770         DynInstPtr inst = fromDecode->insts[i];
 771         insts[inst->threadNumber].push_back(inst);
 772     }
 773 }
 774
 775 template<class Impl>
 776 bool
 777 DefaultRename<Impl>::skidsEmpty()
 778 {
 779     list<ThreadID>::iterator threads = activeThreads->begin();
 780     list<ThreadID>::iterator end = activeThreads->end();
 781
 782     while (threads != end) {
 783         ThreadID tid = *threads++;
 784
 785         if (!skidBuffer[tid].empty())
 786             return false;
 787     }
 788
 789     return true;
 790 }
 791
 792 template<class Impl>
 793 void
 794 DefaultRename<Impl>::updateStatus()
 795 {
 796     bool any_unblocking = false;
 797
 798     list<ThreadID>::iterator threads = activeThreads->begin();
 799     list<ThreadID>::iterator end = activeThreads->end();
 800
 801     while (threads != end) {
 802         ThreadID tid = *threads++;
 803
 804         if (renameStatus[tid] == Unblocking) {
 805             any_unblocking = true;
 806             break;
 807         }
 808     }
 809
 810     // Rename will have activity if it's unblocking.
 811     if (any_unblocking) {
 812         if (_status == Inactive) {
 813             _status = Active;
 814
 815             DPRINTF(Activity, "Activating stage.\n");
 816
 817             cpu->activateStage(O3CPU::RenameIdx);
 818         }
 819     } else {
 820         // If it's not unblocking, then rename will not have any internal
 821         // activity.  Switch it to inactive.
 822         if (_status == Active) {
 823             _status = Inactive;
 824             DPRINTF(Activity, "Deactivating stage.\n");
 825
 826             cpu->deactivateStage(O3CPU::RenameIdx);
 827         }
 828     }
 829 }
 830
 831 template <class Impl>
 832 bool
 833 DefaultRename<Impl>::block(ThreadID tid)
 834 {
 835     DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
 836
 837     // Add the current inputs onto the skid buffer, so they can be
 838     // reprocessed when this stage unblocks.
 839     skidInsert(tid);
 840
 841     // Only signal backwards to block if the previous stages do not think
 842     // rename is already blocked.
 843     if (renameStatus[tid] != Blocked) {
 844         // If resumeUnblocking is set, we unblocked during the squash,
 845         // but now we're have unblocking status. We need to tell earlier
 846         // stages to block.
 847         if (resumeUnblocking || renameStatus[tid] != Unblocking) {
 848             toDecode->renameBlock[tid] = true;
 849             toDecode->renameUnblock[tid] = false;
 850             wroteToTimeBuffer = true;
 851         }
 852
 853         // Rename can not go from SerializeStall to Blocked, otherwise
 854         // it would not know to complete the serialize stall.
 855         if (renameStatus[tid] != SerializeStall) {
 856             // Set status to Blocked.
 857             renameStatus[tid] = Blocked;
 858             return true;
 859         }
 860     }
 861
 862     return false;
 863 }
 864
 865 template <class Impl>
 866 bool
 867 DefaultRename<Impl>::unblock(ThreadID tid)
 868 {
 869     DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
 870
 871     // Rename is done unblocking if the skid buffer is empty.
 872     if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
 873
 874         DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
 875
 876         toDecode->renameUnblock[tid] = true;
 877         wroteToTimeBuffer = true;
 878
 879         renameStatus[tid] = Running;
 880         return true;
 881     }
 882
 883     return false;
 884 }
 885
 886 template <class Impl>
 887 void
 888 DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
 889 {
 890     typename std::list<RenameHistory>::iterator hb_it =
 891         historyBuffer[tid].begin();
 892
 893     // After a syscall squashes everything, the history buffer may be empty
 894     // but the ROB may still be squashing instructions.
 895     if (historyBuffer[tid].empty()) {
 896         return;
 897     }
 898
 899     // Go through the most recent instructions, undoing the mappings
 900     // they did and freeing up the registers.
 901     while (!historyBuffer[tid].empty() &&
 902            (*hb_it).instSeqNum > squashed_seq_num) {
 903         assert(hb_it != historyBuffer[tid].end());
 904
 905         DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
 906                 "number %i.\n", tid, (*hb_it).instSeqNum);
 907
 908         // Tell the rename map to set the architected register to the
 909         // previous physical register that it was renamed to.
 910         renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
 911
 912         // Put the renamed physical register back on the free list.
 913         freeList->addReg(hb_it->newPhysReg);
 914
 915         // Be sure to mark its register as ready if it's a misc register.
 916         if (hb_it->newPhysReg >= maxPhysicalRegs) {
 917             scoreboard->setReg(hb_it->newPhysReg);
 918         }
 919
 920         historyBuffer[tid].erase(hb_it++);
 921
 922         ++renameUndoneMaps;
 923     }
 924 }
 925
 926 template<class Impl>
 927 void
 928 DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
 929 {
 930     DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
 931             "history buffer %u (size=%i), until [sn:%lli].\n",
 932             tid, tid, historyBuffer[tid].size(), inst_seq_num);
 933
 934     typename std::list<RenameHistory>::iterator hb_it =
 935         historyBuffer[tid].end();
 936
 937     --hb_it;
 938
 939     if (historyBuffer[tid].empty()) {
 940         DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
 941         return;
 942     } else if (hb_it->instSeqNum > inst_seq_num) {
 943         DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
 944                 "that a syscall happened recently.\n", tid);
 945         return;
 946     }
 947
 948     // Commit all the renames up until (and including) the committed sequence
 949     // number. Some or even all of the committed instructions may not have
 950     // rename histories if they did not have destination registers that were
 951     // renamed.
 952     while (!historyBuffer[tid].empty() &&
 953            hb_it != historyBuffer[tid].end() &&
 954            (*hb_it).instSeqNum <= inst_seq_num) {
 955
 956         DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
 957                 "[sn:%lli].\n",
 958                 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
 959
 960         freeList->addReg((*hb_it).prevPhysReg);
 961         ++renameCommittedMaps;
 962
 963         historyBuffer[tid].erase(hb_it--);
 964     }
 965 }
 966
 967 template <class Impl>
 968 inline void
 969 DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
 970 {
 971     assert(renameMap[tid] != 0);
 972
 973     unsigned num_src_regs = inst->numSrcRegs();
 974
 975     // Get the architectual register numbers from the source and
 976     // destination operands, and redirect them to the right register.
 977     // Will need to mark dependencies though.
 978     for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
 979         RegIndex src_reg = inst->srcRegIdx(src_idx);
 980         RegIndex flat_src_reg = src_reg;
 981         if (src_reg < TheISA::FP_Base_DepTag) {
 982             flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
 983             DPRINTF(Rename, "Flattening index %d to %d.\n",
 984                     (int)src_reg, (int)flat_src_reg);
 985         } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
 986             src_reg = src_reg - TheISA::FP_Base_DepTag;
 987             flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
 988             DPRINTF(Rename, "Flattening index %d to %d.\n",
 989                     (int)src_reg, (int)flat_src_reg);
 990             flat_src_reg += TheISA::NumIntRegs;
 991         } else if (src_reg < TheISA::Max_DepTag) {
 992             flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
 993                            TheISA::NumFloatRegs + TheISA::NumIntRegs;
 994             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
 995                     src_reg, flat_src_reg);
 996         } else {
 997             panic("Reg index is out of bound: %d.", src_reg);
 998         }
 999
1000         // Look up the source registers to get the phys. register they've
1001         // been renamed to, and set the sources to those registers.
1002         PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1003
1004         DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1005                 "physical reg %i.\n", tid, (int)flat_src_reg,
1006                 (int)renamed_reg);
1007
1008         inst->renameSrcReg(src_idx, renamed_reg);
1009
1010         // See if the register is ready or not.
1011         if (scoreboard->getReg(renamed_reg) == true) {
1012             DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1013                     tid, renamed_reg);
1014
1015             inst->markSrcRegReady(src_idx);
1016         } else {
1017             DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1018                     tid, renamed_reg);
1019         }
1020
1021         ++renameRenameLookups;
1022         inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
1023     }
1024 }
1025
1026 template <class Impl>
1027 inline void
1028 DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1029 {
1030     typename RenameMap::RenameInfo rename_result;
1031
1032     unsigned num_dest_regs = inst->numDestRegs();
1033
1034     // Rename the destination registers.
1035     for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1036         RegIndex dest_reg = inst->destRegIdx(dest_idx);
1037         RegIndex flat_dest_reg = dest_reg;
1038         if (dest_reg < TheISA::FP_Base_DepTag) {
1039             // Integer registers are flattened.
1040             flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1041             DPRINTF(Rename, "Flattening index %d to %d.\n",
1042                     (int)dest_reg, (int)flat_dest_reg);
1043         } else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
1044             dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1045             flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1046             DPRINTF(Rename, "Flattening index %d to %d.\n",
1047                     (int)dest_reg, (int)flat_dest_reg);
1048             flat_dest_reg += TheISA::NumIntRegs;
1049         } else if (dest_reg < TheISA::Max_DepTag) {
1050             // Floating point and Miscellaneous registers need their indexes
1051             // adjusted to account for the expanded number of flattened int regs.
1052             flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1053                             TheISA::NumIntRegs + TheISA::NumFloatRegs;
1054             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1055                     dest_reg, flat_dest_reg);
1056         } else {
1057             panic("Reg index is out of bound: %d.", dest_reg);
1058         }
1059
1060         inst->flattenDestReg(dest_idx, flat_dest_reg);
1061
1062         // Get the physical register that the destination will be
1063         // renamed to.
1064         rename_result = renameMap[tid]->rename(flat_dest_reg);
1065
1066         //Mark Scoreboard entry as not ready
1067         if (dest_reg < TheISA::Ctrl_Base_DepTag)
1068             scoreboard->unsetReg(rename_result.first);
1069
1070         DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1071                 "reg %i.\n", tid, (int)flat_dest_reg,
1072                 (int)rename_result.first);
1073
1074         // Record the rename information so that a history can be kept.
1075         RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1076                                rename_result.first,
1077                                rename_result.second);
1078
1079         historyBuffer[tid].push_front(hb_entry);
1080
1081         DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1082                 "(size=%i), [sn:%lli].\n",tid,
1083                 historyBuffer[tid].size(),
1084                 (*historyBuffer[tid].begin()).instSeqNum);
1085
1086         // Tell the instruction to rename the appropriate destination
1087         // register (dest_idx) to the new physical register
1088         // (rename_result.first), and record the previous physical
1089         // register that the same logical register was renamed to
1090         // (rename_result.second).
1091         inst->renameDestReg(dest_idx,
1092                             rename_result.first,
1093                             rename_result.second);
1094
1095         ++renameRenamedOperands;
1096     }
1097 }
1098
1099 template <class Impl>
1100 inline int
1101 DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1102 {
1103     int num_free = freeEntries[tid].robEntries -
1104                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1105
1106     //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1107
1108     return num_free;
1109 }
1110
1111 template <class Impl>
1112 inline int
1113 DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1114 {
1115     int num_free = freeEntries[tid].iqEntries -
1116                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1117
1118     //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1119
1120     return num_free;
1121 }
1122
1123 template <class Impl>
1124 inline int
1125 DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1126 {
1127     int num_free = freeEntries[tid].lsqEntries -
1128                   (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1129
1130     //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1131
1132     return num_free;
1133 }
1134
1135 template <class Impl>
1136 unsigned
1137 DefaultRename<Impl>::validInsts()
1138 {
1139     unsigned inst_count = 0;
1140
1141     for (int i=0; i<fromDecode->size; i++) {
1142         if (!fromDecode->insts[i]->isSquashed())
1143             inst_count++;
1144     }
1145
1146     return inst_count;
1147 }
1148
1149 template <class Impl>
1150 void
1151 DefaultRename<Impl>::readStallSignals(ThreadID tid)
1152 {
1153     if (fromIEW->iewBlock[tid]) {
1154         stalls[tid].iew = true;
1155     }
1156
1157     if (fromIEW->iewUnblock[tid]) {
1158         assert(stalls[tid].iew);
1159         stalls[tid].iew = false;
1160     }
1161
1162     if (fromCommit->commitBlock[tid]) {
1163         stalls[tid].commit = true;
1164     }
1165
1166     if (fromCommit->commitUnblock[tid]) {
1167         assert(stalls[tid].commit);
1168         stalls[tid].commit = false;
1169     }
1170 }
1171
1172 template <class Impl>
1173 bool
1174 DefaultRename<Impl>::checkStall(ThreadID tid)
1175 {
1176     bool ret_val = false;
1177
1178     if (stalls[tid].iew) {
1179         DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1180         ret_val = true;
1181     } else if (stalls[tid].commit) {
1182         DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1183         ret_val = true;
1184     } else if (calcFreeROBEntries(tid) <= 0) {
1185         DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1186         ret_val = true;
1187     } else if (calcFreeIQEntries(tid) <= 0) {
1188         DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1189         ret_val = true;
1190     } else if (calcFreeLSQEntries(tid) <= 0) {
1191         DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1192         ret_val = true;
1193     } else if (renameMap[tid]->numFreeEntries() <= 0) {
1194         DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1195         ret_val = true;
1196     } else if (renameStatus[tid] == SerializeStall &&
1197                (!emptyROB[tid] || instsInProgress[tid])) {
1198         DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1199                 "empty.\n",
1200                 tid);
1201         ret_val = true;
1202     }
1203
1204     return ret_val;
1205 }
1206
1207 template <class Impl>
1208 void
1209 DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1210 {
1211     if (fromIEW->iewInfo[tid].usedIQ)
1212         freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1213
1214     if (fromIEW->iewInfo[tid].usedLSQ)
1215         freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1216
1217     if (fromCommit->commitInfo[tid].usedROB) {
1218         freeEntries[tid].robEntries =
1219             fromCommit->commitInfo[tid].freeROBEntries;
1220         emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1221     }
1222
1223     DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1224             tid,
1225             freeEntries[tid].iqEntries,
1226             freeEntries[tid].robEntries,
1227             freeEntries[tid].lsqEntries);
1228
1229     DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1230             tid, instsInProgress[tid]);
1231 }
1232
1233 template <class Impl>
1234 bool
1235 DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1236 {
1237     // Check if there's a squash signal, squash if there is
1238     // Check stall signals, block if necessary.
1239     // If status was blocked
1240     //     check if stall conditions have passed
1241     //         if so then go to unblocking
1242     // If status was Squashing
1243     //     check if squashing is not high.  Switch to running this cycle.
1244     // If status was serialize stall
1245     //     check if ROB is empty and no insts are in flight to the ROB
1246
1247     readFreeEntries(tid);
1248     readStallSignals(tid);
1249
1250     if (fromCommit->commitInfo[tid].squash) {
1251         DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1252                 "commit.\n", tid);
1253
1254         squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1255
1256         return true;
1257     }
1258
1259     if (fromCommit->commitInfo[tid].robSquashing) {
1260         DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1261
1262         renameStatus[tid] = Squashing;
1263
1264         return true;
1265     }
1266
1267     if (checkStall(tid)) {
1268         return block(tid);
1269     }
1270
1271     if (renameStatus[tid] == Blocked) {
1272         DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1273                 tid);
1274
1275         renameStatus[tid] = Unblocking;
1276
1277         unblock(tid);
1278
1279         return true;
1280     }
1281
1282     if (renameStatus[tid] == Squashing) {
1283         // Switch status to running if rename isn't being told to block or
1284         // squash this cycle.
1285         if (resumeSerialize) {
1286             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1287                     tid);
1288
1289             renameStatus[tid] = SerializeStall;
1290             return true;
1291         } else if (resumeUnblocking) {
1292             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1293                     tid);
1294             renameStatus[tid] = Unblocking;
1295             return true;
1296         } else {
1297             DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1298                     tid);
1299
1300             renameStatus[tid] = Running;
1301             return false;
1302         }
1303     }
1304
1305     if (renameStatus[tid] == SerializeStall) {
1306         // Stall ends once the ROB is free.
1307         DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1308                 "unblocking.\n", tid);
1309
1310         DynInstPtr serial_inst = serializeInst[tid];
1311
1312         renameStatus[tid] = Unblocking;
1313
1314         unblock(tid);
1315
1316         DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1317                 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1318
1319         // Put instruction into queue here.
1320         serial_inst->clearSerializeBefore();
1321
1322         if (!skidBuffer[tid].empty()) {
1323             skidBuffer[tid].push_front(serial_inst);
1324         } else {
1325             insts[tid].push_front(serial_inst);
1326         }
1327
1328         DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1329                 " Adding to front of list.\n", tid);
1330
1331         serializeInst[tid] = NULL;
1332
1333         return true;
1334     }
1335
1336     // If we've reached this point, we have not gotten any signals that
1337     // cause rename to change its status.  Rename remains the same as before.
1338     return false;
1339 }
1340
1341 template<class Impl>
1342 void
1343 DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1344 {
1345     if (inst_list.empty()) {
1346         // Mark a bit to say that I must serialize on the next instruction.
1347         serializeOnNextInst[tid] = true;
1348         return;
1349     }
1350
1351     // Set the next instruction as serializing.
1352     inst_list.front()->setSerializeBefore();
1353 }
1354
1355 template <class Impl>
1356 inline void
1357 DefaultRename<Impl>::incrFullStat(const FullSource &source)
1358 {
1359     switch (source) {
1360       case ROB:
1361         ++renameROBFullEvents;
1362         break;
1363       case IQ:
1364         ++renameIQFullEvents;
1365         break;
1366       case LSQ:
1367         ++renameLSQFullEvents;
1368         break;
1369       default:
1370         panic("Rename full stall stat should be incremented for a reason!");
1371         break;
1372     }
1373 }
1374
1375 template <class Impl>
1376 void
1377 DefaultRename<Impl>::dumpHistory()
1378 {
1379     typename std::list<RenameHistory>::iterator buf_it;
1380
1381     for (ThreadID tid = 0; tid < numThreads; tid++) {
1382
1383         buf_it = historyBuffer[tid].begin();
1384
1385         while (buf_it != historyBuffer[tid].end()) {
1386             cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1387                     "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1388                     (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1389
1390             buf_it++;
1391         }
1392     }
1393 }