2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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34 #include "arch/isa_traits.hh"
35 #include "arch/regfile.hh"
36 #include "config/full_system.hh"
37 #include "cpu/o3/rename.hh"
40 DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
42 iewToRenameDelay(params->iewToRenameDelay),
43 decodeToRenameDelay(params->decodeToRenameDelay),
44 commitToRenameDelay(params->commitToRenameDelay),
45 renameWidth(params->renameWidth),
46 commitWidth(params->commitWidth),
47 resumeSerialize(false),
48 resumeUnblocking(false),
49 numThreads(params->numberOfThreads),
50 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
54 for (int i=0; i< numThreads; i++) {
55 renameStatus[i] = Idle;
57 freeEntries[i].iqEntries = 0;
58 freeEntries[i].lsqEntries = 0;
59 freeEntries[i].robEntries = 0;
61 stalls[i].iew = false;
62 stalls[i].commit = false;
63 serializeInst[i] = NULL;
65 instsInProgress[i] = 0;
69 serializeOnNextInst[i] = false;
72 // @todo: Make into a parameter.
73 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
78 DefaultRename<Impl>::name() const
80 return cpu->name() + ".rename";
85 DefaultRename<Impl>::regStats()
88 .name(name() + ".RENAME:SquashCycles")
89 .desc("Number of cycles rename is squashing")
90 .prereq(renameSquashCycles);
92 .name(name() + ".RENAME:IdleCycles")
93 .desc("Number of cycles rename is idle")
94 .prereq(renameIdleCycles);
96 .name(name() + ".RENAME:BlockCycles")
97 .desc("Number of cycles rename is blocking")
98 .prereq(renameBlockCycles);
99 renameSerializeStallCycles
100 .name(name() + ".RENAME:serializeStallCycles")
101 .desc("count of cycles rename stalled for serializing inst")
102 .flags(Stats::total);
104 .name(name() + ".RENAME:RunCycles")
105 .desc("Number of cycles rename is running")
106 .prereq(renameIdleCycles);
108 .name(name() + ".RENAME:UnblockCycles")
109 .desc("Number of cycles rename is unblocking")
110 .prereq(renameUnblockCycles);
112 .name(name() + ".RENAME:RenamedInsts")
113 .desc("Number of instructions processed by rename")
114 .prereq(renameRenamedInsts);
116 .name(name() + ".RENAME:SquashedInsts")
117 .desc("Number of squashed instructions processed by rename")
118 .prereq(renameSquashedInsts);
120 .name(name() + ".RENAME:ROBFullEvents")
121 .desc("Number of times rename has blocked due to ROB full")
122 .prereq(renameROBFullEvents);
124 .name(name() + ".RENAME:IQFullEvents")
125 .desc("Number of times rename has blocked due to IQ full")
126 .prereq(renameIQFullEvents);
128 .name(name() + ".RENAME:LSQFullEvents")
129 .desc("Number of times rename has blocked due to LSQ full")
130 .prereq(renameLSQFullEvents);
131 renameFullRegistersEvents
132 .name(name() + ".RENAME:FullRegisterEvents")
133 .desc("Number of times there has been no free registers")
134 .prereq(renameFullRegistersEvents);
135 renameRenamedOperands
136 .name(name() + ".RENAME:RenamedOperands")
137 .desc("Number of destination operands rename has renamed")
138 .prereq(renameRenamedOperands);
140 .name(name() + ".RENAME:RenameLookups")
141 .desc("Number of register rename lookups that rename has made")
142 .prereq(renameRenameLookups);
144 .name(name() + ".RENAME:CommittedMaps")
145 .desc("Number of HB maps that are committed")
146 .prereq(renameCommittedMaps);
148 .name(name() + ".RENAME:UndoneMaps")
149 .desc("Number of HB maps that are undone due to squashing")
150 .prereq(renameUndoneMaps);
152 .name(name() + ".RENAME:serializingInsts")
153 .desc("count of serializing insts renamed")
156 renamedTempSerializing
157 .name(name() + ".RENAME:tempSerializingInsts")
158 .desc("count of temporary serializing insts renamed")
162 .name(name() + ".RENAME:skidInsts")
163 .desc("count of insts added to the skid buffer")
168 template <class Impl>
170 DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
174 // Setup wire to read information from time buffer, from IEW stage.
175 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
177 // Setup wire to read infromation from time buffer, from commit stage.
178 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
180 // Setup wire to write information to previous stages.
181 toDecode = timeBuffer->getWire(0);
184 template <class Impl>
186 DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
188 renameQueue = rq_ptr;
190 // Setup wire to write information to future stages.
191 toIEW = renameQueue->getWire(0);
194 template <class Impl>
196 DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
198 decodeQueue = dq_ptr;
200 // Setup wire to get information from decode.
201 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
204 template <class Impl>
206 DefaultRename<Impl>::initStage()
208 // Grab the number of free entries directly from the stages.
209 for (int tid=0; tid < numThreads; tid++) {
210 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
211 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
212 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
213 emptyROB[tid] = true;
219 DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
221 activeThreads = at_ptr;
225 template <class Impl>
227 DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
229 for (int i=0; i<numThreads; i++) {
230 renameMap[i] = &rm_ptr[i];
234 template <class Impl>
236 DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
243 DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
245 scoreboard = _scoreboard;
248 template <class Impl>
250 DefaultRename<Impl>::drain()
252 // Rename is ready to switch out at any time.
253 cpu->signalDrained();
257 template <class Impl>
259 DefaultRename<Impl>::switchOut()
261 // Clear any state, fix up the rename map.
262 for (int i = 0; i < numThreads; i++) {
263 typename std::list<RenameHistory>::iterator hb_it =
264 historyBuffer[i].begin();
266 while (!historyBuffer[i].empty()) {
267 assert(hb_it != historyBuffer[i].end());
269 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
270 "number %i.\n", i, (*hb_it).instSeqNum);
272 // Tell the rename map to set the architected register to the
273 // previous physical register that it was renamed to.
274 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
276 // Put the renamed physical register back on the free list.
277 freeList->addReg(hb_it->newPhysReg);
279 // Be sure to mark its register as ready if it's a misc register.
280 if (hb_it->newPhysReg >= maxPhysicalRegs) {
281 scoreboard->setReg(hb_it->newPhysReg);
284 historyBuffer[i].erase(hb_it++);
287 skidBuffer[i].clear();
291 template <class Impl>
293 DefaultRename<Impl>::takeOverFrom()
298 // Reset all state prior to taking over from the other CPU.
299 for (int i=0; i< numThreads; i++) {
300 renameStatus[i] = Idle;
302 stalls[i].iew = false;
303 stalls[i].commit = false;
304 serializeInst[i] = NULL;
306 instsInProgress[i] = 0;
310 serializeOnNextInst[i] = false;
314 template <class Impl>
316 DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
318 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
320 // Clear the stall signal if rename was blocked or unblocking before.
321 // If it still needs to block, the blocking should happen the next
322 // cycle and there should be space to hold everything due to the squash.
323 if (renameStatus[tid] == Blocked ||
324 renameStatus[tid] == Unblocking) {
325 toDecode->renameUnblock[tid] = 1;
327 resumeSerialize = false;
328 serializeInst[tid] = NULL;
329 } else if (renameStatus[tid] == SerializeStall) {
330 if (serializeInst[tid]->seqNum <= squash_seq_num) {
331 DPRINTF(Rename, "Rename will resume serializing after squash\n");
332 resumeSerialize = true;
333 assert(serializeInst[tid]);
335 resumeSerialize = false;
336 toDecode->renameUnblock[tid] = 1;
338 serializeInst[tid] = NULL;
342 // Set the status to Squashing.
343 renameStatus[tid] = Squashing;
345 // Squash any instructions from decode.
346 unsigned squashCount = 0;
348 for (int i=0; i<fromDecode->size; i++) {
349 if (fromDecode->insts[i]->threadNumber == tid &&
350 fromDecode->insts[i]->seqNum > squash_seq_num) {
351 fromDecode->insts[i]->setSquashed();
352 wroteToTimeBuffer = true;
358 // Clear the instruction list and skid buffer in case they have any
362 // Clear the skid buffer in case it has any data in it.
363 skidBuffer[tid].clear();
365 doSquash(squash_seq_num, tid);
368 template <class Impl>
370 DefaultRename<Impl>::tick()
372 wroteToTimeBuffer = false;
374 blockThisCycle = false;
376 bool status_change = false;
382 std::list<unsigned>::iterator threads = activeThreads->begin();
383 std::list<unsigned>::iterator end = activeThreads->end();
385 // Check stall and squash signals.
386 while (threads != end) {
387 unsigned tid = *threads++;
389 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
391 status_change = checkSignalsAndUpdate(tid) || status_change;
393 rename(status_change, tid);
400 if (wroteToTimeBuffer) {
401 DPRINTF(Activity, "Activity this cycle.\n");
402 cpu->activityThisCycle();
405 threads = activeThreads->begin();
407 while (threads != end) {
408 unsigned tid = *threads++;
410 // If we committed this cycle then doneSeqNum will be > 0
411 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
412 !fromCommit->commitInfo[tid].squash &&
413 renameStatus[tid] != Squashing) {
415 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
420 // @todo: make into updateProgress function
421 for (int tid=0; tid < numThreads; tid++) {
422 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
424 assert(instsInProgress[tid] >=0);
431 DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
433 // If status is Running or idle,
434 // call renameInsts()
435 // If status is Unblocking,
436 // buffer any instructions coming from decode
437 // continue trying to empty skid buffer
438 // check if stall conditions have passed
440 if (renameStatus[tid] == Blocked) {
442 } else if (renameStatus[tid] == Squashing) {
443 ++renameSquashCycles;
444 } else if (renameStatus[tid] == SerializeStall) {
445 ++renameSerializeStallCycles;
446 // If we are currently in SerializeStall and resumeSerialize
447 // was set, then that means that we are resuming serializing
448 // this cycle. Tell the previous stages to block.
449 if (resumeSerialize) {
450 resumeSerialize = false;
452 toDecode->renameUnblock[tid] = false;
454 } else if (renameStatus[tid] == Unblocking) {
455 if (resumeUnblocking) {
457 resumeUnblocking = false;
458 toDecode->renameUnblock[tid] = false;
462 if (renameStatus[tid] == Running ||
463 renameStatus[tid] == Idle) {
464 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
468 } else if (renameStatus[tid] == Unblocking) {
472 // Add the current inputs to the skid buffer so they can be
473 // reprocessed when this stage unblocks.
477 // If we switched over to blocking, then there's a potential for
478 // an overall status change.
479 status_change = unblock(tid) || status_change || blockThisCycle;
483 template <class Impl>
485 DefaultRename<Impl>::renameInsts(unsigned tid)
487 // Instructions can be either in the skid buffer or the queue of
488 // instructions coming from decode, depending on the status.
489 int insts_available = renameStatus[tid] == Unblocking ?
490 skidBuffer[tid].size() : insts[tid].size();
492 // Check the decode queue to see if instructions are available.
493 // If there are no available instructions to rename, then do nothing.
494 if (insts_available == 0) {
495 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
497 // Should I change status to idle?
500 } else if (renameStatus[tid] == Unblocking) {
501 ++renameUnblockCycles;
502 } else if (renameStatus[tid] == Running) {
508 // Will have to do a different calculation for the number of free
510 int free_rob_entries = calcFreeROBEntries(tid);
511 int free_iq_entries = calcFreeIQEntries(tid);
512 int free_lsq_entries = calcFreeLSQEntries(tid);
513 int min_free_entries = free_rob_entries;
515 FullSource source = ROB;
517 if (free_iq_entries < min_free_entries) {
518 min_free_entries = free_iq_entries;
522 if (free_lsq_entries < min_free_entries) {
523 min_free_entries = free_lsq_entries;
527 // Check if there's any space left.
528 if (min_free_entries <= 0) {
529 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
531 "ROB has %i free entries.\n"
532 "IQ has %i free entries.\n"
533 "LSQ has %i free entries.\n",
539 blockThisCycle = true;
543 incrFullStat(source);
546 } else if (min_free_entries < insts_available) {
547 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
548 "%i insts available, but only %i insts can be "
549 "renamed due to ROB/IQ/LSQ limits.\n",
550 tid, insts_available, min_free_entries);
552 insts_available = min_free_entries;
554 blockThisCycle = true;
556 incrFullStat(source);
559 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
560 skidBuffer[tid] : insts[tid];
562 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
563 "send iew.\n", tid, insts_available);
565 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
566 "dispatched to IQ last cycle.\n",
567 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
569 // Handle serializing the next instruction if necessary.
570 if (serializeOnNextInst[tid]) {
571 if (emptyROB[tid] && instsInProgress[tid] == 0) {
572 // ROB already empty; no need to serialize.
573 serializeOnNextInst[tid] = false;
574 } else if (!insts_to_rename.empty()) {
575 insts_to_rename.front()->setSerializeBefore();
579 int renamed_insts = 0;
581 while (insts_available > 0 && toIEWIndex < renameWidth) {
582 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
584 assert(!insts_to_rename.empty());
586 inst = insts_to_rename.front();
588 insts_to_rename.pop_front();
590 if (renameStatus[tid] == Unblocking) {
591 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
593 tid, inst->seqNum, inst->readPC());
596 if (inst->isSquashed()) {
597 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
598 "squashed, skipping.\n",
599 tid, inst->seqNum, inst->readPC());
601 ++renameSquashedInsts;
603 // Decrement how many instructions are available.
609 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
611 tid, inst->seqNum, inst->readPC());
613 // Handle serializeAfter/serializeBefore instructions.
614 // serializeAfter marks the next instruction as serializeBefore.
615 // serializeBefore makes the instruction wait in rename until the ROB
618 // In this model, IPR accesses are serialize before
619 // instructions, and store conditionals are serialize after
620 // instructions. This is mainly due to lack of support for
621 // out-of-order operations of either of those classes of
623 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
624 !inst->isSerializeHandled()) {
625 DPRINTF(Rename, "Serialize before instruction encountered.\n");
627 if (!inst->isTempSerializeBefore()) {
628 renamedSerializing++;
629 inst->setSerializeHandled();
631 renamedTempSerializing++;
634 // Change status over to SerializeStall so that other stages know
635 // what this is blocked on.
636 renameStatus[tid] = SerializeStall;
638 serializeInst[tid] = inst;
640 blockThisCycle = true;
643 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
644 !inst->isSerializeHandled()) {
645 DPRINTF(Rename, "Serialize after instruction encountered.\n");
647 renamedSerializing++;
649 inst->setSerializeHandled();
651 serializeAfter(insts_to_rename, tid);
654 // Check here to make sure there are enough destination registers
655 // to rename to. Otherwise block.
656 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
657 DPRINTF(Rename, "Blocking due to lack of free "
658 "physical registers to rename to.\n");
659 blockThisCycle = true;
660 insts_to_rename.push_front(inst);
661 ++renameFullRegistersEvents;
666 renameSrcRegs(inst, inst->threadNumber);
668 renameDestRegs(inst, inst->threadNumber);
672 // Put instruction in rename queue.
673 toIEW->insts[toIEWIndex] = inst;
676 // Increment which instruction we're on.
679 // Decrement how many instructions are available.
683 instsInProgress[tid] += renamed_insts;
684 renameRenamedInsts += renamed_insts;
686 // If we wrote to the time buffer, record this.
688 wroteToTimeBuffer = true;
691 // Check if there's any instructions left that haven't yet been renamed.
693 if (insts_available) {
694 blockThisCycle = true;
697 if (blockThisCycle) {
699 toDecode->renameUnblock[tid] = false;
705 DefaultRename<Impl>::skidInsert(unsigned tid)
707 DynInstPtr inst = NULL;
709 while (!insts[tid].empty()) {
710 inst = insts[tid].front();
712 insts[tid].pop_front();
714 assert(tid == inst->threadNumber);
716 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
717 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
721 skidBuffer[tid].push_back(inst);
724 if (skidBuffer[tid].size() > skidBufferMax)
726 typename InstQueue::iterator it;
727 warn("Skidbuffer contents:\n");
728 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
730 warn("[tid:%u]: %s [sn:%i].\n", tid,
731 (*it)->staticInst->disassemble(inst->readPC()),
734 panic("Skidbuffer Exceeded Max Size");
738 template <class Impl>
740 DefaultRename<Impl>::sortInsts()
742 int insts_from_decode = fromDecode->size;
744 for (int i=0; i < numThreads; i++)
745 assert(insts[i].empty());
747 for (int i = 0; i < insts_from_decode; ++i) {
748 DynInstPtr inst = fromDecode->insts[i];
749 insts[inst->threadNumber].push_back(inst);
755 DefaultRename<Impl>::skidsEmpty()
757 std::list<unsigned>::iterator threads = activeThreads->begin();
758 std::list<unsigned>::iterator end = activeThreads->end();
760 while (threads != end) {
761 unsigned tid = *threads++;
763 if (!skidBuffer[tid].empty())
772 DefaultRename<Impl>::updateStatus()
774 bool any_unblocking = false;
776 std::list<unsigned>::iterator threads = activeThreads->begin();
777 std::list<unsigned>::iterator end = activeThreads->end();
779 while (threads != end) {
780 unsigned tid = *threads++;
782 if (renameStatus[tid] == Unblocking) {
783 any_unblocking = true;
788 // Rename will have activity if it's unblocking.
789 if (any_unblocking) {
790 if (_status == Inactive) {
793 DPRINTF(Activity, "Activating stage.\n");
795 cpu->activateStage(O3CPU::RenameIdx);
798 // If it's not unblocking, then rename will not have any internal
799 // activity. Switch it to inactive.
800 if (_status == Active) {
802 DPRINTF(Activity, "Deactivating stage.\n");
804 cpu->deactivateStage(O3CPU::RenameIdx);
809 template <class Impl>
811 DefaultRename<Impl>::block(unsigned tid)
813 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
815 // Add the current inputs onto the skid buffer, so they can be
816 // reprocessed when this stage unblocks.
819 // Only signal backwards to block if the previous stages do not think
820 // rename is already blocked.
821 if (renameStatus[tid] != Blocked) {
822 // If resumeUnblocking is set, we unblocked during the squash,
823 // but now we're have unblocking status. We need to tell earlier
825 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
826 toDecode->renameBlock[tid] = true;
827 toDecode->renameUnblock[tid] = false;
828 wroteToTimeBuffer = true;
831 // Rename can not go from SerializeStall to Blocked, otherwise
832 // it would not know to complete the serialize stall.
833 if (renameStatus[tid] != SerializeStall) {
834 // Set status to Blocked.
835 renameStatus[tid] = Blocked;
843 template <class Impl>
845 DefaultRename<Impl>::unblock(unsigned tid)
847 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
849 // Rename is done unblocking if the skid buffer is empty.
850 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
852 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
854 toDecode->renameUnblock[tid] = true;
855 wroteToTimeBuffer = true;
857 renameStatus[tid] = Running;
864 template <class Impl>
866 DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
868 typename std::list<RenameHistory>::iterator hb_it =
869 historyBuffer[tid].begin();
871 // After a syscall squashes everything, the history buffer may be empty
872 // but the ROB may still be squashing instructions.
873 if (historyBuffer[tid].empty()) {
877 // Go through the most recent instructions, undoing the mappings
878 // they did and freeing up the registers.
879 while (!historyBuffer[tid].empty() &&
880 (*hb_it).instSeqNum > squashed_seq_num) {
881 assert(hb_it != historyBuffer[tid].end());
883 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
884 "number %i.\n", tid, (*hb_it).instSeqNum);
886 // Tell the rename map to set the architected register to the
887 // previous physical register that it was renamed to.
888 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
890 // Put the renamed physical register back on the free list.
891 freeList->addReg(hb_it->newPhysReg);
893 // Be sure to mark its register as ready if it's a misc register.
894 if (hb_it->newPhysReg >= maxPhysicalRegs) {
895 scoreboard->setReg(hb_it->newPhysReg);
898 historyBuffer[tid].erase(hb_it++);
906 DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
908 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
909 "history buffer %u (size=%i), until [sn:%lli].\n",
910 tid, tid, historyBuffer[tid].size(), inst_seq_num);
912 typename std::list<RenameHistory>::iterator hb_it =
913 historyBuffer[tid].end();
917 if (historyBuffer[tid].empty()) {
918 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
920 } else if (hb_it->instSeqNum > inst_seq_num) {
921 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
922 "that a syscall happened recently.\n", tid);
926 // Commit all the renames up until (and including) the committed sequence
927 // number. Some or even all of the committed instructions may not have
928 // rename histories if they did not have destination registers that were
930 while (!historyBuffer[tid].empty() &&
931 hb_it != historyBuffer[tid].end() &&
932 (*hb_it).instSeqNum <= inst_seq_num) {
934 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
936 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
938 freeList->addReg((*hb_it).prevPhysReg);
939 ++renameCommittedMaps;
941 historyBuffer[tid].erase(hb_it--);
945 template <class Impl>
947 DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
949 assert(renameMap[tid] != 0);
951 unsigned num_src_regs = inst->numSrcRegs();
953 // Get the architectual register numbers from the source and
954 // destination operands, and redirect them to the right register.
955 // Will need to mark dependencies though.
956 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
957 RegIndex src_reg = inst->srcRegIdx(src_idx);
958 RegIndex flat_src_reg = src_reg;
959 if (src_reg < TheISA::FP_Base_DepTag) {
960 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
961 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
963 // Floating point and Miscellaneous registers need their indexes
964 // adjusted to account for the expanded number of flattened int regs.
965 flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
966 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
969 inst->flattenSrcReg(src_idx, flat_src_reg);
971 // Look up the source registers to get the phys. register they've
972 // been renamed to, and set the sources to those registers.
973 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
975 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
976 "physical reg %i.\n", tid, (int)flat_src_reg,
979 inst->renameSrcReg(src_idx, renamed_reg);
981 // See if the register is ready or not.
982 if (scoreboard->getReg(renamed_reg) == true) {
983 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg);
985 inst->markSrcRegReady(src_idx);
987 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg);
990 ++renameRenameLookups;
994 template <class Impl>
996 DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
998 typename RenameMap::RenameInfo rename_result;
1000 unsigned num_dest_regs = inst->numDestRegs();
1002 // Rename the destination registers.
1003 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1004 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1005 RegIndex flat_dest_reg = dest_reg;
1006 if (dest_reg < TheISA::FP_Base_DepTag) {
1007 // Integer registers are flattened.
1008 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1009 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1011 // Floating point and Miscellaneous registers need their indexes
1012 // adjusted to account for the expanded number of flattened int regs.
1013 flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1014 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
1017 inst->flattenDestReg(dest_idx, flat_dest_reg);
1019 // Get the physical register that the destination will be
1021 rename_result = renameMap[tid]->rename(flat_dest_reg);
1023 //Mark Scoreboard entry as not ready
1024 scoreboard->unsetReg(rename_result.first);
1026 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1027 "reg %i.\n", tid, (int)flat_dest_reg,
1028 (int)rename_result.first);
1030 // Record the rename information so that a history can be kept.
1031 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1032 rename_result.first,
1033 rename_result.second);
1035 historyBuffer[tid].push_front(hb_entry);
1037 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1038 "(size=%i), [sn:%lli].\n",tid,
1039 historyBuffer[tid].size(),
1040 (*historyBuffer[tid].begin()).instSeqNum);
1042 // Tell the instruction to rename the appropriate destination
1043 // register (dest_idx) to the new physical register
1044 // (rename_result.first), and record the previous physical
1045 // register that the same logical register was renamed to
1046 // (rename_result.second).
1047 inst->renameDestReg(dest_idx,
1048 rename_result.first,
1049 rename_result.second);
1051 ++renameRenamedOperands;
1055 template <class Impl>
1057 DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1059 int num_free = freeEntries[tid].robEntries -
1060 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1062 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1067 template <class Impl>
1069 DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1071 int num_free = freeEntries[tid].iqEntries -
1072 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1074 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1079 template <class Impl>
1081 DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1083 int num_free = freeEntries[tid].lsqEntries -
1084 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1086 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1091 template <class Impl>
1093 DefaultRename<Impl>::validInsts()
1095 unsigned inst_count = 0;
1097 for (int i=0; i<fromDecode->size; i++) {
1098 if (!fromDecode->insts[i]->isSquashed())
1105 template <class Impl>
1107 DefaultRename<Impl>::readStallSignals(unsigned tid)
1109 if (fromIEW->iewBlock[tid]) {
1110 stalls[tid].iew = true;
1113 if (fromIEW->iewUnblock[tid]) {
1114 assert(stalls[tid].iew);
1115 stalls[tid].iew = false;
1118 if (fromCommit->commitBlock[tid]) {
1119 stalls[tid].commit = true;
1122 if (fromCommit->commitUnblock[tid]) {
1123 assert(stalls[tid].commit);
1124 stalls[tid].commit = false;
1128 template <class Impl>
1130 DefaultRename<Impl>::checkStall(unsigned tid)
1132 bool ret_val = false;
1134 if (stalls[tid].iew) {
1135 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1137 } else if (stalls[tid].commit) {
1138 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1140 } else if (calcFreeROBEntries(tid) <= 0) {
1141 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1143 } else if (calcFreeIQEntries(tid) <= 0) {
1144 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1146 } else if (calcFreeLSQEntries(tid) <= 0) {
1147 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1149 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1150 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1152 } else if (renameStatus[tid] == SerializeStall &&
1153 (!emptyROB[tid] || instsInProgress[tid])) {
1154 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1163 template <class Impl>
1165 DefaultRename<Impl>::readFreeEntries(unsigned tid)
1167 bool updated = false;
1168 if (fromIEW->iewInfo[tid].usedIQ) {
1169 freeEntries[tid].iqEntries =
1170 fromIEW->iewInfo[tid].freeIQEntries;
1174 if (fromIEW->iewInfo[tid].usedLSQ) {
1175 freeEntries[tid].lsqEntries =
1176 fromIEW->iewInfo[tid].freeLSQEntries;
1180 if (fromCommit->commitInfo[tid].usedROB) {
1181 freeEntries[tid].robEntries =
1182 fromCommit->commitInfo[tid].freeROBEntries;
1183 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1187 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1189 freeEntries[tid].iqEntries,
1190 freeEntries[tid].robEntries,
1191 freeEntries[tid].lsqEntries);
1193 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1194 tid, instsInProgress[tid]);
1197 template <class Impl>
1199 DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1201 // Check if there's a squash signal, squash if there is
1202 // Check stall signals, block if necessary.
1203 // If status was blocked
1204 // check if stall conditions have passed
1205 // if so then go to unblocking
1206 // If status was Squashing
1207 // check if squashing is not high. Switch to running this cycle.
1208 // If status was serialize stall
1209 // check if ROB is empty and no insts are in flight to the ROB
1211 readFreeEntries(tid);
1212 readStallSignals(tid);
1214 if (fromCommit->commitInfo[tid].squash) {
1215 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1218 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1223 if (fromCommit->commitInfo[tid].robSquashing) {
1224 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1226 renameStatus[tid] = Squashing;
1231 if (checkStall(tid)) {
1235 if (renameStatus[tid] == Blocked) {
1236 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1239 renameStatus[tid] = Unblocking;
1246 if (renameStatus[tid] == Squashing) {
1247 // Switch status to running if rename isn't being told to block or
1248 // squash this cycle.
1249 if (resumeSerialize) {
1250 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1253 renameStatus[tid] = SerializeStall;
1255 } else if (resumeUnblocking) {
1256 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1258 renameStatus[tid] = Unblocking;
1261 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1264 renameStatus[tid] = Running;
1269 if (renameStatus[tid] == SerializeStall) {
1270 // Stall ends once the ROB is free.
1271 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1272 "unblocking.\n", tid);
1274 DynInstPtr serial_inst = serializeInst[tid];
1276 renameStatus[tid] = Unblocking;
1280 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1282 tid, serial_inst->seqNum, serial_inst->readPC());
1284 // Put instruction into queue here.
1285 serial_inst->clearSerializeBefore();
1287 if (!skidBuffer[tid].empty()) {
1288 skidBuffer[tid].push_front(serial_inst);
1290 insts[tid].push_front(serial_inst);
1293 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1294 " Adding to front of list.\n", tid);
1296 serializeInst[tid] = NULL;
1301 // If we've reached this point, we have not gotten any signals that
1302 // cause rename to change its status. Rename remains the same as before.
1306 template<class Impl>
1308 DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1311 if (inst_list.empty()) {
1312 // Mark a bit to say that I must serialize on the next instruction.
1313 serializeOnNextInst[tid] = true;
1317 // Set the next instruction as serializing.
1318 inst_list.front()->setSerializeBefore();
1321 template <class Impl>
1323 DefaultRename<Impl>::incrFullStat(const FullSource &source)
1327 ++renameROBFullEvents;
1330 ++renameIQFullEvents;
1333 ++renameLSQFullEvents;
1336 panic("Rename full stall stat should be incremented for a reason!");
1341 template <class Impl>
1343 DefaultRename<Impl>::dumpHistory()
1345 typename std::list<RenameHistory>::iterator buf_it;
1347 for (int i = 0; i < numThreads; i++) {
1349 buf_it = historyBuffer[i].begin();
1351 while (buf_it != historyBuffer[i].end()) {
1352 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1353 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1354 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);