src/cpu/o3/rename_map.cc

   1 /*
   2  * Copyright (c) 2016-2018,2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder. You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #include "cpu/o3/rename_map.hh"
  43
  44 #include <vector>
  45
  46 #include "cpu/reg_class.hh"
  47 #include "debug/Rename.hh"
  48
  49 using namespace std;
  50
  51 /**** SimpleRenameMap methods ****/
  52
  53 SimpleRenameMap::SimpleRenameMap()
  54     : freeList(NULL), zeroReg(IntRegClass,0)
  55 {
  56 }
  57
  58
  59 void
  60 SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
  61                       RegIndex _zeroReg)
  62 {
  63     assert(freeList == NULL);
  64     assert(map.empty());
  65
  66     map.resize(size);
  67     freeList = _freeList;
  68     zeroReg = RegId(IntRegClass, _zeroReg);
  69 }
  70
  71 SimpleRenameMap::RenameInfo
  72 SimpleRenameMap::rename(const RegId& arch_reg)
  73 {
  74     PhysRegIdPtr renamed_reg;
  75     // Record the current physical register that is renamed to the
  76     // requested architected register.
  77     PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
  78
  79     if (arch_reg == zeroReg) {
  80         assert(prev_reg->isZeroReg());
  81         renamed_reg = prev_reg;
  82     } else if (prev_reg->getNumPinnedWrites() > 0) {
  83         // Do not rename if the register is pinned
  84         assert(arch_reg.getNumPinnedWrites() == 0);  // Prevent pinning the
  85                                                      // same register twice
  86         DPRINTF(Rename, "Renaming pinned reg, numPinnedWrites %d\n",
  87                 prev_reg->getNumPinnedWrites());
  88         renamed_reg = prev_reg;
  89         renamed_reg->decrNumPinnedWrites();
  90     } else {
  91         renamed_reg = freeList->getReg();
  92         map[arch_reg.flatIndex()] = renamed_reg;
  93         renamed_reg->setNumPinnedWrites(arch_reg.getNumPinnedWrites());
  94         renamed_reg->setNumPinnedWritesToComplete(
  95             arch_reg.getNumPinnedWrites() + 1);
  96     }
  97
  98     DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
  99             " %d (%d)\n",
 100             arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
 101             prev_reg->flatIndex(), prev_reg->flatIndex());
 102
 103     return RenameInfo(renamed_reg, prev_reg);
 104 }
 105
 106
 107 /**** UnifiedRenameMap methods ****/
 108
 109 void
 110 UnifiedRenameMap::init(PhysRegFile *_regFile,
 111                        RegIndex _intZeroReg,
 112                        RegIndex _floatZeroReg,
 113                        UnifiedFreeList *freeList,
 114                        VecMode _mode)
 115 {
 116     regFile = _regFile;
 117     vecMode = _mode;
 118
 119     intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
 120
 121     floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
 122
 123     vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
 124
 125     vecElemMap.init(TheISA::NumVecRegs * NVecElems,
 126             &(freeList->vecElemList), (RegIndex)-1);
 127
 128     predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1);
 129
 130     ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
 131
 132 }
 133
 134 void
 135 UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
 136 {
 137     if (vecMode == Enums::Elem) {
 138
 139         /* The free list should currently be tracking full registers. */
 140         panic_if(freeList->hasFreeVecElems(),
 141                 "The free list is already tracking Vec elems");
 142         panic_if(freeList->numFreeVecRegs() !=
 143                 regFile->numVecPhysRegs() - TheISA::NumVecRegs,
 144                 "The free list has lost vector registers");
 145
 146         /* Split the free regs. */
 147         while (freeList->hasFreeVecRegs()) {
 148             auto vr = freeList->getVecReg();
 149             auto range = this->regFile->getRegElemIds(vr);
 150             freeList->addRegs(range.first, range.second);
 151         }
 152
 153     } else if (vecMode == Enums::Full) {
 154
 155         /* The free list should currently be tracking register elems. */
 156         panic_if(freeList->hasFreeVecRegs(),
 157                 "The free list is already tracking full Vec");
 158         panic_if(freeList->numFreeVecElems() !=
 159                  regFile->numVecElemPhysRegs() -
 160                  TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg,
 161                  "The free list has lost vector register elements");
 162
 163         auto range = regFile->getRegIds(VecRegClass);
 164         freeList->addRegs(range.first + TheISA::NumVecRegs, range.second);
 165
 166         /* We remove the elems from the free list. */
 167         while (freeList->hasFreeVecElems())
 168             freeList->getVecElem();
 169     }
 170 }
 171
 172 void
 173 UnifiedRenameMap::switchMode(VecMode newVecMode)
 174 {
 175     if (newVecMode == Enums::Elem && vecMode == Enums::Full) {
 176
 177         /* Switch to vector element rename mode. */
 178         vecMode = Enums::Elem;
 179
 180         /* Split the mapping of each arch reg. */
 181         int vec_idx = 0;
 182         for (auto &vec: vecMap) {
 183             PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec);
 184             auto idx = 0;
 185             for (auto phys_elem = range.first;
 186                  phys_elem < range.second; idx++, phys_elem++) {
 187
 188                 setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
 189             }
 190             vec_idx++;
 191         }
 192
 193     } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) {
 194
 195         /* Switch to full vector register rename mode. */
 196         vecMode = Enums::Full;
 197
 198         /* To rebuild the arch regs we take the easy road:
 199          *  1.- Stitch the elems together into vectors.
 200          *  2.- Replace the contents of the register file with the vectors
 201          *  3.- Set the remaining registers as free
 202          */
 203         TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
 204         for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
 205             VecReg dst = new_RF[i].as<TheISA::VecElem>();
 206             for (uint32_t l = 0; l < NVecElems; l++) {
 207                 RegId s_rid(VecElemClass, i, l);
 208                 PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
 209                 dst[l] = regFile->readVecElem(s_prid);
 210             }
 211         }
 212
 213         for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
 214             PhysRegId pregId(VecRegClass, i, 0);
 215             regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
 216         }
 217
 218     }
 219 }