2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #ifndef __CPU_O3_ROB_IMPL_HH__
42 #define __CPU_O3_ROB_IMPL_HH__
46 #include "base/logging.hh"
47 #include "cpu/o3/rob.hh"
48 #include "debug/Fetch.hh"
49 #include "debug/ROB.hh"
50 #include "params/DerivO3CPU.hh"
55 ROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params)
56 : robPolicy(params->smtROBPolicy),
58 numEntries(params->numROBEntries),
59 squashWidth(params->squashWidth),
61 numThreads(params->numThreads),
64 //Figure out rob policy
65 if (robPolicy == SMTQueuePolicy::Dynamic) {
66 //Set Max Entries to Total ROB Capacity
67 for (ThreadID tid = 0; tid < numThreads; tid++) {
68 maxEntries[tid] = numEntries;
71 } else if (robPolicy == SMTQueuePolicy::Partitioned) {
72 DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
74 //@todo:make work if part_amt doesnt divide evenly.
75 int part_amt = numEntries / numThreads;
77 //Divide ROB up evenly
78 for (ThreadID tid = 0; tid < numThreads; tid++) {
79 maxEntries[tid] = part_amt;
82 } else if (robPolicy == SMTQueuePolicy::Threshold) {
83 DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
85 int threshold = params->smtROBThreshold;;
87 //Divide up by threshold amount
88 for (ThreadID tid = 0; tid < numThreads; tid++) {
89 maxEntries[tid] = threshold;
93 for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
100 template <class Impl>
102 ROB<Impl>::resetState()
104 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
105 threadEntries[tid] = 0;
106 squashIt[tid] = instList[tid].end();
107 squashedSeqNum[tid] = 0;
108 doneSquashing[tid] = true;
112 // Initialize the "universal" ROB head & tail point to invalid
114 head = instList[0].end();
115 tail = instList[0].end();
118 template <class Impl>
120 ROB<Impl>::name() const
122 return cpu->name() + ".rob";
125 template <class Impl>
127 ROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
129 DPRINTF(ROB, "Setting active threads list pointer.\n");
130 activeThreads = at_ptr;
133 template <class Impl>
135 ROB<Impl>::drainSanityCheck() const
137 for (ThreadID tid = 0; tid < numThreads; tid++)
138 assert(instList[tid].empty());
142 template <class Impl>
144 ROB<Impl>::takeOverFrom()
149 template <class Impl>
151 ROB<Impl>::resetEntries()
153 if (robPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) {
154 auto active_threads = activeThreads->size();
156 list<ThreadID>::iterator threads = activeThreads->begin();
157 list<ThreadID>::iterator end = activeThreads->end();
159 while (threads != end) {
160 ThreadID tid = *threads++;
162 if (robPolicy == SMTQueuePolicy::Partitioned) {
163 maxEntries[tid] = numEntries / active_threads;
164 } else if (robPolicy == SMTQueuePolicy::Threshold &&
165 active_threads == 1) {
166 maxEntries[tid] = numEntries;
172 template <class Impl>
174 ROB<Impl>::entryAmount(ThreadID num_threads)
176 if (robPolicy == SMTQueuePolicy::Partitioned) {
177 return numEntries / num_threads;
183 template <class Impl>
185 ROB<Impl>::countInsts()
189 for (ThreadID tid = 0; tid < numThreads; tid++)
190 total += countInsts(tid);
195 template <class Impl>
197 ROB<Impl>::countInsts(ThreadID tid)
199 return instList[tid].size();
202 template <class Impl>
204 ROB<Impl>::insertInst(const DynInstPtr &inst)
210 DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState());
212 assert(numInstsInROB != numEntries);
214 ThreadID tid = inst->threadNumber;
216 instList[tid].push_back(inst);
218 //Set Up head iterator if this is the 1st instruction in the ROB
219 if (numInstsInROB == 0) {
220 head = instList[tid].begin();
221 assert((*head) == inst);
224 //Must Decrement for iterator to actually be valid since __.end()
225 //actually points to 1 after the last inst
226 tail = instList[tid].end();
232 ++threadEntries[tid];
234 assert((*tail) == inst);
236 DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]);
239 template <class Impl>
241 ROB<Impl>::retireHead(ThreadID tid)
245 assert(numInstsInROB > 0);
247 // Get the head ROB instruction by copying it and remove it from the list
248 InstIt head_it = instList[tid].begin();
250 DynInstPtr head_inst = std::move(*head_it);
251 instList[tid].erase(head_it);
253 assert(head_inst->readyToCommit());
255 DPRINTF(ROB, "[tid:%i] Retiring head instruction, "
256 "instruction PC %s, [sn:%llu]\n", tid, head_inst->pcState(),
260 --threadEntries[tid];
262 head_inst->clearInROB();
263 head_inst->setCommitted();
265 //Update "Global" Head of ROB
268 // @todo: A special case is needed if the instruction being
269 // retired is the only instruction in the ROB; otherwise the tail
270 // iterator will become invalidated.
271 cpu->removeFrontInst(head_inst);
274 template <class Impl>
276 ROB<Impl>::isHeadReady(ThreadID tid)
279 if (threadEntries[tid] != 0) {
280 return instList[tid].front()->readyToCommit();
286 template <class Impl>
288 ROB<Impl>::canCommit()
290 //@todo: set ActiveThreads through ROB or CPU
291 list<ThreadID>::iterator threads = activeThreads->begin();
292 list<ThreadID>::iterator end = activeThreads->end();
294 while (threads != end) {
295 ThreadID tid = *threads++;
297 if (isHeadReady(tid)) {
305 template <class Impl>
307 ROB<Impl>::numFreeEntries()
309 return numEntries - numInstsInROB;
312 template <class Impl>
314 ROB<Impl>::numFreeEntries(ThreadID tid)
316 return maxEntries[tid] - threadEntries[tid];
319 template <class Impl>
321 ROB<Impl>::doSquash(ThreadID tid)
324 DPRINTF(ROB, "[tid:%i] Squashing instructions until [sn:%llu].\n",
325 tid, squashedSeqNum[tid]);
327 assert(squashIt[tid] != instList[tid].end());
329 if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) {
330 DPRINTF(ROB, "[tid:%i] Done squashing instructions.\n",
333 squashIt[tid] = instList[tid].end();
335 doneSquashing[tid] = true;
339 bool robTailUpdate = false;
341 for (int numSquashed = 0;
342 numSquashed < squashWidth &&
343 squashIt[tid] != instList[tid].end() &&
344 (*squashIt[tid])->seqNum > squashedSeqNum[tid];
347 DPRINTF(ROB, "[tid:%i] Squashing instruction PC %s, seq num %i.\n",
348 (*squashIt[tid])->threadNumber,
349 (*squashIt[tid])->pcState(),
350 (*squashIt[tid])->seqNum);
352 // Mark the instruction as squashed, and ready to commit so that
353 // it can drain out of the pipeline.
354 (*squashIt[tid])->setSquashed();
356 (*squashIt[tid])->setCanCommit();
359 if (squashIt[tid] == instList[tid].begin()) {
360 DPRINTF(ROB, "Reached head of instruction list while "
363 squashIt[tid] = instList[tid].end();
365 doneSquashing[tid] = true;
370 InstIt tail_thread = instList[tid].end();
373 if ((*squashIt[tid]) == (*tail_thread))
374 robTailUpdate = true;
380 // Check if ROB is done squashing.
381 if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) {
382 DPRINTF(ROB, "[tid:%i] Done squashing instructions.\n",
385 squashIt[tid] = instList[tid].end();
387 doneSquashing[tid] = true;
396 template <class Impl>
398 ROB<Impl>::updateHead()
400 InstSeqNum lowest_num = 0;
401 bool first_valid = true;
403 // @todo: set ActiveThreads through ROB or CPU
404 list<ThreadID>::iterator threads = activeThreads->begin();
405 list<ThreadID>::iterator end = activeThreads->end();
407 while (threads != end) {
408 ThreadID tid = *threads++;
410 if (instList[tid].empty())
414 head = instList[tid].begin();
415 lowest_num = (*head)->seqNum;
420 InstIt head_thread = instList[tid].begin();
422 DynInstPtr head_inst = (*head_thread);
424 assert(head_inst != 0);
426 if (head_inst->seqNum < lowest_num) {
428 lowest_num = head_inst->seqNum;
433 head = instList[0].end();
438 template <class Impl>
440 ROB<Impl>::updateTail()
442 tail = instList[0].end();
443 bool first_valid = true;
445 list<ThreadID>::iterator threads = activeThreads->begin();
446 list<ThreadID>::iterator end = activeThreads->end();
448 while (threads != end) {
449 ThreadID tid = *threads++;
451 if (instList[tid].empty()) {
455 // If this is the first valid then assign w/out
458 tail = instList[tid].end();
464 // Assign new tail if this thread's tail is younger
465 // than our current "tail high"
466 InstIt tail_thread = instList[tid].end();
469 if ((*tail_thread)->seqNum > (*tail)->seqNum) {
476 template <class Impl>
478 ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid)
481 DPRINTF(ROB, "Does not need to squash due to being empty "
488 DPRINTF(ROB, "Starting to squash within the ROB.\n");
490 robStatus[tid] = ROBSquashing;
492 doneSquashing[tid] = false;
494 squashedSeqNum[tid] = squash_num;
496 if (!instList[tid].empty()) {
497 InstIt tail_thread = instList[tid].end();
500 squashIt[tid] = tail_thread;
506 template <class Impl>
507 const typename Impl::DynInstPtr&
508 ROB<Impl>::readHeadInst(ThreadID tid)
510 if (threadEntries[tid] != 0) {
511 InstIt head_thread = instList[tid].begin();
513 assert((*head_thread)->isInROB());
521 template <class Impl>
522 typename Impl::DynInstPtr
523 ROB<Impl>::readTailInst(ThreadID tid)
525 InstIt tail_thread = instList[tid].end();
531 template <class Impl>
532 ROB<Impl>::ROBStats::ROBStats(Stats::Group *parent)
533 : Stats::Group(parent, "rob"),
534 ADD_STAT(reads, "The number of ROB reads"),
535 ADD_STAT(writes, "The number of ROB writes")
539 template <class Impl>
540 typename Impl::DynInstPtr
541 ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
543 for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) {
544 if ((*it)->seqNum == squash_inst) {
551 #endif//__CPU_O3_ROB_IMPL_HH__